JPH0249133U - - Google Patents
Info
- Publication number
- JPH0249133U JPH0249133U JP12774688U JP12774688U JPH0249133U JP H0249133 U JPH0249133 U JP H0249133U JP 12774688 U JP12774688 U JP 12774688U JP 12774688 U JP12774688 U JP 12774688U JP H0249133 U JPH0249133 U JP H0249133U
- Authority
- JP
- Japan
- Prior art keywords
- wire
- island portion
- conductive pattern
- semiconductor pellet
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000008188 pellet Substances 0.000 claims description 3
- QNRATNLHPGXHMA-XZHTYLCXSA-N (r)-(6-ethoxyquinolin-4-yl)-[(2s,4s,5r)-5-ethyl-1-azabicyclo[2.2.2]octan-2-yl]methanol;hydrochloride Chemical compound Cl.C([C@H]([C@H](C1)CC)C2)CN1[C@@H]2[C@H](O)C1=CC=NC2=CC=C(OCC)C=C21 QNRATNLHPGXHMA-XZHTYLCXSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/0554—External layer
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案の実施例を示す要部透視平面図
、第2図はアイランドへのワイアボンデイングを
示す要部側断面図、第3図乃至第6図は本考案の
効果を説明するアイランド部の平面図で、第3図
及び第5図は本考案と比較される従来のアイラン
ド部、第4図及び第6図は本考案によるアイラン
ド部である。第7図は半導体装置の一例を示す一
部透視平面図、第8図は第7図装置の正断面図で
ある。
1……配線基板、1a……絶縁基板、1b……
導電パターン、1d……アイランド部、4……半
導体ペレツト、5……第1のワイア、6……第2
のワイア。
Fig. 1 is a perspective plan view of the main part showing an embodiment of the present invention, Fig. 2 is a side sectional view of the main part showing wire bonding to the island, and Figs. 3 to 6 are island diagrams illustrating the effects of the present invention. FIGS. 3 and 5 are plan views of the conventional island section compared with the present invention, and FIGS. 4 and 6 are plan views of the island section according to the present invention. FIG. 7 is a partially transparent plan view showing an example of a semiconductor device, and FIG. 8 is a front sectional view of the device shown in FIG. 1... Wiring board, 1a... Insulating board, 1b...
Conductive pattern, 1d... Island portion, 4... Semiconductor pellet, 5... First wire, 6... Second
Wire.
Claims (1)
に半導体ペレツトをマウントし、半導体ペレツト
上の電極と前記導電パターンのアイランド部とを
第1のワイアで接続するとともに、上記第1のワ
イアが接続されたアイランド部に第2のワイアを
接続した半導体装置において、上記第1、第2の
ワイアが接続されるアイランド部を略菱形にした
ことを特徴とする半導体装置。 A semiconductor pellet is mounted on a wiring board having a conductive pattern formed on an insulating substrate, and the electrode on the semiconductor pellet and the island portion of the conductive pattern are connected by a first wire, and the first wire is connected. 1. A semiconductor device in which a second wire is connected to an island portion, wherein the island portion to which the first and second wires are connected has a substantially rhombic shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12774688U JPH0249133U (en) | 1988-09-29 | 1988-09-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12774688U JPH0249133U (en) | 1988-09-29 | 1988-09-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0249133U true JPH0249133U (en) | 1990-04-05 |
Family
ID=31380451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12774688U Pending JPH0249133U (en) | 1988-09-29 | 1988-09-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0249133U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60234335A (en) * | 1984-05-08 | 1985-11-21 | Toshiba Corp | Semiconductor device |
-
1988
- 1988-09-29 JP JP12774688U patent/JPH0249133U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60234335A (en) * | 1984-05-08 | 1985-11-21 | Toshiba Corp | Semiconductor device |