JPS6294673U - - Google Patents
Info
- Publication number
- JPS6294673U JPS6294673U JP18754485U JP18754485U JPS6294673U JP S6294673 U JPS6294673 U JP S6294673U JP 18754485 U JP18754485 U JP 18754485U JP 18754485 U JP18754485 U JP 18754485U JP S6294673 U JPS6294673 U JP S6294673U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- electrically insulating
- constructed
- pattern
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 description 1
Description
図面は本考案の実施例を示し、第１図は一実施
例の平面図、第２図は第１図―線断面図、第
３図は第１図―線断面図、第４図は他の実施
例のＩＣ取付部の断面図、第５図はさらに他の実
施例のＩＣ取付部の断面図である。
１……電気絶縁性基板、２……溝部、６……導
電性ワイヤ。
The drawings show an embodiment of the present invention, and FIG. 1 is a plan view of one embodiment, FIG. 2 is a sectional view taken along the line of FIG. 1, FIG. 3 is a sectional view taken along the line of FIG. FIG. 5 is a cross-sectional view of an IC mounting portion of another embodiment. 1... Electrically insulating substrate, 2... Groove, 6... Conductive wire.
Claims (1)
電性ワイヤを引きまわして回路を構成したことを
特徴とする回路基板。 A circuit board characterized in that a circuit is constructed by routing conductive wires in grooves formed in a pattern on an electrically insulating board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985187544U JPH037971Y2 (en) | 1985-12-05 | 1985-12-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985187544U JPH037971Y2 (en) | 1985-12-05 | 1985-12-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6294673U true JPS6294673U (en) | 1987-06-17 |
| JPH037971Y2 JPH037971Y2 (en) | 1991-02-27 |
Family
ID=31138101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985187544U Expired JPH037971Y2 (en) | 1985-12-05 | 1985-12-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH037971Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010182773A (en) * | 2009-02-04 | 2010-08-19 | Shinko Electric Ind Co Ltd | Wiring substrate, electronic device, and electronic device mounting structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5074970B2 (en) * | 2008-03-21 | 2012-11-14 | 古河電気工業株式会社 | Trough and trough lid |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58165396A (en) * | 1982-03-26 | 1983-09-30 | 富士通電装株式会社 | Method of producing printed board |
-
1985
- 1985-12-05 JP JP1985187544U patent/JPH037971Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58165396A (en) * | 1982-03-26 | 1983-09-30 | 富士通電装株式会社 | Method of producing printed board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010182773A (en) * | 2009-02-04 | 2010-08-19 | Shinko Electric Ind Co Ltd | Wiring substrate, electronic device, and electronic device mounting structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH037971Y2 (en) | 1991-02-27 |