JPH01194340A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH01194340A
JPH01194340A JP63019427A JP1942788A JPH01194340A JP H01194340 A JPH01194340 A JP H01194340A JP 63019427 A JP63019427 A JP 63019427A JP 1942788 A JP1942788 A JP 1942788A JP H01194340 A JPH01194340 A JP H01194340A
Authority
JP
Japan
Prior art keywords
board
printed wiring
wiring board
chip components
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63019427A
Other languages
Japanese (ja)
Inventor
Hideki Obara
小原　東樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63019427A priority Critical patent/JPH01194340A/en
Publication of JPH01194340A publication Critical patent/JPH01194340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

PURPOSE:To avoid crackings produced in a molding process by a method where in semiconductor chips which are mounted on both end parts of a printed wiring board have smaller dimensions than semiconductor chips which are mounted on the center part of the printed wiring board. CONSTITUTION:A printed wiring board 3 on which wiring patterns are formed in mounted on a base board 1 which is molded with leads 2 solidly. Chip components 4a and 4b such as IC's and resistors are mounted on the board 3 and connected to the wiring patterns on the board 3 with bonding wires 5. The chip components 4a on both the end parts of the board 3 are so selected as to have smaller dimensions than the chip components on the center part of the board 3 and all the chip components are so mounted as to be arranged inside an equistrain line 8. In order to make the connection to the outside, the wiring patterns of the board 3 are electrically connected to the leads 2 with bonding wires 6. Then the board 3 is sealed with resin 7 by transfer mold ing. With this constitution, crackings produced in the molding process can be avoided.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to hybrid integrated circuits.

〔従来の技術〕[Conventional technology]

混成集積回路の高集積化の一例としてモノリシックＩＣ
の形状に類似したパッケージのＣＯＭＰＡＣＴ　（登録
商標）があり、量産化に適した構造を有している。Monolithic IC is an example of high integration of hybrid integrated circuits.
There is a package called COMPACT (registered trademark), which is similar in shape to , and has a structure suitable for mass production.

第３図（ａ）、（ｂ）は従来の混成集積回路の例を示す
切欠平面図及びｚ−ｚ’線断面図である。FIGS. 3(a) and 3(b) are a cutaway plan view and a sectional view taken along the line z-z', showing an example of a conventional hybrid integrated circuit.

第３図（ａ）、（ｂ）に示すように、ベース基板１の上
に長方形のプリント配線基板３を固定し、プリント配線
基板３の上に抵抗、ＩＣチップ等のチップ部品４ａ、４
ｂをマウント材で固定して搭載し、チップ部品４ａ、４
ｂとプリント配線基板３の配線パターン及びリード２と
前記配線パターンとの間をボンディング線５．６で電気
的に接続する０次に、チップ部品４ａ、４ｂを含むプリ
ント配線基板３をトランスファモールドした樹脂体７で
封止する。As shown in FIGS. 3(a) and 3(b), a rectangular printed wiring board 3 is fixed on the base board 1, and chip parts 4a, 4 such as resistors and IC chips are placed on the printed wiring board 3.
b is fixed with a mounting material and mounted, and the chip components 4a, 4 are mounted.
b and the wiring pattern of the printed wiring board 3, and the lead 2 and the wiring pattern are electrically connected by bonding wires 5 and 6. Next, the printed wiring board 3 including the chip components 4a and 4b was transfer molded. It is sealed with a resin body 7.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の混成集積回路は、ＩＣチップ等のチップ
部品を多数必要とするメモリ回路等をパッケージ化しよ
うとすると、モールド樹脂が硬化する際のプリント配線
基板３の両端の歪が不均一（図では、等歪線８として示
され、この線の外側に出たチップ部品には、異常な応力
が加わる）になるために、両端に配置したチップ部品に
クラックが生じ、歩留を著しく低下させるという欠点が
ある。In the conventional hybrid integrated circuit described above, when trying to package a memory circuit or the like that requires a large number of chip components such as IC chips, the distortion at both ends of the printed wiring board 3 when the molding resin hardens is uneven (Fig. (This is shown as the equal strain line 8, and abnormal stress is applied to chip components that extend outside this line.) This causes cracks to occur in chip components placed at both ends, significantly reducing yield. There is a drawback.

たとえば、８０Ｘ１５ｍｍ２のプリント配線基板の両端
部に７．５Ｘ７．５龍２のＩＣチップ４ｂを、端部から
３．７５＋ｎｍ離して配置したとき、樹脂体のモールド
化によって、ＩＣチップ４ｂには、等歪線８に沿ってク
ラックが生じ、高密度実装が出来ないという問題点があ
る。For example, when a 7.5 x 7.5 x 2 IC chip 4b is placed at both ends of an 80 x 15 mm 2 printed wiring board at a distance of 3.75+nm from the end, the IC chip 4b is There is a problem in that cracks occur along the strain lines 8 and high-density mounting is not possible.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の混成集積回路は、ベース基板上に固定した長方
形のプリント配線基板と、前記プリント配線基板上に搭
載した半導体チップと、前記半導体チップを含む前記プ
リント配線基板を封止した樹脂体とを含む混成集積回路
において、前記プリント配線基板の両端に搭載し且つ中
央部に搭載した前記半導体チップよりも小寸法である半
導体チップを有している。The hybrid integrated circuit of the present invention includes a rectangular printed wiring board fixed on a base substrate, a semiconductor chip mounted on the printed wiring board, and a resin body encapsulating the printed wiring board including the semiconductor chip. The hybrid integrated circuit includes semiconductor chips mounted on both ends of the printed wiring board and smaller in size than the semiconductor chips mounted in the center.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の第１の実施例を示す切
欠平面図及びｘ−ｘ’線断面図である。FIGS. 1(a) and 1(b) are a cutaway plan view and a sectional view taken along line xx', showing a first embodiment of the present invention.

第１図（ａ）、（ｂ）に示すように、リード２と一体形
成されたベース基板１の上に、配線パターンを形成した
プリント配線基板３を載置し、その上に、ＩＣや抵抗等
のチップ部品４ａ、４ｂをマウントし、ボンディング線
５でプリント配線基板３上の配線パターンと接続する。As shown in FIGS. 1(a) and (b), a printed wiring board 3 on which a wiring pattern is formed is placed on a base board 1 integrally formed with leads 2, and ICs and resistors are placed on top of the printed wiring board 3 on which a wiring pattern is formed. Chip components 4a and 4b such as the above are mounted and connected to the wiring pattern on the printed wiring board 3 with bonding wires 5.

プリント配線基板３の両端のチップ部品４ａは、中央部
のチップ部品４ｂに比べ、チップ寸法の小さなもの（正
方形チップ）が選ばれ、いずれのチップ部品も等歪線８
の内側に入る様に配置されている。たとえば、８０Ｘ１
５ｍＩ＋＋２のプリント配線基板に対して、両端のチッ
プ部品４ａを３．７５Ｘ３．７５ｍ１１２にしである。The chip components 4a at both ends of the printed wiring board 3 are selected to have smaller chip dimensions (square chips) than the chip components 4b at the center, and both chip components are aligned with the equal strain line 8.
It is arranged so that it goes inside. For example, 80X1
For a 5 mI++2 printed wiring board, the chip components 4a at both ends are 3.75 x 3.75 m112.

外部への取り出しはリード２とプリント配線基板３の配
線パターンとの間をボンディング線６により電気的に接
続する。樹脂体７によりプリント配線基板３をトランス
ファーモールドで封止し、通常のＩＣパッケージ類似の
形状とする。To take out to the outside, the leads 2 and the wiring pattern of the printed wiring board 3 are electrically connected by bonding wires 6. The printed wiring board 3 is sealed with the resin body 7 by transfer molding to have a shape similar to a normal IC package.

第２図（ａ）、、（ｂ）は、本発明の第２の実施例を示
す切欠平面図及びＹ−Ｙ’線断面図である。FIGS. 2(a) and 2(b) are a cutaway plan view and a sectional view taken along the line YY', showing a second embodiment of the present invention.

第２図（ａ）、（ｂ）に示すように、リード２と１体形
成されたベース基板１の上に配線パターンを形成したプ
リント配線基板３を載置し、その上にＩＣや抵抗等のチ
ップ部品４ａ、４ｂをマウントし、ボンディング線５で
プリント配線基板３上の配線パターンを接続する。プリ
ント配線基板３の短辺側近傍の両端のチップ部品４ａは
、縦横比の大きな長方形のチップ部品（たとえば、３．
７５Ｘ７＋ｎ＋ａ２）であり、短辺の寸法が、中央部の
チップ部品４ｂ（たとえば７．５Ｘ７．５ｍｍ２）に比
べて小さくなるようにしてあり、いずれのチップ部品も
等歪曲線８の内側に入る様に配置される。外部の取り出
しは、リード２とプリント配線基板３との間をボンディ
ング線６により電気的に接続する。次に、樹脂体７によ
り、プリント配線基板３をトランスファーモールドで封
止し、通常のＩＣパッケージ類似の形状とする。As shown in FIGS. 2(a) and 2(b), a printed wiring board 3 with a wiring pattern formed thereon is placed on a base board 1 formed integrally with leads 2, and ICs, resistors, etc. The chip components 4a and 4b are mounted, and the wiring patterns on the printed wiring board 3 are connected with the bonding wires 5. The chip components 4a at both ends near the short side of the printed wiring board 3 are rectangular chip components with a large aspect ratio (for example, 3.
75×7+n+a2), and the dimensions of the short side are smaller than that of the chip component 4b in the center (for example, 7.5×7.5 mm2), so that all chip components fall inside the iso-strain curve 8. Placed. For external extraction, the leads 2 and the printed wiring board 3 are electrically connected by bonding wires 6. Next, the printed wiring board 3 is sealed with the resin body 7 by transfer molding to form a shape similar to a normal IC package.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、プリント配線基板をトラ
ンスファーモールドした樹脂体で封止する際に生じるベ
ース基板上のプリント配線基板の両端の不均一な歪分布
に対して、両端に配置する半導体素子の寸法を小形化す
ることで半導体素子の割れを軽減できる効果がある。As explained above, the present invention addresses uneven strain distribution at both ends of the printed wiring board on the base substrate that occurs when the printed wiring board is sealed with a transfer-molded resin body. By reducing the size of the semiconductor element, cracking of the semiconductor element can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は本発明の第１の実施例を示す切
欠平面図及びｘ−ｘ’線断面図、第２図（ａ＞、（ｂ）
は本発明の第２の実施例を示す切欠平面図及びＹ−Ｙ’
線断面図、第３図（ａ）。 （ｂ）は従来の混成集積回路の例を示す切欠平面図及び
ｚ−ｚ’線断面図である。 １・・・ベース基板、２・・・リード、３・・・プリン
ト配線基板、４ａ、４ｂ・・・チップ部品、５．６・・
・ボンディング線、７・・・樹脂体、８・・・等歪線。FIGS. 1(a) and (b) are a cutaway plan view and a cross-sectional view taken along the line xx' showing the first embodiment of the present invention, and FIGS. 2(a>, (b))
are a cutaway plan view and YY' showing a second embodiment of the present invention;
Line sectional view, FIG. 3(a). (b) is a cutaway plan view and a sectional view taken along the line zz', showing an example of a conventional hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1... Base board, 2... Lead, 3... Printed wiring board, 4a, 4b... Chip parts, 5.6...
- Bonding wire, 7... Resin body, 8... Equal strain line.

Claims (1)

【特許請求の範囲】[Claims] ベース基板上に固定した長方形のプリント配線基板と、
前記プリント配線基板上に搭載した半導体チップと、前
記半導体チップを含む前記プリント配線基板を封止した
樹脂体とを含む混成集積回路において、前記プリント配
線基板の両端に搭載し且つ中央部に搭載した前記半導体
チップよりも小寸法である半導体チップを有することを
特徴とする混成集積回路。A rectangular printed wiring board fixed on the base board,
In a hybrid integrated circuit including a semiconductor chip mounted on the printed wiring board and a resin body sealing the printed wiring board including the semiconductor chip, the semiconductor chip is mounted on both ends of the printed wiring board and mounted in the center. A hybrid integrated circuit comprising a semiconductor chip having a smaller size than the semiconductor chip.
JP63019427A 1988-01-28 1988-01-28 Hybrid integrated circuit Pending JPH01194340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63019427A JPH01194340A (en) 1988-01-28 1988-01-28 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63019427A JPH01194340A (en) 1988-01-28 1988-01-28 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH01194340A true JPH01194340A (en) 1989-08-04

Family

ID=11998976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63019427A Pending JPH01194340A (en) 1988-01-28 1988-01-28 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH01194340A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575387A (en) * 1980-06-13 1982-01-12 Matsushita Electric Works Ltd Printed circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575387A (en) * 1980-06-13 1982-01-12 Matsushita Electric Works Ltd Printed circuit board

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