JPH01205457A - Systematized semiconductor device - Google Patents

Systematized semiconductor device

Info

Publication number
JPH01205457A
JPH01205457A JP63030231A JP3023188A JPH01205457A JP H01205457 A JPH01205457 A JP H01205457A JP 63030231 A JP63030231 A JP 63030231A JP 3023188 A JP3023188 A JP 3023188A JP H01205457 A JPH01205457 A JP H01205457A
Authority
JP
Japan
Prior art keywords
chips
case
integrated circuit
semiconductor integrated
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63030231A
Other languages
Japanese (ja)
Inventor
Toshio Kondo
近藤　登志夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63030231A priority Critical patent/JPH01205457A/en
Publication of JPH01205457A publication Critical patent/JPH01205457A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To realize miniaturization and low cost products, by closely arranging on a plane a plurality of semiconductor integrated circuit chips having different functions which constitute a system, and mutually connecting each of the chips with conductive material. CONSTITUTION:Semiconductor integrated circuit chips 1 having different functions are closely arranged on a plane. Each of the chips is mutually connected with conductive material, and accommodated in a case. The semiconductor integrated circuit chips having different functions are, for example, as follows; a microprocessor 1a, ROM 1b, RAM 1c and an SIO (series I/O) 1d which constitute a microcomputer. The plurality of chips 1a-1d mentioned above are closely arranged, and each of the chips 1a-1d is mutually connected with bonding wires 2 as conductive material. This unified body is accommodated in a case 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に半導体装置の実装方
法を改良し、システム化した半導体装置間する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor devices, and particularly to improving a method for mounting semiconductor devices and creating a system for semiconductor devices.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置は、１つのケースに１つ半導
体集積回路のチップしか実装できない構造となっていた
。Conventionally, this type of semiconductor device has a structure in which only one semiconductor integrated circuit chip can be mounted in one case.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

」−記のような従来の半導体装置では、１つのケースに
１つ半導体集積回路のチップしか実装できないので、１
つのシステムとしての装置の機能を実現するには、数個
〜数十個の半導体装置が必要になる。半導体装置は、そ
のケースに格納されているチップに対してはるかに大き
く、またケースの端子構造が一般に規格されている。そ
のため、複数個の半導体装置を配列接続して１つのシス
テムを構成する場合、上記端子構造から配列の制限が生
ずることと、ケースの大きさとから、実装パッケージが
大型化になり、高価格になる欠点があった。In conventional semiconductor devices such as those described above, only one semiconductor integrated circuit chip can be mounted in one case.
In order to realize the function of a device as one system, several to several dozen semiconductor devices are required. A semiconductor device is much larger than the chip housed in its case, and the terminal structure of the case is generally standardized. Therefore, when arranging and connecting multiple semiconductor devices to form one system, the above-mentioned terminal structure imposes restrictions on the arrangement, and the size of the case means that the mounting package becomes large and expensive. There were drawbacks.

本発明のｌ」的は上記の欠点を除去し、装置の小型化、
並びに低価格化が可能な半導体装置を提供することにあ
る。The object of the present invention is to eliminate the above-mentioned drawbacks, reduce the size of the device,
Another object of the present invention is to provide a semiconductor device whose cost can be reduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、一つのシステムを構成する異なる機能の複数
個の半導体集積回路のチップを１平面に密接して並べ、
前記チップの相互を導電物質により接続して、１つのケ
ース内に収納したものである。The present invention involves arranging a plurality of semiconductor integrated circuit chips with different functions constituting one system in close proximity on one plane.
The chips are connected to each other by a conductive material and housed in one case.

〔作用〕[Effect]

本発明は、１つのケース内にチップの形で複数個の半導
体集積回路を接続する。チップ自体の面積が小さく、そ
の配置も自由にできるので、装置は小型に形成させるこ
とができる。The present invention connects a plurality of semiconductor integrated circuits in the form of chips within one case. Since the chip itself has a small area and can be freely arranged, the device can be made compact.

〔実施例〕〔Example〕

以下、本発明の一実施例を第１図〜第２図を参照して説
明する。Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2.

第１図は、本発明の一実施例の半導体装置の斜視図で、
第２図に示した構成ブロック図の半導体装置に適用した
ものである。図において、１ａ−１ｄは異なる機能の半
導体集積回路のチップで、例えば１ａがマイクロプロセ
ンサ、■ｂがＲＯＭ、ＩＣかＲＡＭ、１ｄが５ＩＯ（直
列Ｉ　１０）であって、１つのマイクロコンピュータに
なっている。この複数のチップ１ａ〜１ｄを図示したよ
うに密接して並へて、チップ１ａ〜１ｄの相互を導電物
質であるホンディングワイヤ２で相互を接続して、１つ
のケース３内に収納しである。なお、図ではケース第１
図 ３からの端子は図示していないが、このシステムを応用
する場所にそれぞれ相応して、ケーブルもしくはプリン
ト板に接続しやすいように端子構造を定める。FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention.
This is applied to the semiconductor device of the configuration block diagram shown in FIG. In the figure, 1a to 1d are semiconductor integrated circuit chips with different functions, for example, 1a is a microprocessor sensor, b is a ROM, IC or RAM, and 1d is 5IO (series I 10), which can be integrated into one microcomputer. It has become. The plurality of chips 1a to 1d are arranged closely together as shown in the figure, and the chips 1a to 1d are connected to each other with a bonding wire 2 made of a conductive material, and housed in one case 3. be. In addition, in the figure, case 1
Although the terminals from FIG. 3 are not shown, the terminal structure is determined to facilitate connection to a cable or printed circuit board, depending on the location where this system is applied.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の半導体装置は、異なる機
能の半導体集積回路のチップを１平面に密接して並べて
、チップの相互を導電物質により接続して、１つのケー
ス内に収納したので、装置の小型化、並びに低価格化が
可能となる優れた効果がある。As explained above, in the semiconductor device of the present invention, chips of semiconductor integrated circuits with different functions are closely arranged on one plane, the chips are connected to each other by a conductive material, and housed in a single case. This has the excellent effect of making it possible to reduce the size and cost of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の−・実施例の半導体装置の斜視図、第
２図は実施例の構成ブロック図である。 ■ａ〜１ｄ・・・チップ、 ２・・・ポンディングワイヤ、 ３・・・ケース。FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a block diagram of the structure of the embodiment. ■a~1d...Chip, 2...Ponding wire, 3...Case.

Claims (1)

【特許請求の範囲】[Claims] 　一つのシステムを構成する異なる機能の複数個の半導
体集積回路のチップを１平面に密接して並べ、前記チッ
プの相互を導電物質により接続して、１つのケース内に
収納したことを特徴とするシステム化半導体装置。A plurality of semiconductor integrated circuit chips having different functions constituting one system are closely arranged on one plane, the chips are connected to each other by a conductive material, and the chips are housed in one case. Systemized semiconductor equipment.
JP63030231A 1988-02-10 1988-02-10 Systematized semiconductor device Pending JPH01205457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63030231A JPH01205457A (en) 1988-02-10 1988-02-10 Systematized semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63030231A JPH01205457A (en) 1988-02-10 1988-02-10 Systematized semiconductor device

Publications (1)

Publication Number Publication Date
JPH01205457A true JPH01205457A (en) 1989-08-17

Family

ID=12297936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63030231A Pending JPH01205457A (en) 1988-02-10 1988-02-10 Systematized semiconductor device

Country Status (1)

Country Link
JP (1) JPH01205457A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054763A (en) * 1997-10-31 2000-04-25 Oki Electric Industry Co., Ltd. Semiconductor device
US6379998B1 (en) 1986-03-12 2002-04-30 Hitachi, Ltd. Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6379998B1 (en) 1986-03-12 2002-04-30 Hitachi, Ltd. Semiconductor device and method for fabricating the same
US6054763A (en) * 1997-10-31 2000-04-25 Oki Electric Industry Co., Ltd. Semiconductor device

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