JP2000022072A - Multichip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip module which is capable of testing semiconductor chips comprised in an integrated circuit package without increasing parts in number. SOLUTION: Input terminals 12 through which test signals are inputted from outside, a switching circuit 210 which switches a normal mode to a test mode and vice versa, and output terminals 14 through which the output of a first semiconductor chip 2 is monitored outside of the chip are provided in the first semiconductor chip 2, input terminals 15 through which test signals are inputted from outside, output terminals 17 through which the input of a second semiconductor chip 3 is monitored, and a switching circuit 300 which switches a normal mode to a test mode or vice versa are provided in the second semiconductor chip 3, the first semiconductor chip 2 or the second semiconductor chip 3 is tested supplying test signals through the input terminals 11 or the input terminals 15, and a connection between the semiconductor chips 2 and 3 is tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module having a plurality of semiconductor chips mounted on a single package, and more particularly to a multi-chip module having a built-in test device.

[0002]

2. Description of the Related Art In recent years, with the reduction in size and weight of various electronic devices, a so-called multi-chip module in which a plurality of semiconductor chips are incorporated in a single package as a hardware configuration has begun to be adopted. In the case of a multi-chip module, it is very important to test each function of each built-in semiconductor chip. As a multi-chip module having the built-in test device, for example, Japanese Patent Application Laid-Open No. Hei 5-13662 Are known.

A conventional multi-chip module of this type will be described below with reference to the drawings. FIG. 5 is a block diagram showing the configuration of a conventional multi-chip module. In FIG. 5, reference numeral 1 denotes an integrated circuit package, which includes an input terminal group 11, an output terminal group 18, an input / output terminal group 19, and a switching control terminal group 20. Have. Reference numeral 2 denotes a first semiconductor chip having a function A, which has an input terminal group 21 and an output terminal group 24. 3 is a second semiconductor chip having a function B,
It has an input terminal group 31 and an output terminal group 35. Reference numeral 4 denotes a switching chip for connecting and disconnecting the first semiconductor chip 2 and the second semiconductor chip 3, and includes an input terminal group 41, an input / output terminal group 42, a switching control terminal group 43, and an output terminal group 44. . When the switching chip 4 applies the logical level “L, L” to the switching control terminal group 43, the signal input to the input terminal group 41 is output from the output terminal group 44 as it is.
When a logical level “L, H” is applied to the switching control terminal group 43, the signal input to the input / output terminal group 42 is output from the output terminal group 44 as it is. Further, when a logic level “H, L” is applied to the switching control terminal group 43, the signal input to the input terminal group 41 is directly output from the input / output terminal group 42.

[0005] The connection relation of each terminal in FIG. 5 is as follows. That is, the input terminal group 11 of the integrated circuit package 1 and the input terminal group 21 of the first semiconductor chip 2 are connected, and the output terminal group 24 of the first semiconductor chip 2 and the input terminal group 41 of the switching chip 4 are connected. The input / output terminal group 19 of the integrated circuit package 1 and the input / output terminal group 42 of the switching chip 4 are connected, and the switching control terminal group 20 of the integrated circuit package 1 and the switching control terminal group 43 of the switching chip 4 are connected.
Are connected, the output terminal group 44 of the switching chip 4 and the input terminal group 31 of the second semiconductor chip 3 are connected, and the output terminal group 35 of the second semiconductor chip 3 and the output terminal group 18 of the integrated circuit package are connected. Each is connected.

The operation will be described below. When testing the first semiconductor chip 2, first, a logic level “H, L” is applied to the switching control terminal group 20, and then the function of the first semiconductor chip 2 is confirmed to the input terminal group 11. Input test signal. The result of the signal processing performed by the first semiconductor chip 2 is output from the output terminal group 24. Since the switching chip 4 outputs the signal input to the input terminal group 41 as it is from the input / output terminal group 42, the output of the first semiconductor chip 2 is output to the input / output terminal group 19. Therefore, the first semiconductor chip 2 can be tested.

Next, when testing the second semiconductor chip 3, first, the logic level “L,
Then, a test signal for confirming the function of the second semiconductor chip 3 is input to the input / output terminal group 19.
Since the switching chip 4 outputs the signal input to the input / output terminal group 42 as it is from the output terminal group 44, the signal input to the input / output terminal group 19 is output from the second semiconductor chip 3. Input to the input terminal group 31. The result of the signal processing by the second semiconductor chip 3 passes through the output terminal group 35 and is output from the output terminal group 18 of the integrated circuit package 1, so that the second semiconductor chip 3 can be tested.

[0007]

However, in such a configuration, a switching chip is required in addition to the first semiconductor chip and the second semiconductor chip, so that the number of components for forming the integrated circuit package is reduced. There was a problem that it increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip module capable of independently testing a semiconductor chip constituting an integrated circuit package without increasing the number of components. I do.

[0009]

According to the present invention, there is provided a multi-chip module for inputting a test signal and an external terminal for monitoring an output outside the chip together with a terminal for connecting the semiconductor chips to each semiconductor chip. It has an external terminal and switching means for switching between the normal mode and the test mode.

According to the present invention, each semiconductor chip can be tested independently without installing a switching chip in the integrated circuit package, so that the number of components for the test does not increase as in the prior art. The test can be easily performed.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same reference numerals are used for the same portions in the conventional device and each embodiment.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a multichip module according to Embodiment 1 of the present invention. In FIG. 1, 1 is an integrated circuit package, and 2 is built in the integrated circuit package 1. A first semiconductor chip 3 having a function A is a second semiconductor chip having a function B built in the integrated circuit package 1 like the first semiconductor chip 2. The integrated circuit package 1 has an input terminal group 11 and an output terminal group 14 and an output terminal group 18 for externally monitoring the output of the first semiconductor chip. The first semiconductor chip 2 includes an input terminal group 2
1, an output terminal group 24 for outputting a signal to the second semiconductor chip, an output terminal group 25 for monitoring the output,
It has a functional circuit 200. The functional circuit 200 has an input terminal group 201 and an output terminal group 202. The second semiconductor chip 3 has an input terminal group 31 and an output terminal group 35.

The connection relation of each terminal in FIG. 1 is as follows. Input terminal group 11 of integrated circuit package 1
Terminal group 21 of first semiconductor chip 2 and functional circuit 2
00, the output terminal group 202 and the output terminal group 24 of the functional circuit 200, the input terminal group 31 and the monitor output terminal group 25 of the second semiconductor chip 3, and the integrated circuit package 1. Output terminal group 1
4 are connected to each other, and the output terminal group 35 of the second semiconductor chip 3 and the output terminal group 1 of the integrated circuit package 1 are further connected.
8 are connected respectively.

The operation will be described below. In the present embodiment, a case where the first semiconductor chip 2 is tested alone will be described. First, a test signal is input to the input terminal group 11 of the integrated circuit package 1. The input test signal is supplied to the input terminal group 21 of the first semiconductor chip 2.
Is supplied to the functional circuit 200 to perform signal processing corresponding to the test signal, and is output to the output terminal group 202. The signal output from the output terminal group 202 is output to the output terminal group 24 of the first semiconductor chip 2 and simultaneously to the output terminal group 14 of the integrated circuit package 1 through the output terminal group 25. . Therefore, the first semiconductor chip 2 can be tested alone.

As described above, according to the present embodiment, by providing the terminal group for connecting the semiconductor chips in the semiconductor chip and the output terminal group for monitoring the output outside the chip, the conventional switching is realized. A semiconductor chip can be tested alone without using a chip for testing.

(Embodiment 2) FIG. 2 is a block diagram showing a configuration of a multichip module according to Embodiment 2 of the present invention. In FIG. 2, reference numeral 1 denotes an integrated circuit package, and 2 denotes a built-in integrated circuit package. A first semiconductor chip 3 having a function A is a second semiconductor chip having a function B built in the integrated circuit package 1 like the first semiconductor chip 2. The integrated circuit package 1 includes an input terminal group 11, an input terminal group 15 for inputting a test signal to the second semiconductor chip 3, a switching control terminal 16 for selecting a normal mode and a test mode, and an output terminal group 18. Have. The first semiconductor chip 2 has an input terminal group 21 and an output terminal group 24. The second semiconductor chip 3 includes an input terminal group 31 and an input terminal group 3 for inputting a test signal.
2, a switching control terminal 33 for selecting a normal mode and a test mode, an output terminal group 35, a switching circuit 300, and a functional circuit 310. The switching circuit 300 includes the input terminal group 30
1. It has an input terminal group 302 for inputting a test signal, a switching control terminal 303, and an output terminal group 304. Functional circuit 31
0 has an input terminal group 311 and an output terminal group 312.

The connection relation of each terminal in FIG. 2 is as follows. That is, the input terminal group 11 of the integrated circuit package 1 and the input terminal group 21 of the first semiconductor chip 2 are connected, and the output terminal group 24 of the first semiconductor chip 2 and the input terminal group 31 of the second semiconductor chip 3 are connected. And switching circuit 300
Are connected to the input terminal group 301 of the integrated circuit package 1.
Are connected to the input terminal group 15 of the second semiconductor chip 3 and the input terminal group 302 of the switching circuit 300.
The switching control terminal 16 of the integrated circuit package 1, the switching control terminal 33 of the second semiconductor chip 3, and the switching control terminal 303 of the switching circuit 300 are connected, and the output terminal group 304 of the switching circuit 300 and the input terminal group of the functional circuit 310 are connected. The output terminal group 312 of the functional circuit 310, the output terminal group 35 of the second semiconductor chip 3, and the output terminal group 18 of the integrated circuit package 1 are connected to each other.

Here, when the logic level “L” is input to the switching control terminal 303, the switching circuit 300 of the second semiconductor chip 3 outputs the signal input from the input terminal group 301 to the output terminal group 304 as it is. So that
When a logic level “H” is input to the switching control terminal 303, the signal input from the input terminal group 302 is output to the output terminal group 304 as it is.

The operation will be described below. In the present embodiment, a case where the second semiconductor chip 3 is tested alone will be described. First, a logic level “H” is input to the switching control terminal 16 of the integrated circuit package 1.
Next, when a signal for testing the second semiconductor chip 3 is input from the input terminal group 15, the switching circuit 300 of the second semiconductor chip 3 outputs the signal input from the input terminal group 302 to the output terminal group 304 as it is. Since the test signal is output, the test signal input from the input terminal group 15 of the integrated circuit package 1 is input to the functional circuit 310 as it is. The functional circuit 310 performs signal processing corresponding to the input test signal, and outputs the result to an output terminal group 312. The output signal passes through the second semiconductor chip 3 and is output to the output terminal group of the integrated circuit package 1. 18 is output.
Therefore, the first semiconductor chip 2 can be tested alone.

As described above, according to the present embodiment, in a plurality of semiconductor chips built in an integrated circuit package, in addition to an input terminal group for receiving a signal from a preceding semiconductor chip, a test signal for inputting a test signal is provided. By providing the input terminal group and the switching means for switching between the normal mode and the test mode, the semiconductor chip can be tested independently without using a conventional switching chip.

(Embodiment 3) FIG. 3 is a block diagram showing a configuration of a multichip module according to Embodiment 3 of the present invention. In FIG. 3, reference numeral 1 denotes an integrated circuit package, and 2 denotes a built-in integrated circuit package. The first semiconductor chip 3 having the function A is a second semiconductor chip having the function B built in the integrated circuit package 1 like the first semiconductor chip 2. The integrated circuit package 1 includes an input terminal group 11, an input terminal group 12 for inputting a test signal,
It has a switching control terminal 13 for selecting a normal mode and a test mode, an output terminal group 17 for monitoring a signal input to the second semiconductor chip 3, and an output terminal group 18. The first semiconductor chip 2 includes an input terminal group 21, an input terminal group 22 for inputting a test signal, a switching control terminal 23 for selecting a normal mode and a test mode, an output terminal group 24, a function circuit 200, A circuit 210; The functional circuit 200 includes an input terminal group 201 and an output terminal group 2
02. The switching circuit 210 includes an input terminal group 211, an input terminal group 212 for inputting a test signal, and a switching control terminal 21 for selecting a normal mode or a test mode.
3. It has an output terminal group 214. Second semiconductor chip 3
Are input terminal group 31, output terminal group 34 for monitoring an input signal, output terminal group 35, functional circuit 310
Having. The functional circuit 310 includes an input terminal group 311 and an output terminal group 312.

The connection relationship of each terminal in FIG. 3 is as follows. Input terminal group 11 of integrated circuit package 1
Terminal group 21 of first semiconductor chip 2 and functional circuit 2
00 are connected to the output terminal group 202 of the functional circuit 200 and the input terminal group 211 of the switching circuit 210.
Are connected, the input terminal group 12 of the integrated circuit package 1, the input terminal group 22 of the first semiconductor chip 2, and the switching circuit 21
0, the switching control terminal 13 of the integrated circuit package 1, the switching control terminal 23 of the first semiconductor chip 2, and the switching control terminal 213 of the switching circuit 210 are connected, and the output terminal of the switching circuit 210 is connected. Group 214, output terminal group 24 of first semiconductor chip 2, and second semiconductor chip 3
Input terminal group 31 and input terminal group 311 of functional circuit 310
And the output terminal group 34 of the second semiconductor chip 3 and the output terminal group 17 of the integrated circuit package 1 are connected, respectively.
The output terminal group 312 of the functional circuit 310, the output terminal group 35 of the second semiconductor chip 3, and the output terminal group 18 of the integrated circuit package 1 are connected to each other.

Here, the switching circuit 2 of the first semiconductor chip 2
When the logic level “L” is input to the switching control terminal 213, the signal input from the input terminal group 211 is output to the output terminal group 214 as it is, and the logic is input to the switching control terminal 213. When the level “H” is input, the signal input from the input terminal group 212 is output to the output terminal group 214 as it is.

The operation will be described below. In the present embodiment, a case where the connection between the first semiconductor chip 2 and the second semiconductor chip 3 is tested will be described.

First, when a logic level “H” is input to the switching control terminal 13 of the integrated circuit package 1 and an arbitrary signal is input from the input terminal group 12 of the integrated circuit package 1, the switching circuit 210 Since the input signal is output as it is to the output terminal group 214, the signal input from the input terminal group 12 is output as it is from the output terminal group 214 of the switching circuit 210, and the first semiconductor chip 2 Are output to the output terminal group 24. Since this signal can be monitored by the output terminal group 17 of the integrated circuit package 1 as shown, the connection between the first semiconductor chip 2 and the second semiconductor chip 3 can be tested.

As described above, according to the present embodiment, at the connection part of a plurality of semiconductor chips built in the integrated circuit package, the input terminal group for inputting the test signal to the output part of the preceding semiconductor chip is provided. By providing switching means for switching between a normal mode and a test mode, and further providing an output terminal group for monitoring a signal input to an input portion of the next-stage semiconductor chip, the connection between the semiconductor chips can be extremely improved. Easy to test.

(Embodiment 4) FIG. 4 is a block diagram showing a configuration of a multi-chip module according to Embodiment 4 of the present invention.
3 are integrated. In the figure, 1 is an integrated circuit package, 2 is a first semiconductor chip having a function A built in the integrated circuit package 1, and 3 is a function built in the integrated circuit package 1 like the first semiconductor chip 2. B is a second semiconductor chip having B. Integrated circuit package 1
Is an input terminal group 11, an input terminal group 12 for inputting a test signal to the first semiconductor chip 2, a switching control terminal 13 for selecting a normal mode and a test mode, and an output of the first semiconductor chip 2. An output terminal group 14 for monitoring from the outside, an input terminal group 15 for inputting a test signal to the second semiconductor chip 3, a switching control terminal 16 for selecting a normal mode and a test mode, An output terminal group 17 and an output terminal group 18 for monitoring are provided. The first semiconductor chip 2 includes an input terminal group 21,
An input terminal group 22 for inputting a test signal, a switching control terminal 23 for selecting a normal mode and a test mode,
An output terminal group 24, an output terminal group 25 for monitoring the output of the first semiconductor chip 2, a functional circuit 200, and a switching circuit 210 are provided. The functional circuit 200 includes the input terminal group 20
1. An output terminal group 202 is provided. The switching circuit 210 has an input terminal group 211, an input terminal group 212 for inputting a test signal, a switching control terminal 213, and an output terminal group 214. The second semiconductor chip 3 includes an input terminal group 31, an input terminal group 32 for inputting a test signal, a switching control terminal 33 for selecting a normal mode and a test mode, and an output for monitoring an input signal. It has a terminal group 34, an output terminal group 35, a switching circuit 300, and a functional circuit 310.
The switching circuit 300 has an input terminal group 301, an input terminal group 302 for inputting a test signal, a switching control terminal 303, and an output terminal group 304. The functional circuit 310 includes an input terminal group 311 and an output terminal group 312.

The connection relation of each terminal in FIG. 4 is as follows. Input terminal group 11 of integrated circuit package 1
Terminal group 21 of first semiconductor chip 2 and functional circuit 2
00 are connected to the output terminal group 202 of the functional circuit 200 and the input terminal group 21 of the switching circuit 210.
1. The output terminal group 25 of the first semiconductor chip 2 and the output terminal group 14 of the integrated circuit package 1 are connected, and the input terminal group 12 of the integrated circuit package 1 and the input terminal group 22 of the first semiconductor chip 2 are switched. The input terminal group 212 of the circuit 210 is connected to the switching control terminal 13 of the integrated circuit package 1, the switching control terminal 23 of the first semiconductor chip 2, and the switching circuit 2.
10 switching control terminals 213 are connected, and the switching circuit 210
Output terminal group 214, the output terminal group 24 of the first semiconductor chip 2, the input terminal group 31 of the second semiconductor chip 3, the input terminal group 301 and the output terminal group 34 of the switching circuit 300, and the output of the integrated circuit package 1. The terminal group 17 is connected, the input terminal group 15 of the integrated circuit package 1, the input terminal group 32 of the second semiconductor chip 3 and the input terminal group 302 of the switching circuit 300 are connected, and the switching control terminal 16 of the integrated circuit package 1 is connected. And the switching control terminal 33 of the second semiconductor chip 3 and the switching control terminal 303 of the switching circuit 300 are connected. The output terminal group 304 of the switching circuit 300 and the input terminal group 311 of the functional circuit 310 are connected. Output terminal group 3
12, the output terminal group 35 of the second semiconductor chip 3 and the output terminal group 18 of the integrated circuit package 1 are connected respectively.

Here, when the switching circuit 210 of the first semiconductor chip 2 inputs the logic level “L” to the switching control terminal 213, the signal input from the input terminal group 211 is output to the output terminal group 214 as it is. When a logic level “H” is input to the switching control terminal 213, the signal input from the input terminal group 212 is output to the output terminal group 214 as it is. The switching circuit 300 of the second semiconductor chip 3 includes a switching control terminal 30
When a logic level “L” is input to the input terminal group 301,
When the logic level “H” is input to the switching control terminal 303, the signal input from the input terminal group 302 is output as it is to the output terminal group 304. The data is output to the group 304.

The operation will be described below.

First, a case where the first semiconductor chip 2 is tested will be described. When a test signal is input to the input terminal group 11 of the integrated circuit package 1, the input test signal is input to the functional circuit 200 through the input terminal group 21. The functional circuit 200 performs signal processing according to the input test signal, and outputs the signal from the output terminal group 202. The signal output from the output terminal group 202 is output from the output terminal group 14 of the integrated circuit package 1 through the output terminal group 25. Therefore, the first semiconductor chip 2 can be tested.

Next, the case of testing the second semiconductor chip 3 will be described. The logic level “H” is input to the switching control terminal 16. Next, when a test signal is input to the input terminal group 15, the switching circuit 300 outputs the signal input from the input terminal group 302 as it is to the output terminal group 304. The test signal is input to the function circuit 310. Functional circuit 31
0 performs signal processing corresponding to the input test signal,
This is output to the output terminal group 312. Output terminal group 312
Are output from the output terminal group 18 of the integrated circuit package 1 through the output terminal group 35. Therefore, the second semiconductor chip 3 can be tested.

Next, a case of testing the connection between the first semiconductor chip 2 and the second semiconductor chip 3 will be described.
A logic level “H” is input to the switching control terminal 13 and an arbitrary signal is input from the input terminal group 12 of the integrated circuit package 1. Since the switching circuit 210 outputs the signal input from the input terminal group 212 as it is to the output terminal group 214, the signal input from the input terminal group 12 is output directly from the output terminal group 214 of the switching circuit 210. Then, the signal is output to the output terminal group 24 of the first semiconductor chip 2. Further, the signal output from the output terminal group 24 is output from the output terminal group 17 of the integrated circuit package 1 through the input terminal group 31 and the output terminal group 34 of the second semiconductor chip 3. Therefore, the connection between the first semiconductor chip 2 and the second semiconductor chip 3 can be tested.

As described above, according to the present embodiment, the semiconductor chip is provided with the terminal group for connecting the semiconductor chips and the output terminal group for monitoring the output outside the chip. In a plurality of built-in semiconductor chips, in addition to an input terminal group for receiving a signal from a preceding semiconductor chip, an input terminal group for inputting a test signal, and a switching unit for switching between a normal mode and a test mode are provided. Further, at a connection portion of a plurality of semiconductor chips incorporated in the integrated circuit package, an input terminal group for inputting a test signal to an output portion of a preceding semiconductor chip, and a switching means for switching between a normal mode and a test mode are provided. And an output terminal group for monitoring signals input to the input section of the next-stage semiconductor chip. , It is possible to test each semiconductor chip of the integrated circuit package alone, very easy to test the connection between the semiconductor chips.

In the fourth embodiment, the output terminal group 2 for monitoring the output of the first semiconductor chip 1
5, the test is performed by increasing the number of external terminals of the first semiconductor chip 1. However, a switching circuit is provided in the first semiconductor chip 1 to switch to another output terminal group (easy implementation). It is apparent that the number of external terminals can be reduced by sharing these output terminal groups 25 with each other (not shown in each drawing). Similarly, it goes without saying that the input terminal group 32 of the second semiconductor chip 3 can be shared with other input terminal groups.

[0036]

As described above, according to the present invention, each semiconductor chip in an integrated circuit package can be independently tested, and the connection between the semiconductor chips can be very easily tested. Therefore, an advantageous effect that the number of components constituting the multi-chip module can be reduced can be obtained since the switching chip for the above is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a multichip module according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a multichip module according to a second embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a multichip module according to a third embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a multichip module according to a fourth embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a conventional multichip module.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Integrated circuit package 2 1st semiconductor chip 3 2nd semiconductor chip 11,12,15,21,22,31,32,201,
211, 212, 301, 302, 311 Input terminal group 13, 16, 23, 33, 213, 303 Switching control terminal 14, 17, 18, 24, 25, 34, 35, 202,
214, 304, 312 output terminal group 200, 310 functional circuit 210, 300 switching circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/66

Claims (4)

[Claims] 1. An integrated circuit package including a plurality of semiconductor chips, wherein a second output terminal group for outputting the same signal as the first output terminal group to the outside is provided on the built-in first semiconductor chip. A multi-chip module, comprising: 2. An integrated circuit package containing a plurality of semiconductor chips, comprising: an input terminal group for supplying a test signal to a built-in second semiconductor chip; and switching means for switching between a normal mode and a test mode. Multi-chip module characterized by doing. 3. An integrated circuit package containing a plurality of semiconductor chips, comprising: an input terminal group for supplying a test signal to a built-in first semiconductor chip; and switching means for switching between a normal mode and a test mode; A multi-chip module comprising a built-in second semiconductor chip and an output terminal group for outputting an input signal to the outside. 4. An integrated circuit package containing a plurality of semiconductor chips, wherein a second output terminal group that outputs the same signal as the first output terminal group to the outside is provided on the built-in first semiconductor chip. , An input terminal group for supplying a test signal,
A switching unit for switching between a normal mode and a test mode, and an output terminal group for outputting the same signal as the first input terminal group to the second semiconductor chip; an input terminal group for supplying a test signal; And a switching means for switching between a test mode and a test mode.