JPH09213874A - Multi-chip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make sure that each chip out of a multi-chip module is normal after the multi-chip module is formed. SOLUTION: Switches 4 to 8 are provided between the I/O terminals 1a to 1c, 2a, and 3a to 3c of chips 1 to 3 and between the I/O terminals 1a to 1c, 2a, 2b, 3a to 3c of the chips 1 to 3 and outer I/O terminals 9a and 9b. The outer I/O terminals 9a and 9b and the I/O terminals, the I/O terminals 1a to 1c, 2a, 2b, and 3a to 3c of chips 1 to 3 are connected together through a required path by a combination of the switches 4 to 8 which are selectively turned on or off, and the I/O terminals 1a to 1c, 2a, 2b, 3a to 3c of the chips 1 to 3 are connected together also through a required path taking advantage of the above combination of the switches 4 to 8, whereby each chip of the semiconductor chips 1 to 3 can be connected to the outer I/O terminals 9a and 9b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module in which two or more chips are packaged in one package.

[0002]

2. Description of the Related Art Multi-chip modules (hereinafter referred to as MCM)
(Referred to as) is formed by casing two or more chips in one package, and the chips are connected in the package or the external I / O and the chips are connected to each other.

[0003]

However, in the above-mentioned conventional MCM, the chips are connected in the package or the external I / O and the chips are connected. There is a problem that the normality in the can not be confirmed.

[0004]

In order to solve the above-mentioned problems, the present invention is a multi-chip module in which two or more chips are packaged in one package, and between each chip and between each chip and an external terminal. It is characterized in that a switch is provided in between and each chip is connected between each chip and each chip and an external terminal by a combination of turning on and off the switch group.

[0005]

1 is a block diagram showing a first embodiment of a multi-chip module of the present invention. In the figure, 1 to 3 are chips, and three chips are casing in a package.

1a, 1b, 1c are I / Os of the chip 1, 2
Reference numerals a and 2b are I / Os of the chip 2, and reference numerals 3a, 3b and 3c are I / Os of the chip 3. Reference numerals 4 to 8 denote switches, which are a combination of ON and OFF of these switch groups and are connected to an external I / O.
The O9a and 9b and the I / Os of the chips and the I / Os of the chips can be connected to each other through a desired path.

The external I / O 9a is connected to the switch 4. The I / O 1a of the chip 1 is also connected to the switch 4. I / O 1b of chip 1 is connected to switch 5,
The I / O 1c of the chip 1 is connected to the switch 6. The I / O 2a of the chip 2 is connected to the switch 5, and the I / O 2b of the chip 2 is connected to the switch 7.

The I / O 3a of the chip 3 is connected to the switch 6, the I / O 3b of the chip 3 is connected to the switch 7,
The I / O 3c of the chip 3 is connected to the switch 8. The external I / O 9b is connected to the switch 8. Further, the switch 4 and the switch 5, the switch 5, the switch 6 and the switch 7, and the switch 7 and the switch 8 are connected.

Next, the operation of the MCM described with reference to FIG. 1 will be described. FIG. 2 is a block diagram showing an example of the connection between chips of the MCM. In order to realize this connection with the MCM described in FIG. 1, the switch 4 connects the external I / O 9a and the chip 1 to each other.
I / O 1a of the chip 1 is connected and the switch 5 switches the I / O of the chip 1
1b and the I / O 2a of the chip 2 are connected, and the switch 6 connects the I / O 1c of the chip 1 and the I / O 3a of the chip 3,
I / O 2b on chip 2 and I / O on chip 3 with switch 7
3b is connected, and the switch 8 connects the I / O 3c of the chip 3 and the external I / O 9b.

As a result, the MCM described with reference to FIG. 1 can have the function of the MCM shown in FIG. next,
The connection for confirming the normality at the chip level will be described. For example, when confirming the normality of the chip 2, the switch 4 connects the external I / O 9a and the switch 5, and the switch 5 connects the I / O of the switch 4 and the chip 2.
2a is connected. Further, the switch 8 connects the external I / O 9b and the switch 7, and the switch 7 connects the switch 8 and the I / O 2b of the chip 2. This allows the external I
/ O9a is connected to the I / O2a of the chip 2, and the external I / O9b is connected to the I / O2b of the chip 2, so that the chip 2 can be directly accessed from the external I / O to You can check the normality of.

I / O1a and I / O1b in chip 1
When confirming the normality between the external I / O
9a and the I / O 1a of the chip 1 are connected, the switch 5 connects the I / O 1b of the chip 1 and the switch 7, and the switch 7
Switch 5 and switch 8 are connected, and switch 8 connects external I / O 9b and switch 7. As a result, the external I / O 9a and the I / O 1a of the chip 1 are connected, and the external I / O 9b and the I / O 1b of the chip 1 are connected, and the I / O 1a and I / O 1b of the chip 1 are connected to each other. On the other hand, the normality of the chip 1 can be confirmed by directly accessing from the external I / O.

I / O1b and I / O1c in chip 1
When confirming the normality between the external I / O
9a and the switch 5 are connected, and the switch 5 connects the switch 4 and the I / O 1b of the chip 1. The switch 6 connects the I / O 1c of the chip 1 to the switch 7, the switch 7 connects the switch 6 to the switch 8, and the switch 8 connects the external I / O 9b to the switch 7. As a result, the external I / O 9a and the I / O 1b of the chip 1 are connected, and the external I / O 9b and the I / O 1c of the chip 1 are connected, and the I / O 1b and I / O 1c of the chip 1 are connected. On the other hand, the normality of the chip 1 can be confirmed by directly accessing from the external I / O.

I / O1a and I / O1c in chip 1
When confirming the normality between the external I / O
9a and the I / O 1a of the chip 1 are connected. The switch 6 connects the I / O 1c of the chip 1 to the switch 7, the switch 7 connects the switch 6 to the switch 8, and the switch 8 connects the external I / O 9b to the switch 7. As a result, the external I / O 9a and the I / O 1a of the chip 1 are connected, and the external I / O 9b and the I / O 1c of the chip 1 are connected, and the I / O 1a and the I / O of the chip 1 are connected.
The normality of the chip 1 can be confirmed by directly accessing 1c from an external I / O.

I / O 3a and I / O 3b in chip 3
When confirming the normality between the external I / O
9a and the switch 5 are connected, the switch 5 connects the switch 4 and the switch 6, and the switch 6 connects the switch 5 and the I / O 3a of the chip 3. The switch 7 connects the I / O 3b of the chip 3 to the switch 8, and the switch 8 connects the external I / O 9b to the switch 7. As a result, the external I / O 9a and the I / O 3a of the chip 3 are connected, and the external I / O 9b and the I / O 3b of the chip 3 are connected, so that the I / O 3a and I / O 3b of the chip 3 are connected. On the other hand, the normality of the chip 3 can be confirmed by directly accessing from the external I / O.

I / O 3b and I / O 3c in chip 3
When confirming the normality between the external I / O
9a and the switch 5 are connected, the switch 5 connects the switch 4 and the switch 7, and the switch 7 connects the switch 5 and the I / O 3b of the chip 3. In addition, switch 8
/ O9b and the I / O3c of the chip 3 are connected. As a result, the external I / O 9a and the I / O 3b of the chip 3 are connected, and the external I / O 9b and the I / O 3c of the chip 3 are connected, and the I / O 3b and I / O of the chip 3 are connected.
The normality of the chip 3 can be confirmed by directly accessing 3c from an external I / O.

I / O 3a and I / O 3c in chip 3
When confirming the normality between the external I / O
9a and the switch 5 are connected, the switch 5 connects the switch 4 and the switch 6, and the switch 6 connects the switch 5 and the I / O 3a of the chip 3. In addition, switch 8
/ O9b and the I / O3c of the chip 3 are connected. As a result, the external I / O 9a and the I / O 3a of the chip 3 are connected, and the external I / O 9b and the I / O 3c of the chip 3 are connected, and the I / O 3a and the I / O of the chip 3 are connected.
The normality of the chip 3 can be confirmed by directly accessing 3c from an external I / O.

As described above, in the first embodiment of the present invention, the switches are provided between the chips and between the chips and the external I / O, and the connection is changed by the switches. Each chip can be connected to an external I / O by itself, and each chip can be directly accessed from the external I / O.
As a result, normality can be confirmed at the chip level.

From this, as a test with the MCM, after performing a test with each chip alone, a plurality of chips are mounted and bonded to create an MCM, and the process of conducting a comprehensive test as the MCM is performed. By mounting and bonding a plurality of chips to create an MCM, performing a comprehensive test as an MCM, and performing an individual chip test as described above on the MCM only when an abnormality occurs,
It is possible to reduce equipment by reducing the number of steps and eliminating the need for a socket for testing individual chips.

Here, as described with reference to FIG. 1, by providing switches between the chips and between the chips and the external I / O, after the MCM is created, the inter-chip connection and external input / output are performed. Can be changed. This allows
Since a plurality of functions can be realized by one type of MCM, the number of types of MCM to be created can be reduced and the cost can be suppressed.

FIG. 3 is a block diagram showing a second embodiment of the multichip module of the present invention. In the figure, 1 to 3 are chips, and three chips are casing in a package 4. 1a, 1b and 1c are I of the chip 1
/ O, 2a, 2b, 2c are I / Os of the chip 2, 3a, 3
b is an I / O of the chip 3.

9a _{0 to} a ₉ and 9b _{0 to} b ₉ are external I / Os.
It is. 10 is a switch element, and this switch element 10
I / O of each chip, I / O of each chip and external I / O are connected in a one-to-one relationship. By the operation of the switch element 10, the external I / O and the I / Os of the chips and the I / Os of the chips can be connected through a desired path.

Here, an example of the connection path is the same as that described with reference to FIG. 1, and therefore its description is omitted here. As described above, in the second embodiment of the present invention, the switch elements are provided between the chips and between the chips and the external I / O, and the connection is changed by the operation of the switch elements. The chip itself can be connected to an external I / O, and inter-chip connection and external input / output can be changed.

At this time, by using the switch element,
It is possible to deal with a large number of I / Os. Although the switch element is used in the embodiment of FIG. 3, a programmable gate array can be used instead of the switch element.

[0024]

As described above, according to the present invention, in a multi-chip module having a plurality of chips mounted therein, switches are provided between each chip and between each chip and an external terminal to turn on and off the switch group. It is designed to connect between chips and between each chip and external terminals in the off combination.By changing the connection by a switch, each chip can be connected to an external terminal. It has the effect of confirming normality.

Further, since the connection between chips and the input / output to the outside can be changed after the multichip module is produced, there is an effect that one type of multichip module can have a plurality of functions.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a multi-chip module of the present invention.

FIG. 2 is a block diagram showing an example of connection between chips.

FIG. 3 is a block diagram showing a second embodiment of a multi-chip module of the present invention.

[Explanation of symbols]

 1-3 chips 1a-1c I / O 2a, 2b I / O 3a-3c I / O 4-8 switch 9a, 9b external I / O

Claims (2)

[Claims] 1. A multi-chip module in which two or more chips are casing in one package, switches are provided between the chips and between each chip and an external terminal, and a combination of ON and OFF of the switch group is provided. A multi-chip module characterized by connecting between each chip and between each chip and an external terminal. 2. The multi-chip module according to claim 1, wherein an on / off state of the switch group is combined to form an electrical path connecting one of the plurality of chips and an external terminal, A multi-chip module characterized in that each chip can be driven.