JPS5922335A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5922335A
JPS5922335A JP13242582A JP13242582A JPS5922335A JP S5922335 A JPS5922335 A JP S5922335A JP 13242582 A JP13242582 A JP 13242582A JP 13242582 A JP13242582 A JP 13242582A JP S5922335 A JPS5922335 A JP S5922335A
Authority
JP
Japan
Prior art keywords
integrated circuits
group
pads
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13242582A
Other languages
Japanese (ja)
Inventor
Yasushi Sakui
康司 作井
Fumio Horiguchi
文男 堀口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13242582A priority Critical patent/JPS5922335A/en
Publication of JPS5922335A publication Critical patent/JPS5922335A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PURPOSE:To enable to obtain systems having different functions by a method wherein bonding pads connected to integrated circuits are arranged as to surround the integrated circuits of the plural number, and the bonding pads thereof are selected. CONSTITUTION:The group of the integrated circuits 2 consisting of the integrated circuits I -VI is provided at the central part of a semiconductor chip 1, and moreover the bonding pads 3 of the plural number are arranged as to surround the group of the integrated circuits 2 at the circumferential part of the chip 1. The group of the pads I -VI is connected to the integrated circuits I -VI corresponding respectively. The system A can be constructed by selecting the group of the pads (provided that the group of the pads IV is excluded) surrounded by the alternate long and short dash line 4, and the system B can be constructed by selecting the group of the pads (provided that the group of the III is excluded) surrounded by the altenate long and two short dashes line 5. The systems A, B are constructed of the integrated circuits shown on the right sides of the following formulas. System A= I +III+IV+V. System B=II+IV+V+VI.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に係わシ、特に同一チップ上に複
数の集積回路を形成した半導体装置のポンディングパッ
ド配置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor devices, and particularly to improvements in the arrangement of bonding pads in semiconductor devices in which a plurality of integrated circuits are formed on the same chip.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

近年、半導体素子の微細化に伴い、そのチップ面積は急
激に縮小化している。しかしながら、デンディングに際
しては、リード線となる金線の太さに限界があシ、現在
の直径40〔μm〕程度の金線をデンディングするため
には、ポンディングパッドを最低でも100〔μnt 
:] X 100〔μm〕の大きさ確保しなければなら
ない。しだがって、1つのチップにおいては、集積回路
の占める面積は減少し、ポンディングパッドの占める面
積比は増加する傾向にある。
In recent years, with the miniaturization of semiconductor devices, the chip area has been rapidly reduced. However, when bending, there is a limit to the thickness of the gold wire that becomes the lead wire.
:] A size of 100 [μm] must be secured. Therefore, in one chip, the area occupied by the integrated circuit tends to decrease and the area occupied by the bonding pad tends to increase.

また、最近の傾向として同一チップ上に複数の集積回路
を形成し、これらを適当に選択して異なるシステムを実
現する技術が用いられている。しかしたから、この場合
複数の集積回路から必要なものを選択するために、配線
用のマスクツ4ターンを変える必要があシ、これがため
に製造コストの増大化及び工程の煩雑化を招いている。
Furthermore, as a recent trend, a technique is being used in which a plurality of integrated circuits are formed on the same chip, and these are appropriately selected to realize different systems. However, in this case, in order to select the required one from a plurality of integrated circuits, it is necessary to change the four turns of the wiring mask, which increases manufacturing costs and complicates the process.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、マスクパターンを変えることなく同一
チップ上の複数の集積回路を選択することができ、異な
るシステムを容易、かつ廉価に実現し得る半導体装置を
提供することにある。
An object of the present invention is to provide a semiconductor device that allows a plurality of integrated circuits to be selected on the same chip without changing the mask pattern, and that allows different systems to be realized easily and at low cost.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、デンディングパッドの選択によシ複数
の集積回路から所望のものを選択することにある。
The gist of the present invention is to select a desired one from a plurality of integrated circuits by selecting a denting pad.

すなわち本発明は、1つのチップ上に複数の集積回路を
形成してなる半導体装置において、上記各集積回路を囲
むよう該集積回路に接続されたポンディングパッドを配
置し、これらのビンディングパッドの選択によシ異なる
機能のシステムを実現するようにしたものである。
That is, the present invention provides a semiconductor device in which a plurality of integrated circuits are formed on one chip, in which bonding pads connected to the integrated circuits are arranged so as to surround each of the integrated circuits, and the selection of these binding pads is performed. This system is designed to realize systems with different functions.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ぎンディングパッドの選択によシ同一
工程で機能の異なる各種のシステムを実現することがで
きる。このため半導体技術分野における有用性は極めて
大きい。また、配線用マスクパターンを変える必要がな
いので、コスト高を招くこともなく容易に実現すること
が可能である。
According to the present invention, various systems with different functions can be realized in the same process by selecting binding pads. Therefore, it is extremely useful in the field of semiconductor technology. Furthermore, since there is no need to change the wiring mask pattern, it can be easily realized without increasing costs.

〔発明の実施例〕[Embodiments of the invention]

第1図は本発明の一実施例を模式的に示す概略構成図で
ある。半導体チップ1の中央部には複数の集積回路1.
n、III、IV、V、Mからなる集積回路群2が形成
されている。また、チップ1の周辺部には上記集積回路
群2を囲むように複数のデンディングパッド3が配置さ
れている。これらのデンディングパッド3は、その1辺
のパッド群r、n、m、y、v、wは前記集積回路I、
〜、■にそれぞれ接続されている。
FIG. 1 is a schematic configuration diagram schematically showing an embodiment of the present invention. A plurality of integrated circuits 1.
An integrated circuit group 2 consisting of n, III, IV, V, and M is formed. Furthermore, a plurality of denting pads 3 are arranged at the periphery of the chip 1 so as to surround the integrated circuit group 2 . These dending pads 3 have pad groups r, n, m, y, v, and w on one side of the integrated circuit I,
~, ■ are connected respectively.

そして、ノぐラド群■、〜、■から第1のノぐラド群が
構成され、第1のパッド群の外側に配置されたノ9ツド
群t、nから第2のパッド群が構成されるものとなって
いる。
The first pad group is composed of the pad groups ■, ~, and ■, and the second pad group is composed of the pad groups t and n arranged outside the first pad group. It has become something that

このような構成であれば、パッド群I、〜。With such a configuration, pad groups I, -.

■を適当に選択することによって、集積回路I。(2) By appropriately selecting the integrated circuit I.

〜、■のうち必要なものからなる異なる機能を有するシ
ステムを得ることができる。つまシ、第1図中1点鎖線
4で囲まれるパッド群(ただしパッド群■を除く)を選
択することによシシステムAを、2点鎖線5で囲まれる
パッド群(ただしノクツド群■を除く)を選択すること
によってシステムBを得るととができる。なお、システ
ムA、Bは次式の集積回路で構成されるものとする。
It is possible to obtain a system having different functions consisting of the necessary ones among . By selecting the pad group surrounded by the one-dot chain line 4 in FIG. ), system B can be obtained. It is assumed that systems A and B are composed of integrated circuits of the following formula.

ここで、集積回路V、VlはシステムAtBK共通して
使われる回路であるから、そのノ9ツド群v、■を前記
第1図に示す如く配置し、デンディングの際にシステム
A、Hのいずれを選んでも含まれるように配置しておく
、 かくして本実施例によれば、ゾンデイングツ々ッド3の
選択によって、その機能の異なる2種のシステムA、B
を実現することができる。また、デンディングの際に金
線等が重なることを防止でき、確実なゼンデイングを行
うことカニできる。
Here, since the integrated circuits V and Vl are circuits that are commonly used in the systems AtBK, their node groups v and 2 are arranged as shown in FIG. Thus, according to this embodiment, depending on the selection of the zoning module 3, two types of systems A and B with different functions are arranged.
can be realized. In addition, it is possible to prevent gold wires etc. from overlapping during bending, and it is possible to perform reliable bending.

第2図は他の実施例を模式的に示す概略構成図である。FIG. 2 is a schematic configuration diagram schematically showing another embodiment.

なお、第1図と同一部分には同一符号を付して、その詳
しい説明は省略する。この実施例は集積回路群2を増加
し、その/4’ツド3を2重に配置するようにしたもの
である。すなわち、集積回路群2は複数の集積回路1.
II。
Note that the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. In this embodiment, the number of integrated circuit groups 2 is increased, and the /4' nodes 3 are arranged in duplicate. That is, the integrated circuit group 2 includes a plurality of integrated circuits 1.
II.

111、IV、V、Vl、■、■から形成され、これら
の周囲にパッド群V、〜、■からなる第1ノやラド群が
配置され、第1パッド群を囲んでノ4ツド群!、〜、■
からなる第2パッド群が配置されている。
111, IV, V, Vl, ■, ■, and around these pad groups V, ~, ■, the first No. and Rad groups are arranged, and surrounding the first pad group No. 4 Tsudo groups! ,~,■
A second pad group consisting of the following is arranged.

このような構成であれば、図中実線6、破線7.1点鎖
線8或いは2点鎖線9で囲まれるノ4ッド群を選択する
ことによって、次式で示されるシステムA t B #
 Ct Dを実現することができる。
With such a configuration, by selecting the node group surrounded by the solid line 6, the broken line 7, the one-dot chain line 8, or the two-dot chain line 9 in the figure, the system A t B # shown by the following formula can be created.
CtD can be realized.

したがって、先の実施例と同様な効果を奏するのは勿論
のことである。
Therefore, it goes without saying that the same effects as in the previous embodiment can be achieved.

なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記集積回路の個数やパッド群の個数等
は、仕様に応じて適宜定めればよい。また、1つのチッ
プ上の集積回路とゾンデイングツ4ツドについてだけで
なく、1つのチップの外に印刷技術を用いてリード線を
引@出L、yj?ンディングノぐラドをチップ外に設け
る半導体装置に適用することも可能であ克。その他、本
発明の要旨を逸脱しない範囲で、種々変形して実施する
ととができる。
Note that the present invention is not limited to the embodiments described above. For example, the number of integrated circuits, the number of pad groups, etc. may be determined as appropriate according to specifications. In addition to the integrated circuit and sensor components on one chip, we also use printing technology to draw out lead wires outside of one chip. It is also possible to apply this method to semiconductor devices in which the bonding layer is provided outside the chip. In addition, various modifications can be made without departing from the spirit of the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係わる半導体装置を模式的
に示す概略構成図、第2図は他の実施例を模式的に示す
概略構成図である。 1・・・半導体チップ、2・・・集積回路群、3・・・
ポンディングパッド。 出願人代理人  弁理士 鈴 江 武 彦第1図 !。 第2図 13
FIG. 1 is a schematic structural diagram schematically showing a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a schematic structural diagram schematically showing another embodiment. 1... Semiconductor chip, 2... Integrated circuit group, 3...
Ponding pad. Applicant's representative Patent attorney Takehiko Suzue Figure 1! . Figure 2 13

Claims (2)

【特許請求の範囲】[Claims] (1)1つのチップ上に複数の集積回路を形成してなる
半導体装置において、上記各集積回路を囲むよう該集積
回路に接続されたがンディングパッドを配置し、これら
の?ンディングノfツドの選択によシ異なる機能のシス
テムを実現することを特徴とする半導体装置。
(1) In a semiconductor device in which a plurality of integrated circuits are formed on one chip, landing pads connected to the integrated circuits are arranged so as to surround each of the integrated circuits, and these ? A semiconductor device characterized in that it realizes a system with different functions depending on the selection of a terminal node.
(2)  前記デンディングi4ツドは、前記複数の集
積回路の一部に接続された第1 zfクツ群と、残シの
集積回路に接続され上記第1のパッド群の外側に配置さ
れた第2ノ臂ツド群とからなるものであることを特徴と
する特許請求の範囲第1項記載の半導体装置。
(2) The Dending I4 pad includes a first pad group connected to a part of the plurality of integrated circuits, and a second pad group connected to the remaining integrated circuits and arranged outside the first pad group. 2. The semiconductor device according to claim 1, wherein the semiconductor device is comprised of two arm groups.
JP13242582A 1982-07-29 1982-07-29 Semiconductor device Pending JPS5922335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13242582A JPS5922335A (en) 1982-07-29 1982-07-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13242582A JPS5922335A (en) 1982-07-29 1982-07-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5922335A true JPS5922335A (en) 1984-02-04

Family

ID=15081071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13242582A Pending JPS5922335A (en) 1982-07-29 1982-07-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5922335A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4826472A (en) * 1986-06-19 1989-05-02 Ashimori Kogyo Kabushiki Kaisha Toothed belt
JPH0582605A (en) * 1991-09-24 1993-04-02 Mitsubishi Electric Corp Semiconductor integrated circuit element and wafer test inspection
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4826472A (en) * 1986-06-19 1989-05-02 Ashimori Kogyo Kabushiki Kaisha Toothed belt
JPH0582605A (en) * 1991-09-24 1993-04-02 Mitsubishi Electric Corp Semiconductor integrated circuit element and wafer test inspection
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads

Similar Documents

Publication Publication Date Title
US6714431B2 (en) Semiconductor package with a controlled impedance bus and method of forming same
JPS6344734A (en) Semiconductor device
JP2001351983A (en) Semiconductor device and its manufacturing method
JPS61117858A (en) Semiconductor device
JP2748319B2 (en) Multi-chip module design method and module designed thereby
JPS5922335A (en) Semiconductor device
JPS5915183B2 (en) matrix wiring board
JPH04266056A (en) Molded case integrated circuit provided with element for dynamic impedance reduction use
JP2674553B2 (en) Semiconductor device
JP2681427B2 (en) Semiconductor device
JP2002026130A (en) Semiconductor ic circuit and method of placing i/o block
JPS62216240A (en) Package for integrated circuit
US20040245618A1 (en) Integrated circuit and method for fabricating an integrated circuit
JPH05226406A (en) Semiconductor device
JPH01179424A (en) Semiconductor device
JPS62279656A (en) Master slice integrated circuit device
JPH023259A (en) Manufacture of master slice type semiconductor device
US20020030979A1 (en) Circuit board system for optiming contact pin layout in an integrated circuit
JPH02102568A (en) Semiconductor integrated circuit device
JPH0521708A (en) Semiconductor device
JPH0273662A (en) Semiconductor device
JPH06120346A (en) Method for automatically designing semiconductor integrated circuit chip
JPS6081852A (en) Semiconductor device
JPS6136947A (en) Semiconductor device
JPS63296289A (en) Hybrid integrated circuit device