JPH023259A - Manufacture of master slice type semiconductor device - Google Patents

Abstract

PURPOSE:To elevate economical profit by using the TAB method in case that it is mounted to the package having many pins, and using the wire bonding method in case that it is mounted to the package having small pins. CONSTITUTION:In case that it is mounted to the package having many pins, small bonding pads 31 are formed with narrow space in accordance with each of input/output circuits 21 and are connected to pins using the TAB method. In case that it is mounted to the package having small pins, one bonding pad 32 is formed to a plurality of input/output circuits 21 adjoining each other, and this bonding pad is connected to only one among input/output circuits 21 adjoining each other, and the other input/output circuits 21 are left unused. Since the space between the bonding pads are made wide and also the bonding pads are made large, it can be connected to the pin using the wire bonding method. If the input/output circuits 21 left unused are connected in parallel, the driving capacity of the input/output circuits can be elevated.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the manufacturing method of semiconductor devices, the TAB method is used when a mask slice type semiconductor chip is mounted in a package with a large number of pins, and the chip is mounted in a package with a small number of pins. An object of the present invention is to provide a method for manufacturing a mask-sliced semiconductor device that can increase economic benefits by making it possible to connect pins using a wire bonding method in some cases, and in which at least a portion of the wiring is formed. For a master chip in which an unformed main body region and a plurality of input/output circuits are formed, formation of the wiring of the unformed main body region and the formation of the wiring of the unformed main body region and the input/output circuits are performed. an assembly step of forming wiring for connecting the respective connected input/output circuits, forming a TAB pad to be connected to each of the connected input/output circuits, forming wiring for the main body region, and forming a wiring for the main body region; Formation of wiring connecting the region and each of the plurality of mutually adjacent input/output circuits, and formation of wire bonding pads to be connected to each of the plurality of connected sets of the input/output circuits. The forming process and the assembling process are configured to be performed alternatively.

(Industrial Application Field) The present invention relates to an improvement in a method for manufacturing a semiconductor device.In particular, the present invention relates to an improvement in a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a mask slice type semiconductor device that is improved so that it can be formed for both (tape automated bonding) and wire bonding.

[Conventional technology]

A mask slice IC such as a gate array shown in FIG. 2 has a main body SN region 1 in which a large number of basic cells 11 on which at least some wiring is not formed are formed in an array, and a plurality of input/output circuits (I10 cells). ) 21 is formed, and an output pad formation region 3 in which a plurality of output pads will be formed in the future. According to the main body area 1
The wiring for connecting the main body area 1 and the input/output circuit (I10 cell) 21 is completed, and at the same time, the TAB output pad 31 connected to the input/output circuit (I10 cell) 21 is A bonding pad 32 for bonding is formed in the output pad formation region 3.

In recent years, semiconductor devices have become highly integrated and customized, and mask slice type semiconductor devices are now required to have a multi-pin structure of about 80 to 120 pins. For this reason, it has become necessary to form a large number of output bands of semiconductor chips with narrow gaps. It is no longer possible to connect a semiconductor chip with a large number of small output nodes arranged at small intervals to pins using bonding wires, and it is no longer possible to connect the semiconductor chip to a pin using a bonding wire. A TAB (tape automated bonding) method must be used in which a chip is mounted and the output pads of the semiconductor chip are bonded to wiring formed on the tape.

[Problem to be solved by the invention]

By the way, the TAB method is not only disadvantageous in terms of cost compared to the wire bonding method, but also has the disadvantage that it is necessary to prepare a different TAB tape for each type of semiconductor chip, which increases the number of types of TAB tapes. Depending on the final specifications, if a mask slice type semiconductor chip is to be mounted in a package with a large number of pins, the TAB method must be used for the reasons mentioned above, but it is also possible to mount it in a package with a small number of pins. Even in cases where the wire bonding method cannot be used at present, the TAB method must be used even though it is not necessarily necessary. Since an output pad is provided corresponding to each output circuit (I10 cell) 21, the interval between the output bands is narrow regardless of the number of pins of the mounted pancage, and the size of the output pad is also formed small. be. As a result, in mask slice type semiconductor devices,
Even if this is not necessary, there is a drawback in that the TAB method, which is disadvantageous in terms of cost, has to be adopted.

The purpose of the present invention is to eliminate this drawback, and use the TAB method when mounting a mask-sliced semiconductor chip on a package with a large number of pins, and use the TAB method when mounting a mask-sliced semiconductor chip on a package with a small number of pins. It is an object of the present invention to provide a method for manufacturing a mask slice type semiconductor device that enables the use of a bonding method and increases economic benefits.

[! Means for Solving Problem I] The above object is to provide a master chip in which a main body region (1) in which at least a portion of wiring is not formed and a plurality of input/output circuits (21) are formed. The body area (
1) formation of wiring, formation of wiring connecting the main body region (1) and each of the input/output circuits (21), and formation of wiring for connecting the connected input/output circuits (21). An assembly process including the formation of a TAB band (31) to be connected to each, formation of wiring for the main body region (1), and a step of forming a wiring for the main body region (1) and the input/output circuit (21). Forming wiring that connects each of the plurality of mutually adjacent ones;
Wire bonding bands (
This is achieved by performing the formation of step 32) and the assembling step alternatively.

[Effect]

When mounting on a package with a large number of pins (see FIG. 1a), small bonding pads 31 are formed at narrow intervals corresponding to each input/output circuit (I10 cell) 21, and the TA
Connect to the pin using method B.

When mounting on a package with a small number of pins (see Figure 1b), one bonding is required for multiple (the figure shows the case of two) mutually adjacent input/output circuits (I10 cells) 21. A pad 32 is formed, and this bonding pad is connected to only one of the plurality of adjacent input/output circuits (I10 cells) 21, and the remaining input/output circuits (I10 cells) 21 are connected to each other. The intervals between the bonding pads left unused are wide, and the bonding pads are also formed large, so that they can be connected to pins using a wire bonding method.

If the input/output circuit (I10 cell) 21 left unused in FIG. 1b (see FIG. 1c) is connected in parallel, the driving capability of the input/output circuit can be increased.

[Embodiment] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

Referring again to FIG. 2, this is a diagram showing the configuration of a mask slice type semiconductor chip. ■
2 is a main body area in which a large number of basic cells 11 in which at least part of wiring is not formed is formed in an array, 2 is an area in which an input/output circuit (I10 cell) 21 is formed, and 3 is an area in which an input/output circuit (I10 cell) 21 is formed. This is a region where a TAB bonding pad 31 or a wire bonding bonding pad 32 is formed. According to the final specifications, complete the wiring of the main body area 1, form the wiring that connects the main body area 1 and the input/output circuit (■10 cell) 21, and
The TAB output pad 31 connected to the wire bonding output pad 32 is formed in the following manner.

Refer to Figure 1a. When mounting a mask slice type semiconductor chip in a pan cage with a large number of pins, input/output circuit (1/○ cell) 2
Narrow width TAB output pan 3 corresponding to each of 1
1 and connect it to the pin using the TAB method.

Refer to Figure 1b When mounting a mask slice type semiconductor chip in a package with a small number of pins, the input/output circuit (I10 cell)
21 adjacent. A wide bonding pad 32 corresponding to a plurality of wire bonding pads (the figure shows the case of two) is formed, and this bonding pad 32 is connected to the plurality of adjacent input/output circuits (I10 cells) 21. The remaining input/output circuit (I10 cell) 21 is left unused. Since the bonding pads are spaced widely and the bonding pad itself is also large, the wire Can be connected to pins using bonding method.

See Figure 1c If necessary, connect the input/output circuit (I10 cell) 21, which was left unused in Figure 1b, in parallel.
The driving ability of input/output circuits can be improved.

(Effects of the Invention) As explained above, in the method for manufacturing a semiconductor device according to the present invention, a main body region in which at least a portion of wiring is not formed and a plurality of input/output circuits (I10 cells) are formed. For the master chip that is in
forming TAB pads to be connected to each of the cells), forming wiring in the main body region, and connecting the main body region to each of a plurality of mutually adjacent input/output circuits (I10 cells). Wiring formation and input/output circuit (110
The assembly process of forming wire bonding pads to be connected to each of multiple sets of cells (cells) can be selected according to needs, so when mounting on a package with a large number of pins, the TAB method can be used. Even if it is connected, if it is mounted in a package with a small number of pins, it becomes possible to connect to the bin using a wire bonding method, which can increase economic benefits.

[Brief explanation of the drawing]

Figures 1a-lc are diagrams of the formation of a bonding pad. FIG. 2 is a configuration diagram of a mask slice type semiconductor chip. Main body area, basic cell, input/output circuit formation area, input/output circuit (1/○ cell), bonding pad formation area, bonding pad (for TAB), bonding pad (for wire bonding).

Claims (1)

[Claims] A main body region (1
) and a plurality of input/output circuits (21) are formed on the master chip.
) and each of the input/output circuits (21), and formation of wiring connecting the connected input/output circuits (21).
), forming a TAB pad (31) to be connected to each of the main body region (1), and forming a wiring for the main body region (1).
) and each of the plurality of mutually adjacent input/output circuits (21), and a wire connected to each of the plurality of connected sets of the input/output circuits (21). A method of manufacturing a semiconductor device, characterized in that forming a bonding pad (32) and assembling step are performed alternatively.