JPS59105349A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS59105349A
JPS59105349A JP21391182A JP21391182A JPS59105349A JP S59105349 A JPS59105349 A JP S59105349A JP 21391182 A JP21391182 A JP 21391182A JP 21391182 A JP21391182 A JP 21391182A JP S59105349 A JPS59105349 A JP S59105349A
Authority
JP
Japan
Prior art keywords
integrated circuit
wire
pads
value
interval
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21391182A
Other languages
Japanese (ja)
Inventor
Kazutaka Mori
和孝 森
Tamotsu Usami
保 宇佐美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21391182A priority Critical patent/JPS59105349A/en
Publication of JPS59105349A publication Critical patent/JPS59105349A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable to manufacture an integrated circuit substrate which has many terminals and complicated functions with a small area and good yield at a low cost by a method wherein electrode terminals on the integrated circuit substrate are so arranged that the interval between connection members becomes almost constant. CONSTITUTION:A pad d7 is set at the center of one side. Next, the value of a wire interval l is set at a value which satisfies the condition of wire bonding, pads d5 and d8 are decided by drawing a triangle whose bottom side is a wire C7 and height is l. Further, pads d5 and d9 are decided by drawing a triangle whose bottom side is wires C6 and C8 and height is l. The pads d1-d13 are arranged in the above-mentioned manner, the value of the interval l is set again by evaluating its result, and the optimum arrangement is made by successive approximation with a computer. For example, the arrangement of 13 bonding pads d1-d13 is made on one side of a chip, and, based on the optimum value, the pad intervals are successively enlarged toward each corner from the center of one side of the chip; thereby enabling the arrangement in such a manner that each wire interval becomes almost constant.

Description

【発明の詳細な説明】 本発明は集積回路装置に関し、特に集積回路基体上に数
多（設けられた電極端子を外部回路と接続するようにな
した集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to an integrated circuit device in which a large number of electrode terminals (provided on an integrated circuit substrate) are connected to an external circuit.

従来の集積回路の電極端子は、これと接続さｎるパッケ
ージや回路基板上の電極端子の配列状況を考えずに配置
していたため、特にワイヤボンデくなるという欠点があ
った。これは基体上の電極端子を等間隔に配置していた
ためである。しかし実際に製造上の制約となるのは端子
間隔ではなく、ワイヤ間の間隔であることが分った。The electrode terminals of conventional integrated circuits have been arranged without considering the arrangement of the electrode terminals on the package or circuit board to which they are connected, and have had the disadvantage of being wire bonded. This is because the electrode terminals on the base were arranged at equal intervals. However, it has been found that the actual manufacturing constraint is not the terminal spacing, but the spacing between the wires.

本発明の目的は、集積回路基体に接続されるワイヤ等の
接続部材の入射角度を考慮し、この接続部材間の間隔が
ｔＤ丁一定となるように集積回路基体上の電極端子を配
置することによシ、小さな面積の基体上に数多くの端子
を配置できる装置を提供することにある。An object of the present invention is to consider the angle of incidence of connection members such as wires connected to the integrated circuit substrate, and to arrange electrode terminals on the integrated circuit substrate so that the distance between the connection members is constant tD. Another object of the present invention is to provide a device that allows a large number of terminals to be arranged on a substrate having a small area.

以下、本発明の一実施例を第１〜第３図により説明する
。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

Ｍ１図は半導体集積回路基体とその周辺を示す。Diagram M1 shows the semiconductor integrated circuit substrate and its surroundings.

図のＣは電極の接続部材の一例としてのボンディングワ
イヤを示す。図に示すようにワイヤＣとベンツ）ａの辺
との角度は、辺の端部にゆくほどよシ鋭角になる。この
ため第２図に示す従来装置の如くに、ポンディングパッ
ドｄ１〜ｄｌｌを等間隔に並べた場合、ワイヤ間隔看、
〜２．は、！、＜−Ｌ　＜ＥＢ　＜４３゜く形、となる
。この場合石、ｚ１、４　ａ　１・となっている。看、
は、ワイヤボンディングの装置設計上の制限から、ある
最低値が定められる。石、がこの条件を満たすためには
、第２図のように、ポンディングパッドは各辺に１１ケ
しか配置することができない。C in the figure shows a bonding wire as an example of an electrode connection member. As shown in the figure, the angle between the wire C and the side of the vent (a) becomes more acute toward the end of the side. Therefore, when the bonding pads d1 to dll are arranged at equal intervals as in the conventional device shown in FIG.
~2. teeth,! , <-L <EB <43° shape. In this case, the stone is z1, 4 a 1. Look,
A certain minimum value is determined due to limitations in wire bonding equipment design. In order for the stone to satisfy this condition, only 11 pounding pads can be placed on each side, as shown in FIG.

一方、本実施例では第３図の如く、まずパッドｄ７を一
辺の中心に設定する。次にワイヤ間隔石の値をワイヤボ
ンディングの条件を満たすある値に設定し、ワイヤＣ７
を底辺とし高さ石の三角形を描いてｄａ　　、ｄｉを決
定する。さらにＣ６，ｃｆｉを底辺とし高さ矛の三角形
を描いてｄｓ　　、ｄ＋＋を決定する。以上のようにし
てｄ１〜ｄｓｓ　ｔで配置し、その結果を評価して再度
！の値を設定し、計算機による遂次近似によυ最適配置
を行なう。この方法により配置したのが第３図である。On the other hand, in this embodiment, as shown in FIG. 3, the pad d7 is first set at the center of one side. Next, set the wire spacing value to a certain value that satisfies the wire bonding conditions, and wire C7
Determine da and di by drawing a triangle with height as the base. Furthermore, ds and d++ are determined by drawing a triangle with C6 and cfi as the base and the height of the triangle. Place d1 to dss t as above, evaluate the result, and try again! The value of υ is set, and the optimal placement of υ is performed by successive approximations using a computer. FIG. 3 shows an arrangement using this method.

第３図では、チップの一辺にｄ１〜ａＵの１３ケのボン
ディングバンドの配置をし、上記最適値に基いて、チッ
プの一辺の中央部から各角部に向かって順次パッド間隔
を広くしてゆき、これによシ各ワイヤ間隔がほぼ一定と
力るように配置することができた。なお第２図の形、と
第３図の影とは等しい値である。In Figure 3, 13 bonding bands from d1 to aU are arranged on one side of the chip, and the pad spacing is gradually increased from the center of one side of the chip toward each corner based on the above optimal value. As a result, I was able to arrange the wires so that the distance between them was almost constant. Note that the shape in FIG. 2 and the shadow in FIG. 3 have the same value.

本実施例によシ、従来では一辺に１１ケしかパッドを配
置できなかったチップに、−辺１３ケのポンディングパ
ッドを配置できたことになる。これを逆に考えると、あ
るビン数のチップを設計する場合、本実施例によれば、
１０〜２０％チップサイズを縮小できるという効果があ
る。According to this embodiment, it is possible to arrange 13 bonding pads on the minus side on a chip where only 11 pads could be arranged on one side in the conventional chip. Considering this in reverse, when designing a chip with a certain number of bins, according to this embodiment,
This has the effect of reducing the chip size by 10 to 20%.

なお、上記パッド間隔は種々変更でき、例えば中央部付
近ではすべてパッド間隔を一定とし、角部付近でのみそ
の間隔を広くしてもよい。Note that the above-mentioned pad spacing can be changed in various ways; for example, the pad spacing may be all constant near the center, and the spacing may be widened only near the corners.

一本発明によれば、電極接続部材の間隔を最適化し、決
められた数の電極端子を小さな面積の集積回路基体に配
置することができるので、端子数が多くて機能が複雑な
集積回路基体を、小さな面積で、歩留りよく安価に製造
することができる。According to the present invention, it is possible to optimize the spacing between electrode connecting members and arrange a predetermined number of electrode terminals on an integrated circuit substrate with a small area. can be manufactured in a small area at a high yield and at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は集積回路基体（半導体チップ）及びその周辺の
平面図、 第２図、第３図は第１図のチップ−辺を拡大した図であ
って、第２図は従来装置による端子の配置を示す平面図
、第３図は、本実施例による装置の第２図と同様の平面
図である。 ａ・・・半導体チップ、ｂ・・・パンケージのリード部
分（外部の電極端子）、Ｃ及びｃ１〜ｃｓｓ・・・ボン
ディングワイヤ、ｄ及びｄ、〜ｄｌ１１・・・ポンディ
ングパッド、看及びＡ、−Ａ、・・・ワイヤの間隔。Fig. 1 is a plan view of the integrated circuit substrate (semiconductor chip) and its surroundings, Figs. 2 and 3 are enlarged views of the sides of the chip in Fig. 1, and Fig. 2 shows the terminals of the conventional device. A plan view showing the arrangement, FIG. 3, is a plan view similar to FIG. 2 of the apparatus according to this embodiment. a... Semiconductor chip, b... Lead part of the pan cage (external electrode terminal), C and c1~css... Bonding wire, d and d, ~dl11... Bonding pad, and A, -A, ... Wire spacing.

Claims (1)

【特許請求の範囲】 １、集積回路基体上に設けらｎた複数の電極取り出し端
子と、これらの端子を前記集積回路基体外の外部装置と
接続するための接続部材とを有する集積回路装置におい
て、前記端子が前記集積回路基体の各辺の中央部より各
角部側の方が広い間隔で配置されていることを特徴とす
る集積回路装置。 ２、上記端子近傍における接続部材間の間隔が互にほぼ
等しいことを特徴とする特許請求の範囲第１項記載の集
積回路装置。[Claims] 1. An integrated circuit device having a plurality of electrode lead-out terminals provided on an integrated circuit substrate and a connecting member for connecting these terminals to an external device outside the integrated circuit substrate. . An integrated circuit device, wherein the terminals are arranged at wider intervals at each corner of each side of the integrated circuit substrate than at the center. 2. The integrated circuit device according to claim 1, wherein the intervals between the connecting members in the vicinity of the terminals are substantially equal to each other.
JP21391182A 1982-12-08 1982-12-08 Integrated circuit device Pending JPS59105349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21391182A JPS59105349A (en) 1982-12-08 1982-12-08 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21391182A JPS59105349A (en) 1982-12-08 1982-12-08 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS59105349A true JPS59105349A (en) 1984-06-18

Family

ID=16647067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21391182A Pending JPS59105349A (en) 1982-12-08 1982-12-08 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59105349A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653266A (en) * 1992-08-03 1994-02-25 Yamaha Corp Semiconductor device
US6909179B2 (en) * 1996-03-18 2005-06-21 Renesas Technology Corp. Lead frame and semiconductor device using the lead frame and method of manufacturing the same
CN100359678C (en) * 1996-03-18 2008-01-02 株式会社日立制作所 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122144A (en) * 1980-02-29 1981-09-25 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122144A (en) * 1980-02-29 1981-09-25 Toshiba Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653266A (en) * 1992-08-03 1994-02-25 Yamaha Corp Semiconductor device
US6909179B2 (en) * 1996-03-18 2005-06-21 Renesas Technology Corp. Lead frame and semiconductor device using the lead frame and method of manufacturing the same
CN100359678C (en) * 1996-03-18 2008-01-02 株式会社日立制作所 Semiconductor device

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