JPH03166755A - Lead frame for semiconductor integrated circuit - Google Patents

Lead frame for semiconductor integrated circuit

Info

Publication number
JPH03166755A
JPH03166755A JP30720389A JP30720389A JPH03166755A JP H03166755 A JPH03166755 A JP H03166755A JP 30720389 A JP30720389 A JP 30720389A JP 30720389 A JP30720389 A JP 30720389A JP H03166755 A JPH03166755 A JP H03166755A
Authority
JP
Japan
Prior art keywords
integrated circuit
land
ground
power source
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30720389A
Other languages
Japanese (ja)
Inventor
Sumio Mizobe
溝部　澄夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP30720389A priority Critical patent/JPH03166755A/en
Publication of JPH03166755A publication Critical patent/JPH03166755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

PURPOSE:To reduce the number of pins used for a power source and a ground and to accommodate them in a package smaller than normal one by providing a bonding region for a potential different from an integrated circuit board potential between a semiconductor integrated circuit and an inner lead pin. CONSTITUTION:A lead frame is separated at its die pad into two regions of a land 6 for a power source and a land 7 for a ground. In a bonding diagram of an integrated circuit 3 when the frame is used, a pad 8 for a power source is bonded to the land 6, and a pad 9 for a ground is bonded to the land 7. Accordingly, even if there are a plurality of pads 10, 11 for a power source and a ground, they can be coped with two inner lead pins 13, 15. Thus, the total number of outer lead pins is reduced than that of the pads for the power source, the ground on the integrated circuit, and accommodated in a package smaller than normal one.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体集積回路を封入するプラスチックパッ
ケージ用リードフレームに係わり、より詳しくはリード
フレームの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a plastic package that encapsulates a semiconductor integrated circuit, and more particularly to the structure of the lead frame.

〔従来の技術］ 集積回路上の全パッドからアウクーリードビンに信号、
及び電源層を出力する場合、アウターリードビンはパッ
ド数と同数、或はそれ以上のビン数が必要であった． 第ｌ図は従来のＱＦＰのリードフレーム図であり、グイ
パッド１は単一電源層になっている．第２図は当該リー
ドフレームを使用した時のボンディング図であり、グイ
パッドｌに集積回路３をグイボンドし、更に集積回路３
の上バッド４からインナーリード２にワイヤーボンディ
ングした様子を示している．以上より明らかで有るが、
従来の方法では、集積回路３上のパッド４とインナーリ
ード２が必ず対になっており、インナーリード２の本数
は集積回路３上のパッド総数と同数、或はそれ以上必要
であった．ＱＦＰを使わざるを得ないという問題点が有
った。本発明は、集積回路の特性を維持しつつ、電源及
び接地用に使用されるビン数を極力減らし一回り小さい
パッケージに収容可能ならしめることを目的としている
．〔発明が解決しようとする課題１ 集積回路が高速化、大規模化されるにつれて、雑音を抑
える為、電源及び接地用ビンの本数が増加させなければ
ならなかった．一般的には、総ビン数のうち２〜３割が
電源及び接地用ビンに割振られている．一方ＪＤＥＣ　
（日本電子機械工業会）規格のＱ　Ｆ　Ｐ　（Ｑｕａｄ
　Ｆｌａｔ　Ｐａｃｋａｇｅ　）の場合ビン数が、８４
，１００、１３２、１６４、１９６ビンになっている為
、８５ビン必要であればｌ００ＱＦＰを、或は１０１ビ
ン必要であればｌ３２ビンＱＦＰを使わざるを得ないと
いう問題点が有った．本発明は、集積回路の特性を維持
しつつ、電源及び接地用に使用されるビン数を極力減ら
し一回り小さいパッケージに収容可能ならしめる事を目
的としている． 〔課題を解決するための手段］ リードフレームのグイパッド部をエッチング技術を用い
て、接地と複数個の電源領域に分離し、集積回路上の複
数個の電源及び接地用パッドをそれぞれ上記分離電源領
域にボンディングし、且つ当該分離領域から少なくとも
一本のインナーリードピンヘボンディングする事で、集
積回路上の電源及び接地用パッド総数よりアウターリー
ドビン総数を減少させる． 〔実　施　例］ 以下図面に従って本発明の実施例を説明する．第３図は
本発明によるリードフレーム図であり、グイパッド部が
電源用ランド６と接地用ランド７の二つの領域に分離さ
れている．第４図は本発明によるリードフレームを使用
した時の集積回路３のボンディング図であり、電源用バ
ツド８は電源用ランド６へ、接地用パツド９は接地用ラ
ンド７ヘボンディングされている．１０は電源用ランド
６から電源用インナーリードピン１１へのボンディング
線、ｌ２は接地用ランド７から接地用インナーリードピ
ンｌ３へのボンデイング線である．当該発明によれば、
電源及び接地用パッドが各々複数個あったとしても、２
本のインナーリードピンで対応可能であり，集積回路上
のパッド総数にしめる電源及び接地用パッド数の比率が
高い程アウターリードビンの減少効果が大きい．［発明
の効果〕 集積回路が高速化、大規模化されるにつれて、雑音を抑
える為、電源及び接地用ビンの本数が増加する．一般的
には、総ビン数のうち２〜３割が電源及び接地用ビンに
割振られている．一方ＪＤＥＣ（日本電子機械工業会）
規格のＱＦＰ（ＱｕａｄＦｌａｔ　Ｐａｃｋａｇｅ　）
の場合ビン数が、８４、１００、１３２、１６４，１９
６ビンになっている為、８５ビン必要であれば１　００
ＱＦＰを、或は１０１ビン必要であれば１３２ビンＱＦ
Ｐを使わざるを得ないという問題点が有ったが、本発明
によれば、集積回路の特性を維持しつつ、電源及び接地
用に使用されるビン数を極力減らし、一回り小さいパッ
ケージに収容でき、電子機器の小型化及びパッドのコス
トダウンに莫大な貢献が出来る。[Prior art] Signals are sent from all pads on the integrated circuit to the Aucoulea bin.
When outputting a power layer and a power layer, the number of outer lead bins was required to be equal to or greater than the number of pads. Figure 1 is a lead frame diagram of a conventional QFP, and the guide pad 1 is a single power supply layer. Figure 2 is a bonding diagram when using the lead frame, in which the integrated circuit 3 is bonded to the guide pad l, and then the integrated circuit 3 is
This shows wire bonding from upper pad 4 to inner lead 2. It is clear from the above,
In the conventional method, the pads 4 on the integrated circuit 3 and the inner leads 2 are always paired, and the number of inner leads 2 needs to be equal to or greater than the total number of pads on the integrated circuit 3. There was a problem that QFP had to be used. The present invention aims to reduce the number of bins used for power supply and grounding as much as possible while maintaining the characteristics of the integrated circuit, so that it can be accommodated in a slightly smaller package. [Problem to be solved by the invention 1] As integrated circuits become faster and larger, the number of power supply and grounding bins has to be increased in order to suppress noise. Generally, 20-30% of the total number of bins is allocated to power supply and grounding bins. On the other hand, JDEC
(Japan Electronics Industry Association) standard QFP (Quad
Flat Package), the number of bins is 84.
, 100, 132, 164, and 196 bins, so there was a problem that if 85 bins were needed, 100 QFP had to be used, or if 101 bins were needed, 132 bin QFP had to be used. The present invention aims to reduce the number of bins used for power supply and grounding as much as possible while maintaining the characteristics of the integrated circuit so that it can be housed in a slightly smaller package. [Means for Solving the Problems] Using etching technology, the lead frame pad portion is separated into a grounding area and a plurality of power supply areas, and each of the plurality of power supply and grounding pads on the integrated circuit is connected to the separated power supply area. By bonding to at least one inner lead pin from the isolation area, the total number of outer lead pins is reduced compared to the total number of power and ground pads on the integrated circuit. [Examples] Examples of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram of a lead frame according to the present invention, in which the lead pad portion is separated into two areas: a power land 6 and a ground land 7. FIG. 4 is a bonding diagram of the integrated circuit 3 when using the lead frame according to the present invention, in which the power pad 8 is bonded to the power land 6, and the grounding pad 9 is bonded to the grounding land 7. 10 is a bonding wire from the power supply land 6 to the power supply inner lead pin 11, and 12 is a bonding wire from the grounding land 7 to the grounding inner lead pin 13. According to the invention,
Even if there are multiple power and ground pads, 2
This can be done with standard inner lead pins, and the higher the ratio of the number of power supply and grounding pads to the total number of pads on the integrated circuit, the greater the effect of reducing outer lead pins. [Effects of the invention] As integrated circuits become faster and larger, the number of power supply and grounding bins increases in order to suppress noise. Generally, 20-30% of the total number of bins is allocated to power supply and grounding bins. On the other hand, JDEC (Japan Electronics Industry Association)
Standard QFP (QuadFlat Package)
If the number of bins is 84, 100, 132, 164, 19
Since there are 6 bins, if you need 85 bins, 100
QFP, or 132 bin QF if 101 bins are required
However, according to the present invention, while maintaining the characteristics of the integrated circuit, the number of bins used for power supply and grounding can be reduced as much as possible, resulting in a smaller package. This can greatly contribute to the miniaturization of electronic equipment and cost reduction of pads.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＱＦＰのリードフレーム図である． 第２図は従来のリードフレームを使用した時のボンディ
ング図である。 第３図は本発明によるリードフレーム図である． 第４図は本発明によるリードフレームを使用したボンデ
ィング図である。 １　３　・ １　４　・ ・グイパッド ・インナーリード ・タブ吊りリード ・集積回路 ・パッド ・ボンディングワイヤー ・電源用ランド ・接地用ランド ・絶縁領域 ・電源用パッド ・接地用パッド ・電源用ランドと電源用インナーリー ドビン間のボンデイング線 ・・電源用インナーリードピン ・・接地用ランドと接地用インナーリードビン間のポン
ディング線 １ ５ ・接地用インナーリードピン 以 上Figure 1 is a diagram of a conventional QFP lead frame. FIG. 2 is a bonding diagram when a conventional lead frame is used. Figure 3 is a diagram of a lead frame according to the present invention. FIG. 4 is a bonding diagram using the lead frame according to the present invention. 1 3 ・ 1 4 ・ ・Gui pad, inner lead, tab suspension lead, integrated circuit, pad, bonding wire, power supply land, grounding land, insulation area, power supply pad, grounding pad, power supply land and power supply inner Bonding wire between lead bins... Inner lead pin for power supply... Bonding wire between grounding land and inner lead bin for grounding 1 5 - Inner lead pin for grounding or more

Claims (1)

【特許請求の範囲】[Claims] 　半導体集積回路とインナーリードピン間に少なくとも
一つ以上、集積回路基板電位と異なる電位用のボンディ
ング領域を有することを特徴とする半導体集積回路用リ
ードフレーム。A lead frame for a semiconductor integrated circuit, comprising at least one bonding region for a potential different from the integrated circuit substrate potential between the semiconductor integrated circuit and the inner lead pin.
JP30720389A 1989-11-27 1989-11-27 Lead frame for semiconductor integrated circuit Pending JPH03166755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30720389A JPH03166755A (en) 1989-11-27 1989-11-27 Lead frame for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30720389A JPH03166755A (en) 1989-11-27 1989-11-27 Lead frame for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH03166755A true JPH03166755A (en) 1991-07-18

Family

ID=17966283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30720389A Pending JPH03166755A (en) 1989-11-27 1989-11-27 Lead frame for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH03166755A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541149U (en) * 1991-10-15 1993-06-01 金星エレクトロン株式会社 Semiconductor package
JPH06151641A (en) * 1992-11-05 1994-05-31 Toshiba Corp Semiconductor device
US5386141A (en) * 1992-03-31 1995-01-31 Vlsi Technology, Inc. Leadframe having one or more power/ground planes without vias
KR100262180B1 (en) * 1996-06-28 2000-07-15 고토 하지메 Resin sealed semiconductor device and method for manufacturing the same
KR100533750B1 (en) * 2000-07-13 2005-12-06 앰코 테크놀로지 코리아 주식회사 Lead Frame Used for the Fabrication of Semiconductor Package and Semiconductor Package Fabricated Using the Same
US7834435B2 (en) 2006-12-27 2010-11-16 Mediatek Inc. Leadframe with extended pad segments between leads and die pad, and leadframe package using the same
US8124461B2 (en) 2006-12-27 2012-02-28 Mediatek Inc. Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
EP1944802B1 (en) * 2006-12-27 2018-02-14 MediaTek Inc. Semiconductor package product

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541149U (en) * 1991-10-15 1993-06-01 金星エレクトロン株式会社 Semiconductor package
US5386141A (en) * 1992-03-31 1995-01-31 Vlsi Technology, Inc. Leadframe having one or more power/ground planes without vias
JPH07505505A (en) * 1992-03-31 1995-06-15 ブイ・エル・エス・アイ・テクノロジー・インコーポレイテッド Leadframe with one or more power/ground planes without vias
JPH06151641A (en) * 1992-11-05 1994-05-31 Toshiba Corp Semiconductor device
KR100262180B1 (en) * 1996-06-28 2000-07-15 고토 하지메 Resin sealed semiconductor device and method for manufacturing the same
KR100533750B1 (en) * 2000-07-13 2005-12-06 앰코 테크놀로지 코리아 주식회사 Lead Frame Used for the Fabrication of Semiconductor Package and Semiconductor Package Fabricated Using the Same
US7834435B2 (en) 2006-12-27 2010-11-16 Mediatek Inc. Leadframe with extended pad segments between leads and die pad, and leadframe package using the same
US8124461B2 (en) 2006-12-27 2012-02-28 Mediatek Inc. Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
US8350380B2 (en) 2006-12-27 2013-01-08 Mediatek Inc. Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
EP1944802B1 (en) * 2006-12-27 2018-02-14 MediaTek Inc. Semiconductor package product

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