JPH07118507B2 - Semiconductor integrated circuit using bump mounting - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit using bump mounting, and more particularly to a method for laying out the bump and outer and inner gate cells on a chip.

[Conventional technology]

In semiconductor integrated circuits, wire bonding is widely used to connect the semiconductor chip to the terminal pins of the package. In this case, a large number of bonding pads are provided around the semiconductor chip, and a large number of bonding pads connected to the terminal pins are also provided on the package substrate.
These pads are connected by wires.
In a gate array LSI, a large number of external gates (I / O
Gate) and internal gate are made, but in the wire bonding type, the internal gate is located at the center of the chip and I / O.
The gate will be made in the annular region between the bond pad and the internal gate.

A bump method is also used to connect the chip and its mounting substrate. This is multiple hemispherical nodules (bumps) on the chip.
, And a plurality of pads are formed on the side of the substrate, and these bumps are connected to the pads (solder bumps are soldered by heating) to connect the chip and the substrate. This bump method is used not only for individual components but also for integrated circuits.

[Problems to be solved by the invention]

By the way, in a gate array LSI, the arrangement of I / O gate cells and internal gate cells greatly affects the chip size and performance of the LSI. In the case of a gate array LSI with bonding pads or bumps around the chip, internal gates in the center of the chip, and I / O gates between them, the wiring length on the chip may become longer, which adversely affects the chip size and / or performance. Exert. The present invention aims to improve this point by changing the layout of the I / O gate and the like.

[Means for solving problems]

A semiconductor integrated circuit using bump mounting of the present invention has a large number of bumps dispersedly arranged on the entire surface of a semiconductor chip, and the I / O gate cells of a gate array are arranged along a line dividing the periphery of the chip and the chip surface into a plurality of parts. And the internal gate cells are arranged inside the divided area.

[Action]

In the present invention, as shown in FIG. 1, the bumps 10 are dispersedly arranged on the entire surface of the chip 12, the I / O gate cells 14 are arranged on a line that divides the periphery of the chip and the inside thereof, and the internal gate cells are I / O.
It is arranged in a region 16 surrounded by the gate cell 14. In this example, the chip 12 is divided into two parts, the I / O gate cell array has an 8-shape, and the internal gate cells are arranged in the two internal regions. Of course, the number of divisions may be four, eight, etc. instead of two.

In this way, even large chips can be divided into two, four
The chip is divided into small chips, and the LSI has 1 / O gates around the small chips and gates inside, and the average wiring length can be reduced. In addition, high integration of the internal gate becomes possible.

Although the I / O gate cell 14 is directly under the bump 10 in FIG. 1, it may be provided between the bumps as shown in FIG. When bumps are provided on the I / O gate as shown in FIG. 1, the region between each I / O gate cell becomes a channel (region where power supply and signal wiring run). In the case of FIG. 2, the channel is directly below the bump. If the channel has a margin, an internal gate may be provided in this portion as well. Power wiring
Potential drop (Vcc side) or potential rise (Vss) due to IR drop
However, as a countermeasure against this, a plurality of package power supply terminal pins may be provided, and thus a plurality of chip power supply bonding pads or bumps may be provided. The shaded bumps in FIGS. 1 and 2 are for power supply, and a plurality of bumps are provided. Since the bump has an allowable current value, it is necessary to make it plural also from this point. The bumps without diagonal lines are for signal output.

〔Example〕

In the gate array LSI, the connection between the I / O buffer and the internal gate is as shown in FIG.
a-internal gate 18-output buffer 14b. EC
In the L gate array, these have the structure shown in FIG. That is, each consists of two transistors, a differential pair in which their emitters are commonly connected to a constant current source transistor, and a pair of output stage transistors whose bases are connected to their load resistors. ₁ is for input, T ₂ is for reference voltage V _BB , and terminals T ₃ , T ₄ are for output.
In the internal gate 18, terminal T ₅ is for input and T ₆ is the reference voltage Vr.
, T ₇ and T ₈ are for output, and in the output buffer 14b, terminal T ₉ is for input, T ₁₀ is for reference voltage Vr, and terminals T ₁₁ and T ₁₂ are for output. V _CS is a voltage that determines the current value of the constant current source transistor. The input and output buffers and the internal gate have the same configuration, but the reference voltages are different, and the drive capability is larger in the input buffer than in the internal gate and larger in the output buffer.

FIG. 4 (a) is a diagram showing the structure inside the I / O gate 14, in which one output buffer and the constituent elements of its reference voltage Vr generating circuit are formed in the region 14a, and the input buffer is formed in the region 14b. Two
A number of components are formed, and in the region 14c, components of a reference voltage V _BB and a reference voltage Vr (for high drive used instead of V _BB ) generation circuit are formed. FIG. 4 (b),
(C) shows an element array formed in the regions 14b and 14c.

FIG. 5A shows the structure of the internal gate 18. At the center of this region, the constituent elements of the reference voltage Vr generating circuit (shown in (b))
Is provided, and three input OR /
Each of the constituent elements (shown in (c)) of the internal gate circuit such as the NOR circuit is provided.

When the bump 10 is formed on the I / O gate 14 as shown in FIG. 1, it becomes as shown in FIG. That is, a transistor is formed on a semiconductor substrate (chip) SUB, each electrode wiring of an emitter E, a base B, and a collector C is attached, an aluminum Al pad is attached to a base electrode wiring serving as an input end, and the periphery is covered with a cover film PSG. , Bumps are formed on this pad. To form bumps, as shown in FIG. 7 (a), a barrier metal is drawn on the Al pad and a solder ball is placed on the Al pad, and this is heated to form a bump, or solder plating is performed on the barrier metal. There is a method of making a solder block, removing the resist, and then heating the solder block to form bumps.

〔The invention's effect〕

As described above, according to the present invention, the chip of the bump mounting type gate array LSI can be subdivided during the execution, and the average wiring length is reduced, the potential variation of the power supply wiring is reduced, the chip size is reduced, and the performance of the gate array is improved. Can be very effective.

[Brief description of drawings]

1 and 2 are explanatory views of the present invention, FIG. 3 is a circuit diagram showing the connection state and configuration of inner and outer gates, and FIG.
FIG. 5 is an explanatory diagram of the O buffer, FIG. 5 is an explanatory diagram of the internal gate, FIG. 6 is an explanatory diagram of a connection state between the gate and the bump, and FIG. 7 is an explanatory diagram of a bump manufacturing procedure. In the drawing, 12 is a semiconductor chip, 10 is a bump, 14 is an I / O gate cell, and 16 is an internal gate cell formation region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/118 H01L 27/04 A (56) References JP-A-57-85244 (JP, A) JP-A-59-119925 (JP, A) JP-A-59-215743 (JP, A)

Claims (2)

[Claims] 1. A large number of bumps are dispersedly arranged on the entire surface of a semiconductor chip, and I / O gate cells of a gate array are arranged along a line that divides the periphery of the chip and the chip surface into a plurality of lines, and internal gate cells are formed. A semiconductor integrated circuit using bump mounting, wherein the semiconductor integrated circuit is arranged inside the divided region. 2. A semiconductor integrated circuit using bump mounting according to claim 1, wherein elements constituting one output buffer and two input buffers are formed in the I / O gate cell. .