JP2842592B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

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Publication number
JP2842592B2
JP2842592B2 JP63189838A JP18983888A JP2842592B2 JP 2842592 B2 JP2842592 B2 JP 2842592B2 JP 63189838 A JP63189838 A JP 63189838A JP 18983888 A JP18983888 A JP 18983888A JP 2842592 B2 JP2842592 B2 JP 2842592B2
Authority
JP
Japan
Prior art keywords
bonding
pads
integrated circuit
semiconductor integrated
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63189838A
Other languages
Japanese (ja)
Other versions
JPH0239446A (en
Inventor
守雄 根本
司 宇根内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Original Assignee
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI AISHII MAIKON SHISUTEMU KK filed Critical NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority to JP63189838A priority Critical patent/JP2842592B2/en
Publication of JPH0239446A publication Critical patent/JPH0239446A/en
Application granted granted Critical
Publication of JP2842592B2 publication Critical patent/JP2842592B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置に関し、特にボンディ
ングパッドに関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a bonding pad.

〔従来の技術〕[Conventional technology]

従来の半導体集積回路装置は、第４図に示すように半
導体チップ２の面積とボンディングの精度によって、制
限された数のボンディングパッドが予めチップ上に配置
されており、各種のパッケージ毎に、より最適位置に近
いパッド１″を上記制限の中で選び、ボンディングワイ
ヤ３により内部配線５と所定の接続を行っていた。In a conventional semiconductor integrated circuit device, as shown in FIG. 4, a limited number of bonding pads are previously arranged on a chip according to the area of the semiconductor chip 2 and the accuracy of bonding. A pad 1 ″ close to the optimum position is selected from the above restrictions, and a predetermined connection is made to the internal wiring 5 by the bonding wire 3.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来の半導体集積回路におけるボンディング
パッドの数は、チップのパッド配置設計当時のボンディ
ング精度により、その配置や数が決められてしまう為、
たとえ、その後にボンディング技術が向上しても、使用
できるパッドの数は、パッドの配置設計当時のボンディ
ング精度で決められたパッド数以上には増やせないとい
う欠点がある。又、新規パッケージへの移行を検討する
上では、既存のパッドの位置の中から、ピンとパッドの
対応を検討せざるをえず、制限事項を守る為に、未使用
ピンを生じたり、逆にボンディング精度上の厳しい対応
を迫られ、組立不良を起こす欠点がある。Since the number of bonding pads in the conventional semiconductor integrated circuit described above is determined by the bonding accuracy at the time of the chip pad layout design, the layout and number are determined.
Even if the bonding technology is improved thereafter, there is a disadvantage that the number of pads that can be used cannot be increased beyond the number of pads determined by the bonding accuracy at the time of pad layout design. Also, when considering the transition to a new package, it is necessary to consider the correspondence between the pins and the pads from the existing pad positions, and to keep the restrictions, unused pins may be generated or conversely There is a drawback that strict measures must be taken with respect to bonding accuracy, resulting in defective assembly.

〔目的〕〔Purpose〕

本発明の目的は、上記欠点を解決し、ボンディングパ
ッドの利用自由度の高い半導体集積回路装置を提供する
ことにある。An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned drawbacks and has a high degree of freedom in using bonding pads.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体集積回路装置は、半導体チップ周縁部
に複数のボンディングパッドが互いに独立して形成さ
れ、かつ前記複数のボンディングパッドの各々は、その
幅がボンディング時に形成されるボールの直径以下とな
っていることを特徴としている。In a semiconductor integrated circuit device according to the present invention, a plurality of bonding pads are formed independently of each other at a peripheral portion of a semiconductor chip, and each of the plurality of bonding pads has a width equal to or less than a diameter of a ball formed at the time of bonding. It is characterized by having.

このような構成により、チップ上のボンディングパッ
ドの自由度を大きくすることができる。With such a configuration, the degree of freedom of the bonding pads on the chip can be increased.

〔実施例〕〔Example〕

以下、本発明の実施例につき図面を参照して説明す
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第１図は、本発明の実施例を示す平面図である。ボン
ディング時に形成されるボールの直径以下に設定された
パッドが半導体チップ２周縁部に配置され、内部配線５
の接続されたパッド１′と隣接するパッド１を用いてボ
ンディングされている。またパッド1,1′間の電気的接
続をより確実にするためにパッド1,1′間にアルミパタ
ン４が施されている。FIG. 1 is a plan view showing an embodiment of the present invention. A pad set to a diameter equal to or less than the diameter of a ball formed at the time of bonding is arranged on the periphery of the semiconductor chip 2 and the internal wiring 5 is formed.
Is bonded using the pad 1 adjacent to the connected pad 1 '. Further, an aluminum pattern 4 is provided between the pads 1 and 1 'in order to ensure the electrical connection between the pads 1 and 1'.

第２図は、第１図に示した実施例において、パッケー
ジの変更等により、使用パッド数が増えた時の実施例で
ある。このようなパッドの配置により従来のものに比
べ、パッドの配置、および本数に対する自由度が大きく
なる。FIG. 2 shows an embodiment in which the number of used pads is increased due to a change in a package or the like in the embodiment shown in FIG. With such pad arrangement, the degree of freedom with respect to pad arrangement and the number of pads is increased as compared with the conventional arrangement.

第３図は、本発明のパッド位置に対する自由度が大き
い事を利用し、パッドの位置を自由に決めた時の実施例
である。FIG. 3 shows an embodiment in which the position of the pad is freely determined by utilizing the large degree of freedom with respect to the pad position according to the present invention.

このように、従来の半導体チップでは出来なかったパ
ッド位置の微調整が可能となる。さらに、ボンディング
精度が向上すれば、チップのパッド数をさらに増やす事
が可能となる。As described above, fine adjustment of the pad position, which cannot be performed by the conventional semiconductor chip, can be performed. Further, if the bonding accuracy is improved, it is possible to further increase the number of pads of the chip.

〔発明の効果〕〔The invention's effect〕

本発明の半導体集積回路装置は、パッドをボンディン
グに要する時に形成されるボールの直径以下に設定し、
且つチップ周囲に配置することによって使用できるパッ
ド数は、ボンディング精度の向上と共に随時増やせ、さ
らに、パッドの位置に対する自由度が大きくなる事によ
って、設計の自由度が大きくなる等の効果がある。In the semiconductor integrated circuit device of the present invention, the pad is set to be equal to or smaller than the diameter of a ball formed when bonding is required,
In addition, the number of pads that can be used by arranging them around the chip can be increased at any time with the improvement of bonding accuracy, and furthermore, the degree of freedom with respect to the position of the pads is increased, so that the degree of freedom in design is increased.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の実施例を示す平面図、第２図は、第１
図の実施例において使用パッド数が増えた時の実施例を
示す平面図、である。第３図は、第１図の実施例におい
て、パッドの位置を自由にレイアウトした場合の実施例
を示す平面図、第４図は、従来例を示す平面図である。 1,1′,1″……ボンディングパッド、２……半導体チッ
プ、３……ボンディングワイヤー、４……アルミパタン
（パッド間ショート用）、５……内部配線。FIG. 1 is a plan view showing an embodiment of the present invention, and FIG.
FIG. 4 is a plan view showing an embodiment when the number of used pads is increased in the embodiment shown in FIG. FIG. 3 is a plan view showing an embodiment in which the positions of the pads are freely laid out in the embodiment of FIG. 1, and FIG. 4 is a plan view showing a conventional example. 1,1 ', 1 "... bonding pad, 2 ... semiconductor chip, 3 ... bonding wire, 4 ... aluminum pattern (for short between pads), 5 ... internal wiring.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 実開 昭59−58941（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60──────────────────────────────────────────────────続 き Continuation of the front page (56) References Japanese Utility Model Showa 59-58941 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半導体チップ周縁部に複数のボンディング
パッドが形成された半導体集積回路装置において、前記
の複数のボンディングパッドは互いに独立して形成さ
れ、かつ前記複数のボンディングパッドの各々は、その
幅がボンディング時に形成されるボールの直径以下とな
っていることを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device in which a plurality of bonding pads are formed on a peripheral portion of a semiconductor chip, the plurality of bonding pads are formed independently of each other, and each of the plurality of bonding pads has a width. Is smaller than the diameter of a ball formed at the time of bonding.
JP63189838A 1988-07-28 1988-07-28 Semiconductor integrated circuit device Expired - Lifetime JP2842592B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63189838A JP2842592B2 (en) 1988-07-28 1988-07-28 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63189838A JP2842592B2 (en) 1988-07-28 1988-07-28 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0239446A JPH0239446A (en) 1990-02-08
JP2842592B2 true JP2842592B2 (en) 1999-01-06

Family

ID=16248054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63189838A Expired - Lifetime JP2842592B2 (en) 1988-07-28 1988-07-28 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2842592B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958941U (en) * 1982-10-13 1984-04-17 日本電気ホームエレクトロニクス株式会社 semiconductor equipment

Also Published As

Publication number Publication date
JPH0239446A (en) 1990-02-08

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