JP3646970B2 - Semiconductor integrated circuit and semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit and semiconductor integrated circuit device Download PDF

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Publication number
JP3646970B2
JP3646970B2 JP14564898A JP14564898A JP3646970B2 JP 3646970 B2 JP3646970 B2 JP 3646970B2 JP 14564898 A JP14564898 A JP 14564898A JP 14564898 A JP14564898 A JP 14564898A JP 3646970 B2 JP3646970 B2 JP 3646970B2
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Japan
Prior art keywords
semiconductor integrated
integrated circuit
pad
wire
circuit
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JP14564898A
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JPH11340272A (en
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孝治 小西
善久 南
勝 安田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路を組み込んだ半導体集積回路装置に関する。
【０００２】
【従来の技術】
図６、図７に、従来技術における複数の半導体集積回路が配置された半導体集積回路装置を示す。
【０００３】
図６に示す半導体集積回路装置においては、第１の半導体集積回路１６と第２の半導体集積回路８が一辺を近接させた状態で同一のコム１７の上に配置されている。しかし、このような構成では、リード１１とパッド１２との間の距離やリードフレームと半導体集積回路の構造上の問題で、リード１１からのワイヤーボンドが不可能なパッド群１３が生じてしまい、このようなパッドへの配線は、リードからのワイヤーボンドが可能な他のパッドへ配線を変更する必要がある。このため、変更された側のパッドに接続されていた配線は使用不可能となり、場合によっては使用不可能な回路ブロックが発生してしまうことになる。
【０００４】
また、上記のような使用不可能なパッド群（回路ブロック）が発生するという不具合を解消するために、図７に示すように、第１の半導体集積回路９と第２の半導体集積回路１０のパッド１２のすべてを、リード１１からワイヤーボンドが可能な位置に配置替えする技術が提案されている。しかし、この技術では、マスクの修正が必要となり、また、新規に作製するマスクに対策を施すとしても、図６、図７から明らかなように、ワイヤーボンドが可能なリード１１が各々のチップが存在する方面に偏ってしまい、ピン配置設計時に制約を受けてしまうという問題が残る。また、このようなパッド１２の配置替えが行われた半導体集積回路（例えば、図７の第１の半導体集積回路９）を将来単独で使用するような状況になった場合には、図８に示すように、パッド１２が無い部分のリード群１４が余ってしまう。このため、最低の必要リード数よりもリード１１の多いコムを使用することになり、コストアップに繋がってしまう。また、従来、ピン間容量結合が問題となる場合、あるいは図９に示す半導体集積回路装置においてリードＡと隣に位置するリードＢ、Ｃとの結合が問題となるような場合には、リードＢとリードＣを、ＮＣピンとすることによって、又はワイヤーボンドを行うことなくＶＣＣ又はＧＮＤ等のバイアスに接地することによって対応していたが、半導体集積回路上にワイヤーボンドされたワイヤー間の容量結合１５は免れることができないという問題が残る。
【０００５】
【発明が解決しようとする課題】
上記したように、複数の半導体集積回路を同一の半導体集積回路装置内に配置する場合には、以下のような５つの問題が生じる。すなわち、
（１）図６に示すように、リードと半導体集積回路のパッドレイアウトとの関係上、ワイヤーボンドが不可能なパッド群が生じてしまう。
（２）上記（１）の問題をできる限り解消するためには、図７に示すように、半導体集積回路上のパッドレイアウトを変更する必要がある。
（３）上記（１）の問題を解消することができるように最初からパッドレイアウトを設計したとしても、各々の半導体集積回路へワイヤーボンドが可能なリードはその各々の半導体集積回路の周辺に偏ってしまい、ピン配置が制限されてしまう。
（４）図７に示すように、複数の半導体集積回路を配置するパッドレイアウトに設計された場合、パッドが半導体集積回路の４辺のうちほぼ３辺に集中してしまう。このパッドレイアウトは、この半導体集積回路を別の用途で単独の半導体集積回路として使用する場合には、非常に不合理なレイアウトであり、場合によっては図８に示すように逆にＮＣリードが発生し、必要リード数よりもリードの多いコムを使用しなくてはならず、コストアップに繋がってしまう。
（５）従来の技術においては、回路動作的に他の回路との容量結合による干渉を回避したい場合、ＮＣピンを図９に示すように設けて対応しているが、ワイヤー間容量結合及び半導体集積回路上の他の回路との配線間容量結合を防止することはできない。
【０００６】
本発明は、従来技術における前記課題を解決するためになされたものであり、高性能な半導体集積回路を組み込んだ半導体集積回路装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
前記目的を達成するため、本発明に係る半導体集積回路装置の第１の構成は、半導体集積回路と、該半導体集積回路の周辺に配置された複数のリードと、該複数のリードの一部のそれぞれにワイヤーボンドで接続され、かつ、前記半導体集積回路上の回路と配線で接続された、前記半導体集積回路上の第１のワイヤーボンド用パッドと、前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、互いに配線で接続された、前記半導体集積回路上の一組の第２のワイヤーボンド用パッドとを備え、前記第２のワイヤーボンド用パッドに接続された配線、ワイヤー及びリードが、前記第１のワイヤーボンド用パッドに接続された回路を囲むように配置されたことを特徴とする。この半導体集積回路装置の第１の構成によれば、任意のリードから半導体集積回路上の第２のワイヤーボンド用パッドの１つにワイヤーボンドし、当該１つの第２のワイヤーボンド用パッドと互いに接続された他の第２のワイヤーボンド用パッドに他の任意のリードからワイヤーボンドすることができる。その結果、一部の回路を他の回路からシールドする上で、リード間、ワイヤー間及び配線間のすべてをシールドすることによって完全なシールドを可能にすることができる。すなわち、従来技術においては、リード間はシールドできてワイヤーボンドを行わなかった場合にワイヤー間及び半導体集積回路間の結合が残ってしまうが、半導体集積回路上の回路に接続されることなく互いに接続される一組の第２のワイヤーボンド用パッドを備えた半導体集積回路を用いれば、この結合を取り除くことができる。
【０００９】
また、本発明に係る半導体集積回路装置の第２の構成は、半導体集積回路と、該半導体集積回路の周辺に配置された複数のリードと、該複数のリードの一部のそれぞれにワイヤーボンドで接続され、かつ、前記半導体集積回路上の回路と配線で接続された、前記半導体集積回路上の第１のワイヤーボンド用パッドと、前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、前記半導体集積回路上で単独に配置された第３のワイヤーボンド用パッドとを備え、前記第３のワイヤーボンド用パッドに接続されたワイヤーが、前記第１のワイヤーボンド用パッドに接続されたワイヤー間に配置されたことを特徴とする。この半導体集積回路装置の第２の構成によれば、任意のリードから半導体集積回路上の回路及び他のワイヤーボンド用パッドのどちらにも接続されることなく単独で存在する第３のワイヤーボンド用パッドにワイヤーボンドすることができる。リード間容量結合が問題となる場合には、以上のような半導体集積回路上の回路及び他のワイヤーボンド用パッドのどちらにも接続されることなく単独で存在する第３のワイヤーボンド用パッドを備えた半導体集積回路を用いることにより、これを防止することができる。
【００１０】
また、本発明に係る半導体集積回路装置の第３の構成は、第１の半導体集積回路と、該第１の半導体集積回路と近接して同一のコム上に配置された第２の半導体集積回路と、前記第１及び第２の半導体集積回路の周辺に配置された複数のリードと、該複数のリードの一部のそれぞれにワイヤーボンドで接続され、かつ、前記第１の半導体集積回路上の回路と配線で接続された、前記第１の半導体集積回路上の第１のワイヤーボンド用パッドと、前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、互いに配線で接続された、前記第１の半導体集積回路上の一組の第２のワイヤーボンド用パッドと、前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、前記第１の半導体集積回路上で単独に配置された第３のワイヤーボンド用パッドとを備え、前記第２のワイヤーボンド用パッドに接続された配線、ワイヤー及びリードが、前記第１のワイヤーボンド用パッドに接続された回路を囲むように配置され、前記第３のワイヤーボンド用パッドに接続されたワイヤーが、前記第１のワイヤーボンド用パッドに接続されたワイヤー間に配置されたことを特徴とする。この半導体集積回路装置の第３の構成によれば、任意のリードから第１の半導体集積回路上の第２のワイヤーボンド用パッドの１つにワイヤーボンドし、当該１つの第２のワイヤーボンド用パッドと互いに接続された他の第２のワイヤーボンド用パッドからさらに第２の半導体集積回路のパッドにリードを経由することなくワイヤーボンドすることができる。さらに、第１の半導体集積回路に、任意のリードから第１の半導体集積回路上の第３のワイヤーボンド用パッドにワイヤーボンドすることができる。その結果、同一の半導体集積回路装置内に複数の半導体集積回路を配置する場合に発生する、パッド配置設計上の問題、ピン配置設計上の問題や回路の高性能化に問題となるワイヤー間、配線間容量等の多くの問題を一度に解決することができる。
【００１１】
【発明の実施の形態】
以下、実施の形態を用いて本発明をさらに具体的に説明する。
〈第１の実施の形態〉
図１は本実施の形態における半導体集積回路を示す平面図である。
【００１２】
図１に示すように、半導体集積回路１におけるワイヤーボンド用パッドは、半導体集積回路１上の回路に接続される第１のパッド２と、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との３種類からなっている。
【００１３】
この半導体集積回路１は、以下の第２〜第５の実施の形態における半導体集積回路装置の１つ半導体集積回路として用いられるものであり、この半導体集積回路１を半導体集積回路装置の１つの半導体集積回路として用いることにより、前記した従来の諸課題を解決するものであることができる。
【００１４】
従って、本実施の形態においては、ワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類を設けているが、必ずしもこの構成に限定されるものではなく、少なくともどちらか一方のパッド（第２のパッド３又は第３のパッド４）が設けられていればよい。
【００１５】
〈第２の実施の形態〉
図２は本実施の形態における半導体集積回路装置を示す平面図である。
図２において、１は上記第１の実施の形態で示した半導体集積回路（第１の半導体集積回路）であり、第１の半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類が設けられている。また、７はその一辺が第１の半導体集積回路１の一辺と近接した状態で同一のコム６上に配置された第２の半導体集積回路である。
【００１６】
第１及び第２の半導体集積回路１、７には、リードから通常のワイヤーボンディングによってワイヤーボンドされる。また、任意のリード５から第１の半導体集積回路１上の第２のパッド３（第１の半導体集積回路１上の回路に接続されることなく互いに接続される複数のパッド）の１つにワイヤーボンドされ、当該１つの第２のパッド３と互いに接続された他の第２のパッド３からさらに第２の半導体集積回路７のパッドにリードを経由することなくワイヤーボンドされる。
【００１７】
以上のように、半導体集積回路上の回路に接続されることなく互いに接続される複数の第２のパッド３を備えた第１の半導体集積回路１を用いることにより、第１及び第２の半導体集積回路１、７上にワイヤーボンドが不可能なパッド群が生じることがないと共に、半導体集積回路上のパッドレイアウトを変更する必要もない。また、ピン配置が制限されてしまうことがないと共に、必要リード数よりもリードの多いコムを使用する必要がないので、コストの削減を図ることができる。
【００１８】
具体的には、第２の半導体集積回路７が既に設計が完了した既存の半導体集積回路である場合でも、第１の半導体集積回路１と複数チップ化するに当たって、第２の半導体集積回路７のパッド位置を変更することなく、第１の半導体集積回路１を設計する場合に第２の半導体集積回路７へのワイヤーボンドを考慮してパッドを配置すればよい。その結果、図６の従来例に示すようにワイヤーボンドが不可能なパッド群が生じることはないと共に、図７の従来例に示すようにパッド位置を変更する必要もない。また、第１の半導体集積回路１を別途単独で使用する場合であっても、ＮＣリードが生じることはない。
【００１９】
尚、本実施の形態においては、第１の半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類を設けているが、必ずしもこの構成に限定されるものではなく、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３が設けられていればよい。
【００２０】
また、本実施の形態においては、第１の半導体集積回路１と第２の半導体集積回路７がそれぞれ１個の場合を例に挙げて説明しているが、必ずしもこの構成に限定されるものではなく、それぞれ任意の数の半導体集積回路を用いて半導体集積回路装置を構成してもよい。
【００２１】
〈第３の実施の形態〉
図３は本実施の形態における半導体集積回路装置を示す平面図である。
図３において、１は上記第１の実施の形態で示した半導体集積回路であり、半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類が設けられている。
【００２２】
半導体集積回路１には、任意のリード５ａから半導体集積回路１上の第２のパッド３（半導体集積回路１上の回路に接続されることなく互いに接続される複数のパッド）の１つにワイヤーボンドされ、当該１つの第２のパッド３と互いに接続された他の第２のパッド３には他の任意のリード５ｂからワイヤーボンドされる。
【００２３】
以上のような半導体集積回路上の回路に接続されることなく互いに接続される複数の第２のパッド３を備えた半導体集積回路１を用いれば、一部の回路を他の回路からシールドする上で、リード間、ワイヤー間及び配線間のすべてをシールドすることによって完全なシールドを可能にすることができる。すなわち、図９の従来例に示すようにリード間はシールドできてワイヤーボンドを行わなかった場合にはワイヤー間及び半導体集積回路間の結合が残ってしまうが、半導体集積回路上の回路に接続されることなく互いに接続される複数の第２のパッド３を備えた半導体集積回路１を用いれば、この結合を取り除くことができる。
【００２４】
尚、本実施の形態においては、半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類を設けているが、必ずしもこの構成に限定されるものではなく、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３が設けられていればよい。
【００２５】
〈第４の実施の形態〉
図４は本実施の形態における半導体集積回路装置を示す平面図である。
図４において、１は上記第１の実施の形態で示した半導体集積回路であり、半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類が設けられている。
【００２６】
半導体集積回路１には、任意のリード５から半導体集積回路１上の第３のパッド４（半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在するパッド）にワイヤーボンドされる。
【００２７】
図９の従来例に示すように、リード間容量結合が問題となる場合にはＮＣリードが設けられるが、さらにワイヤー間の容量結合が問題になる場合には、以上のような半導体集積回路上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４を備えた半導体集積回路１を用いることにより、これを防止することができる。
【００２８】
尚、本実施の形態においては、半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類を設けているが、必ずしもこの構成に限定されるものではなく、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４が設けられていればよい。
【００２９】
〈第５の実施の形態〉
図５は本実施の形態における半導体集積回路装置を示す平面図である。
図５において、１は上記第１の実施の形態で示した半導体集積回路（第１の半導体集積回路）であり、第１の半導体集積回路１上のワイヤーボンド用パッドとして、半導体集積回路１上の回路に接続される第１のパッド２の他に、半導体集積回路１上の回路に接続されることなく互いに接続される複数の第２のパッド３と、半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在する第３のパッド４との２種類が設けられている。また、７はその一辺が第１の半導体集積回路１の一辺と近接した状態で同一のコム６上に配置された第２の半導体集積回路である。
【００３０】
第１及び第２の半導体集積回路１、７には、リードから通常のワイヤーボンディングによってワイヤーボンドされる。また、任意のリード１８から第１の半導体集積回路１上の第２のパッド３（第１の半導体集積回路１上の回路に接続されることなく互いに接続される複数のパッド）の１つにワイヤーボンドされ、当該１つの第２のパッド３と互いに接続された他の第２のパッド３からさらに第２の半導体集積回路７のパッドにリードを経由することなくワイヤーボンドされる。さらに、第１の半導体集積回路１には、任意のリード１９から第１の半導体集積回路１上の第３のパッド４（半導体集積回路１上の回路及び他のパッドのどちらにも接続されることなく単独で存在するパッド）にワイヤーボンドされる。
【００３１】
本実施の形態によれば、同一の半導体集積回路装置内に複数の半導体集積回路を配置する場合に発生する、パッド配置設計上の問題、ピン配置設計上の問題や回路の高性能化に問題となるワイヤー間、配線間容量等の多くの問題を一度に解決することができる。
【００３２】
尚、本実施の形態においては、第１の半導体集積回路１と第２の半導体集積回路７がそれぞれ１個の場合を例に挙げて説明しているが、必ずしもこの構成に限定されるものではなく、それぞれ任意の数の半導体集積回路を用いて半導体集積回路装置を構成してもよい。
【００３３】
【発明の効果】
以上説明したように、本発明によれば、同一の半導体集積回路装置内に複数の半導体集積回路を配置する場合において発生する諸問題、集積回路上のパッド配置の問題、それに伴うピン配置の問題や各種の容量結合の問題を解決することができる。その結果、半導体集積回路装置の大幅な性能の向上が可能となり、半導体集積回路そのものの再利用時や他に派生使用する場合の活用性を極めて増大させることが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態における半導体集積回路を示す平面図である。
【図２】本発明の第２の実施の形態における半導体集積回路装置を示す平面図である。
【図３】本発明の第３の実施の形態における半導体集積回路装置を示す平面図である。
【図４】本発明の第４の実施の形態における半導体集積回路装置を示す平面図である。
【図５】本発明の第５の実施の形態における半導体集積回路装置を示す平面図である。
【図６】従来技術における複数の半導体集積回路が配置された半導体集積回路装置の一例を示す平面図である。
【図７】従来技術における複数の半導体集積回路が配置された半導体集積回路装置の他の例を示す平面図である。
【図８】従来技術における１個の複数の半導体集積回路が配置された半導体集積回路装置の一例を示す平面図である。
【図９】従来技術における１個の複数の半導体集積回路が配置された半導体集積回路装置の他の例を示す平面図である。
【符号の説明】
１、７ 半導体集積回路
２ 第１のパッド
３ 第２のパッド
４ 第３のパッド
６ コム
５、５ａ、５ｂ、１８、１９ リード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device incorporating the semiconductor integrated circuits.
[0002]
[Prior art]
6 and 7 show a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuits in the prior art are arranged.
[0003]
In the semiconductor integrated circuit device shown in FIG. 6, the first semiconductor integrated circuit 16 and the second semiconductor integrated circuit 8 are arranged on the same comb 17 in a state where one side is close to the other. However, in such a configuration, a pad group 13 that cannot be wire-bonded from the lead 11 is generated due to the distance between the lead 11 and the pad 12 or the structural problem of the lead frame and the semiconductor integrated circuit. For wiring to such a pad, it is necessary to change the wiring to another pad capable of wire bonding from the lead. For this reason, the wiring connected to the changed pad becomes unusable, and in some cases, an unusable circuit block is generated.
[0004]
Further, in order to solve the problem that the above unusable pad group (circuit block) occurs, as shown in FIG. 7, the first semiconductor integrated circuit 9 and the second semiconductor integrated circuit 10 A technique has been proposed in which all of the pads 12 are rearranged from the leads 11 to positions where wire bonding is possible. However, with this technique, it is necessary to modify the mask, and even if measures are taken for a newly manufactured mask, as is apparent from FIGS. 6 and 7, leads 11 capable of wire bonding are provided on each chip. The problem remains that it tends to be biased in the existing direction and is subject to restrictions during pin arrangement design. Further, in the case where the semiconductor integrated circuit (for example, the first semiconductor integrated circuit 9 in FIG. 7) in which the pads 12 have been rearranged is used alone in the future, FIG. As shown, a portion of the lead group 14 where there is no pad 12 is left. For this reason, a comb having more leads 11 than the minimum required number of leads is used, leading to an increase in cost. Conventionally, when capacitive coupling between pins becomes a problem or when coupling between lead A and adjacent leads B and C in the semiconductor integrated circuit device shown in FIG. And lead C as NC pins or grounded to a bias such as VCC or GND without wire bonding, but capacitive coupling between wires wire-bonded on a semiconductor integrated circuit 15 The problem remains that it cannot be avoided.
[0005]
[Problems to be solved by the invention]
As described above, when a plurality of semiconductor integrated circuits are arranged in the same semiconductor integrated circuit device, the following five problems arise. That is,
(1) As shown in FIG. 6, due to the relationship between the leads and the pad layout of the semiconductor integrated circuit, a pad group in which wire bonding is impossible occurs.
(2) In order to eliminate the problem (1) as much as possible, it is necessary to change the pad layout on the semiconductor integrated circuit as shown in FIG.
(3) Even if the pad layout is designed from the beginning so as to solve the problem (1), the lead capable of wire bonding to each semiconductor integrated circuit is biased to the periphery of each semiconductor integrated circuit. As a result, pin arrangement is limited.
(4) As shown in FIG. 7, when the pad layout in which a plurality of semiconductor integrated circuits are arranged is designed, the pads are concentrated on almost three sides of the four sides of the semiconductor integrated circuit. This pad layout is a very unreasonable layout when this semiconductor integrated circuit is used as a single semiconductor integrated circuit for another purpose. In some cases, NC leads are generated as shown in FIG. However, it is necessary to use a comb having more leads than the necessary number of leads, leading to an increase in cost.
(5) In the prior art, when it is desired to avoid interference due to capacitive coupling with other circuits in terms of circuit operation, an NC pin is provided as shown in FIG. Capacitive coupling between wirings with other circuits on the integrated circuit cannot be prevented.
[0006]
The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a semiconductor integrated circuit device incorporating a high-performance semiconductor integrated circuits.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a first configuration of a semiconductor integrated circuit device according to the present invention includes a semiconductor integrated circuit, a plurality of leads arranged around the semiconductor integrated circuit, and a part of the plurality of leads. A first wire bond pad on the semiconductor integrated circuit connected to each other by a wire bond and connected to a circuit on the semiconductor integrated circuit by wiring, and each of the other part of the plurality of leads And a pair of second wire bond pads on the semiconductor integrated circuit that are connected to each other by wire bonds and connected to each other by wires, and the wires connected to the second wire bond pads, The wire and the lead are arranged so as to surround a circuit connected to the first wire bonding pad . According to the first configuration of the semiconductor integrated circuit device, wire bonding is performed from an arbitrary lead to one of the second wire bonding pads on the semiconductor integrated circuit, and the one second wire bonding pad is mutually connected. It is possible to wire bond from any other lead to the other connected second wire bonding pads. As a result, in shielding some circuits from other circuits, complete shielding can be achieved by shielding everything between leads, wires, and wiring. In other words, in the prior art, when the leads can be shielded and wire bonding is not performed, the coupling between the wires and the semiconductor integrated circuit remains, but they are connected to each other without being connected to the circuit on the semiconductor integrated circuit. This coupling can be removed by using a semiconductor integrated circuit having a pair of second wire bonding pads.
[0009]
A second configuration of the semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit, a plurality of leads arranged around the semiconductor integrated circuit, and a wire bond to each of a part of the plurality of leads. Connected to each of the first wire bond pads on the semiconductor integrated circuit and connected to the circuits on the semiconductor integrated circuit by wires and to each of the other parts of the plurality of leads. And a third wire bond pad disposed independently on the semiconductor integrated circuit, and the wire connected to the third wire bond pad is used as the first wire bond pad. It is arranged between connected wires . According to the second configuration of this semiconductor integrated circuit device, the third wire bond exists independently from any lead without being connected to either the circuit on the semiconductor integrated circuit or another wire bond pad . It can be wire bonded to the pad. If the inter-lead capacitance coupling is a problem, a third pad for wire bonding which is present singly without being connected to either the above-described semiconductor integrated circuit circuits and other pads for wire bonding on This can be prevented by using the provided semiconductor integrated circuit.
[0010]
A third configuration of the semiconductor integrated circuit device according to the present invention includes a first semiconductor integrated circuit and a second semiconductor integrated circuit disposed on the same comb in the vicinity of the first semiconductor integrated circuit. A plurality of leads arranged around the first and second semiconductor integrated circuits, and a plurality of leads connected to each of the leads by wire bonds, and on the first semiconductor integrated circuit The first wire bonding pad on the first semiconductor integrated circuit connected to the circuit by wiring and the other part of the plurality of leads are connected by wire bonding and connected to each other by wiring. A pair of second wire bond pads on the first semiconductor integrated circuit, and each of the other parts of the plurality of leads connected by wire bonds, and the first semiconductor integrated circuit Place alone on the circuit A third wire bond pad, and a wiring, a wire and a lead connected to the second wire bond pad are arranged so as to surround a circuit connected to the first wire bond pad. The wire connected to the third wire bond pad is disposed between the wires connected to the first wire bond pad . According to the third configuration of the semiconductor integrated circuit device, wire bonding is performed from an arbitrary lead to one of the second wire bonding pads on the first semiconductor integrated circuit, and the one second wire bonding is performed. Wire bonding can be performed from another second wire bonding pad connected to the pad to the pad of the second semiconductor integrated circuit without passing through a lead. Furthermore, the first semiconductor integrated circuit can be wire-bonded from an arbitrary lead to the third wire-bonding pad on the first semiconductor integrated circuit. As a result, when arranging a plurality of semiconductor integrated circuits in the same semiconductor integrated circuit device, problems in pad layout design, problems in pin layout design, and between wires that cause problems in circuit performance, Many problems such as inter-wiring capacitance can be solved at once.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described more specifically using embodiments.
<First Embodiment>
FIG. 1 is a plan view showing a semiconductor integrated circuit according to the present embodiment.
[0012]
As shown in FIG. 1, the wire bond pads in the semiconductor integrated circuit 1 are connected to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1 and to the circuit on the semiconductor integrated circuit 1 without being connected to each other. A plurality of second pads 3 to be connected and a third pad 4 that exists independently without being connected to any of the circuits on the semiconductor integrated circuit 1 and other pads.
[0013]
The semiconductor integrated circuit 1 is used as a semiconductor integrated circuit of one of the semiconductor integrated circuit devices in the following second to fifth embodiments, and this semiconductor integrated circuit 1 is used as one semiconductor of the semiconductor integrated circuit device. By using it as an integrated circuit, the conventional problems described above can be solved.
[0014]
Therefore, in the present embodiment, the wire bond pads are connected to each other without being connected to the circuit on the semiconductor integrated circuit 1 in addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1. There are provided two types of second pads 3 and third pads 4 that exist independently without being connected to any of the circuits on the semiconductor integrated circuit 1 and other pads. It is not necessarily limited to this configuration, and at least one of the pads (the second pad 3 or the third pad 4) may be provided.
[0015]
<Second Embodiment>
FIG. 2 is a plan view showing the semiconductor integrated circuit device according to the present embodiment.
In FIG. 2, reference numeral 1 denotes the semiconductor integrated circuit (first semiconductor integrated circuit) shown in the first embodiment. As a wire bond pad on the first semiconductor integrated circuit 1, on the semiconductor integrated circuit 1. A plurality of second pads 3 connected to each other without being connected to a circuit on the semiconductor integrated circuit 1, a circuit on the semiconductor integrated circuit 1, and others There are two types of pads, the third pad 4 that exists independently without being connected to either of the pads. Reference numeral 7 denotes a second semiconductor integrated circuit disposed on the same comb 6 with one side thereof close to one side of the first semiconductor integrated circuit 1.
[0016]
The first and second semiconductor integrated circuits 1 and 7 are wire-bonded from the leads by ordinary wire bonding. Also, from any lead 5 to one of the second pads 3 on the first semiconductor integrated circuit 1 (a plurality of pads connected to each other without being connected to the circuit on the first semiconductor integrated circuit 1). Wire bonding is performed, and another second pad 3 connected to the one second pad 3 is further bonded to a pad of the second semiconductor integrated circuit 7 without passing through a lead.
[0017]
As described above, by using the first semiconductor integrated circuit 1 including the plurality of second pads 3 connected to each other without being connected to a circuit on the semiconductor integrated circuit, the first and second semiconductors are used. There is no generation of pads that cannot be wire-bonded on the integrated circuits 1 and 7, and there is no need to change the pad layout on the semiconductor integrated circuit. Further, the pin arrangement is not limited, and it is not necessary to use a comb having more leads than the required number of leads, so that the cost can be reduced.
[0018]
Specifically, even when the second semiconductor integrated circuit 7 is an existing semiconductor integrated circuit whose design has already been completed, when the second semiconductor integrated circuit 7 is formed into a plurality of chips with the first semiconductor integrated circuit 1, The pads may be arranged in consideration of wire bonds to the second semiconductor integrated circuit 7 when designing the first semiconductor integrated circuit 1 without changing the pad position. As a result, a pad group that cannot be wire-bonded does not occur as shown in the conventional example of FIG. 6, and the pad position does not need to be changed as shown in the conventional example of FIG. Further, even when the first semiconductor integrated circuit 1 is separately used separately, NC lead does not occur.
[0019]
In this embodiment, in addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1 as the wire bond pad on the first semiconductor integrated circuit 1, the pad on the semiconductor integrated circuit 1 is used. A plurality of second pads 3 which are connected to each other without being connected to a circuit, and a third pad 4 which is present independently without being connected to either the circuit on the semiconductor integrated circuit 1 or another pad; However, the present invention is not necessarily limited to this configuration. In addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1, it is connected to the circuit on the semiconductor integrated circuit 1. It is only necessary to provide a plurality of second pads 3 that are connected to each other without being connected.
[0020]
In the present embodiment, the case where there is one each of the first semiconductor integrated circuit 1 and the second semiconductor integrated circuit 7 is described as an example. However, the present invention is not necessarily limited to this configuration. Alternatively, the semiconductor integrated circuit device may be configured using any number of semiconductor integrated circuits.
[0021]
<Third Embodiment>
FIG. 3 is a plan view showing the semiconductor integrated circuit device according to the present embodiment.
In FIG. 3, reference numeral 1 denotes the semiconductor integrated circuit shown in the first embodiment, and a first pad 2 connected to a circuit on the semiconductor integrated circuit 1 as a wire bond pad on the semiconductor integrated circuit 1. In addition, a plurality of second pads 3 connected to each other without being connected to a circuit on the semiconductor integrated circuit 1, and without being connected to any of the circuit on the semiconductor integrated circuit 1 and other pads Two types are provided, the third pad 4 existing alone.
[0022]
In the semiconductor integrated circuit 1, a wire is connected from one arbitrary lead 5a to one of the second pads 3 on the semiconductor integrated circuit 1 (a plurality of pads connected to each other without being connected to the circuit on the semiconductor integrated circuit 1). The other second pad 3 that is bonded and connected to the one second pad 3 is wire-bonded from any other lead 5b.
[0023]
If the semiconductor integrated circuit 1 including the plurality of second pads 3 connected to each other without being connected to the circuit on the semiconductor integrated circuit as described above is used, a part of the circuit is shielded from other circuits. Thus, complete shielding can be made possible by shielding everything between leads, between wires and between wires. That is, as shown in the conventional example of FIG. 9, when the leads can be shielded and wire bonding is not performed, the connection between the wires and the semiconductor integrated circuit remains, but it is connected to the circuit on the semiconductor integrated circuit. If the semiconductor integrated circuit 1 having a plurality of second pads 3 connected to each other without using the semiconductor integrated circuit 1 is used, this coupling can be removed.
[0024]
In the present embodiment, the wire bond pad on the semiconductor integrated circuit 1 is connected to the circuit on the semiconductor integrated circuit 1 in addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1. Two types of a plurality of second pads 3 that are connected to each other without being connected, and a third pad 4 that exists independently without being connected to either the circuit on the semiconductor integrated circuit 1 or another pad However, the present invention is not necessarily limited to this configuration, and is not connected to the circuit on the semiconductor integrated circuit 1 in addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1. It is only necessary to provide a plurality of second pads 3 connected to each other.
[0025]
<Fourth embodiment>
FIG. 4 is a plan view showing the semiconductor integrated circuit device according to the present embodiment.
In FIG. 4, reference numeral 1 denotes the semiconductor integrated circuit shown in the first embodiment, and a first pad 2 connected to a circuit on the semiconductor integrated circuit 1 as a wire bond pad on the semiconductor integrated circuit 1. In addition, a plurality of second pads 3 connected to each other without being connected to a circuit on the semiconductor integrated circuit 1, and without being connected to any of the circuit on the semiconductor integrated circuit 1 and other pads Two types are provided, the third pad 4 existing alone.
[0026]
In the semiconductor integrated circuit 1, a third pad 4 on the semiconductor integrated circuit 1 from an arbitrary lead 5 (a pad that exists independently without being connected to either the circuit on the semiconductor integrated circuit 1 or another pad) Wire bonded to.
[0027]
As shown in the conventional example of FIG. 9, an NC lead is provided when capacitive coupling between leads becomes a problem. However, when capacitive coupling between wires becomes a problem, the above-described semiconductor integrated circuit is provided. This can be prevented by using the semiconductor integrated circuit 1 provided with the third pad 4 that exists independently without being connected to either the circuit or other pads.
[0028]
In the present embodiment, the wire bond pad on the semiconductor integrated circuit 1 is connected to the circuit on the semiconductor integrated circuit 1 in addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1. Two types of a plurality of second pads 3 that are connected to each other without being connected, and a third pad 4 that exists independently without being connected to either the circuit on the semiconductor integrated circuit 1 or another pad However, the present invention is not necessarily limited to this configuration. In addition to the first pad 2 connected to the circuit on the semiconductor integrated circuit 1, either the circuit on the semiconductor integrated circuit 1 or another pad It is only necessary to provide the third pad 4 that exists independently without being connected to the other.
[0029]
<Fifth embodiment>
FIG. 5 is a plan view showing the semiconductor integrated circuit device according to the present embodiment.
In FIG. 5, reference numeral 1 denotes the semiconductor integrated circuit (first semiconductor integrated circuit) shown in the first embodiment. As a wire bond pad on the first semiconductor integrated circuit 1, A plurality of second pads 3 connected to each other without being connected to a circuit on the semiconductor integrated circuit 1, a circuit on the semiconductor integrated circuit 1, and others There are two types of pads, the third pad 4 that exists independently without being connected to either of the pads. Reference numeral 7 denotes a second semiconductor integrated circuit disposed on the same comb 6 with one side thereof close to one side of the first semiconductor integrated circuit 1.
[0030]
The first and second semiconductor integrated circuits 1 and 7 are wire-bonded from the leads by ordinary wire bonding. Also, from any lead 18 to one of the second pads 3 on the first semiconductor integrated circuit 1 (a plurality of pads connected to each other without being connected to the circuit on the first semiconductor integrated circuit 1). Wire bonding is performed, and another second pad 3 connected to the one second pad 3 is further bonded to a pad of the second semiconductor integrated circuit 7 without passing through a lead. Further, the first semiconductor integrated circuit 1 is connected to an arbitrary lead 19 from the third pad 4 on the first semiconductor integrated circuit 1 (both the circuit on the semiconductor integrated circuit 1 and other pads). Without being wire-bonded to the pad that exists alone).
[0031]
According to the present embodiment, there are problems in pad arrangement design, pin arrangement design, and circuit performance that occur when a plurality of semiconductor integrated circuits are arranged in the same semiconductor integrated circuit device. Many problems such as inter-wire and inter-wiring capacitance can be solved at once.
[0032]
In the present embodiment, the case where there is one each of the first semiconductor integrated circuit 1 and the second semiconductor integrated circuit 7 is described as an example. However, the present invention is not necessarily limited to this configuration. Alternatively, the semiconductor integrated circuit device may be configured using any number of semiconductor integrated circuits.
[0033]
【The invention's effect】
As described above, according to the present invention, various problems that occur when a plurality of semiconductor integrated circuits are arranged in the same semiconductor integrated circuit device, a problem of pad arrangement on the integrated circuit, and a problem of pin arrangement associated therewith. And various capacitive coupling problems can be solved. As a result, it is possible to greatly improve the performance of the semiconductor integrated circuit device, and it is possible to greatly increase the usability when the semiconductor integrated circuit itself is reused or derived from others.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 3 is a plan view showing a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 4 is a plan view showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
FIG. 5 is a plan view showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
FIG. 6 is a plan view showing an example of a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuits are arranged in the prior art.
FIG. 7 is a plan view showing another example of a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuits are arranged in the prior art.
FIG. 8 is a plan view showing an example of a semiconductor integrated circuit device in which one semiconductor integrated circuit is arranged in the prior art.
FIG. 9 is a plan view showing another example of a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuits are arranged in the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 7 Semiconductor integrated circuit 2 1st pad 3 2nd pad 4 3rd pad 6 Com5, 5a, 5b, 18, 19 Lead

Claims (3)

半導体集積回路と、
該半導体集積回路の周辺に配置された複数のリードと、
該複数のリードの一部のそれぞれにワイヤーボンドで接続され、かつ、前記半導体集積回路上の回路と配線で接続された、前記半導体集積回路上の第１のワイヤーボンド用パッドと、
前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、互いに配線で接続された、前記半導体集積回路上の一組の第２のワイヤーボンド用パッドとを備え、
前記第２のワイヤーボンド用パッドに接続された配線、ワイヤー及びリードが、前記第１のワイヤーボンド用パッドに接続された回路を囲むように配置されたことを特徴とする半導体集積回路装置。 A semiconductor integrated circuit;
A plurality of leads disposed around the semiconductor integrated circuit;
A first wire bond pad on the semiconductor integrated circuit connected to each of a part of the plurality of leads by a wire bond and connected to a circuit on the semiconductor integrated circuit by a wiring;
A set of second wire bonding pads on the semiconductor integrated circuit connected to each other part of the plurality of leads by wire bonds and connected to each other by wiring;
A semiconductor integrated circuit device , wherein a wiring, a wire, and a lead connected to the second wire bonding pad are arranged so as to surround a circuit connected to the first wire bonding pad . 半導体集積回路と、
該半導体集積回路の周辺に配置された複数のリードと、
該複数のリードの一部のそれぞれにワイヤーボンドで接続され、かつ、前記半導体集積回路上の回路と配線で接続された、前記半導体集積回路上の第１のワイヤーボンド用パッドと、
前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、前記半導体集積回路上で単独に配置された第３のワイヤーボンド用パッドとを備え、
前記第３のワイヤーボンド用パッドに接続されたワイヤーが、前記第１のワイヤーボンド用パッドに接続されたワイヤー間に配置されたことを特徴とする半導体集積回路装置。 A semiconductor integrated circuit;
A plurality of leads disposed around the semiconductor integrated circuit;
A first wire bond pad on the semiconductor integrated circuit connected to each of a part of the plurality of leads by a wire bond and connected to a circuit on the semiconductor integrated circuit by a wiring;
A third wire bonding pad connected to each of the other part of the plurality of leads by a wire bond and disposed independently on the semiconductor integrated circuit,
A semiconductor integrated circuit device , wherein a wire connected to the third wire bond pad is disposed between wires connected to the first wire bond pad . 第１の半導体集積回路と、
該第１の半導体集積回路と近接して同一のコム上に配置された第２の半導体集積回路と、
前記第１及び第２の半導体集積回路の周辺に配置された複数のリードと、
該複数のリードの一部のそれぞれにワイヤーボンドで接続され、かつ、前記第１の半導体集積回路上の回路と配線で接続された、前記第１の半導体集積回路上の第１のワイヤーボンド用パッドと、
前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、互いに配線で接続された、前記第１の半導体集積回路上の一組の第２のワイヤーボンド用パッドと、
前記複数のリードの他の一部のそれぞれにワイヤーボンドで接続され、かつ、前記第１の半導体集積回路上で単独に配置された第３のワイヤーボンド用パッドとを備え、
前記第２のワイヤーボンド用パッドに接続された配線、ワイヤー及びリードが、前記第１のワイヤーボンド用パッドに接続された回路を囲むように配置され、
前記第３のワイヤーボンド用パッドに接続されたワイヤーが、前記第１のワイヤーボンド用パッドに接続されたワイヤー間に配置されたことを特徴とする半導体集積回路装置。 A first semiconductor integrated circuit;
A second semiconductor integrated circuit disposed on the same comb in proximity to the first semiconductor integrated circuit;
A plurality of leads disposed around the first and second semiconductor integrated circuits;
For the first wire bond on the first semiconductor integrated circuit, connected to each of a part of the plurality of leads by a wire bond, and connected to the circuit on the first semiconductor integrated circuit by a wiring Pad,
A set of second wire bond pads on the first semiconductor integrated circuit, connected to each other part of the plurality of leads by wire bonds and connected to each other by wiring; and
A third wire bonding pad connected to each of the other part of the plurality of leads by a wire bond and disposed independently on the first semiconductor integrated circuit,
The wiring, wires, and leads connected to the second wire bond pad are arranged so as to surround the circuit connected to the first wire bond pad,
A semiconductor integrated circuit device , wherein a wire connected to the third wire bond pad is disposed between wires connected to the first wire bond pad .
JP14564898A 1998-05-27 1998-05-27 Semiconductor integrated circuit and semiconductor integrated circuit device Expired - Fee Related JP3646970B2 (en)

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