JPH01145842A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01145842A JPH01145842A JP30520987A JP30520987A JPH01145842A JP H01145842 A JPH01145842 A JP H01145842A JP 30520987 A JP30520987 A JP 30520987A JP 30520987 A JP30520987 A JP 30520987A JP H01145842 A JPH01145842 A JP H01145842A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- power
- power supply
- pins
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にチップへの電源供給の
均一化を企っなパッケージを備えている半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a package designed to uniformize power supply to chips.
従来の半導体装置は、電源ピンとして使用される外部リ
ードの先端とチップとをボンディング線で接続している
ので、チップ上の電源電圧レベルを安定するには、複数
のピンを使用することが行なわれている。In conventional semiconductor devices, bonding wires are used to connect the tips of external leads used as power supply pins to the chip, so in order to stabilize the power supply voltage level on the chip, it is necessary to use multiple pins. It is.
上述した従来の半導体装置では、電源ピン１本でＬＳＩ
チップの特定の点にしか電源を供給する事ができないな
め、チップ上の電源電圧レベルを安定させるために複数
ケ所に電源が必要である場合、近くにある外部リードに
ボンディングし、信号ピンを電源として使用しなければ
ならない−ｊｊｔＲ造となっているのて、電源電圧レベ
ルの安定化のためチップ上に設定された電源の端の数だ
け信号ピンの数が減少してしまうという欠点がある。In the conventional semiconductor device mentioned above, LSI can be connected with one power pin.
Since power can only be supplied to specific points on the chip, if you need power at multiple locations to stabilize the supply voltage level on the chip, bond the signal pins to nearby external leads and connect the signal pins to the power source. However, the disadvantage is that the number of signal pins is reduced by the number of power supply terminals set on the chip to stabilize the power supply voltage level.
本発明の半導体装置は、チップをマウントする搭載部と
、前記搭載部の周囲に配置され所定の外部リードに接続
された電源導体を有するパッケージを備えているという
ものである。A semiconductor device of the present invention includes a mounting section for mounting a chip, and a package having a power supply conductor arranged around the mounting section and connected to a predetermined external lead.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ＞は本発明の第１の実施例を一部破断して示
す平面図、第１図（ｂ）は第１図（ａ＞のｘ−ｘ’線断
面図である。FIG. 1(a) is a partially cutaway plan view of a first embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line xx' in FIG. 1(a).
この実施例は、チップ１をマウントする搭載部（アイラ
ンド２として図示）と、アイランド２の周囲に配置され
特定の外部リードである電源ピン５と一体の電源導体４
を有する樹脂モールドパッケージを備えているというも
のである。This embodiment includes a mounting part (illustrated as an island 2) on which a chip 1 is mounted, and a power supply conductor 4 arranged around the island 2 and integrated with a power supply pin 5 which is a specific external lead.
It is equipped with a resin mold package that has a
電源導体４が、アイランド２をほぼ包囲して配置されて
いるので、この電源導体４とチップ１との接続はボンデ
ィング線３により複数個所で行うことができ；チップ上
の電源電圧レベルの安定化が、−本の外部リードを使用
するだけで達成できる。Since the power supply conductor 4 is arranged almost surrounding the island 2, the connection between the power supply conductor 4 and the chip 1 can be made at multiple points by the bonding wire 3; the power supply voltage level on the chip is stabilized. can be achieved simply by using an external lead.
第２図は本発明の第２の実施例の主要部を示す平面模式
図である。FIG. 2 is a schematic plan view showing the main parts of a second embodiment of the present invention.
この実施例は、電源ピン５−１．５−２のそれぞれと一
体の電源導体４−１．４−２がアイランド２の周囲に２
重に配置されているので、単一電源半導体装置の一層の
電源電圧レベルの安定化、もしくは、２電源半導体装置
の各電源電圧レベルの安定化が可能となる利点がある。This embodiment has two power conductors 4-1.4-2 integral with each of the power pins 5-1.5-2 around the island 2.
Since they are arranged in layers, there is an advantage that the power supply voltage level of a single power supply semiconductor device can be further stabilized, or each power supply voltage level of a dual power supply semiconductor device can be stabilized.
以上説明したように本発明は、電源導体をチップ搭載部
の周囲に配置する事により、信号ピンを電源ピンに流用
しなくてもチップ上と電源電圧の安定化を行うことがで
きるので半導体装置のピンの有効活用が可能となる効果
がある。As explained above, in the present invention, by arranging the power conductor around the chip mounting area, it is possible to stabilize the power supply voltage on the chip and the power supply voltage without using signal pins as power supply pins. This has the effect of making it possible to make effective use of the pins.
第１図（ａ）は本発明の第１の実施例を一部破断して示
す平面図、第１図（ｂ）は第１図（ａ）のｘ−ｘ’線断
面図、第２図は第２の実施例の主要部を示す平面模式図
である。
１・・・チップ、２・・・アイランド、３・・・ボンデ
ィング線、４．４−１．４−２・・・電源導体、５゜５
−１．５−２・・・電源ピン、６・・・外部リード、７
・・・樹脂モールド。FIG. 1(a) is a partially cutaway plan view of the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line xx' of FIG. 1(a), and FIG. FIG. 2 is a schematic plan view showing the main parts of the second embodiment. 1... Chip, 2... Island, 3... Bonding wire, 4.4-1.4-2... Power supply conductor, 5゜5
-1.5-2...Power pin, 6...External lead, 7
...Resin mold.
Claims (1)
配置され所定の外部リードに接続された電源導体を有す
るパッケージを備えていることを特徴とする半導体装置
。1. A semiconductor device comprising: a mounting part for mounting a chip; and a package having a power supply conductor arranged around the mounting part and connected to a predetermined external lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30520987A JPH01145842A (en) | 1987-12-01 | 1987-12-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30520987A JPH01145842A (en) | 1987-12-01 | 1987-12-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01145842A true JPH01145842A (en) | 1989-06-07 |
Family
ID=17942366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30520987A Pending JPH01145842A (en) | 1987-12-01 | 1987-12-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01145842A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0620593A1 (en) * | 1993-04-16 | 1994-10-19 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package |
| US5592020A (en) * | 1993-04-16 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package having leads with alternating offset projections |
| JP2008153576A (en) * | 2006-12-20 | 2008-07-03 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
-
1987
- 1987-12-01 JP JP30520987A patent/JPH01145842A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0620593A1 (en) * | 1993-04-16 | 1994-10-19 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package |
| US5592020A (en) * | 1993-04-16 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package having leads with alternating offset projections |
| US5801433A (en) * | 1993-04-16 | 1998-09-01 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package |
| JP2008153576A (en) * | 2006-12-20 | 2008-07-03 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
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