JPH0621329A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH0621329A JPH0621329A JP4176339A JP17633992A JPH0621329A JP H0621329 A JPH0621329 A JP H0621329A JP 4176339 A JP4176339 A JP 4176339A JP 17633992 A JP17633992 A JP 17633992A JP H0621329 A JPH0621329 A JP H0621329A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- resin
- sides
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置は、図３に
示すように、アイランド６に固着した半導体素子２とリ
ード５の一端とを導線７によって接続し、リード５の他
端側が外部に導出され樹脂１によって封止された構造を
有している。図４に示すように、半導体素子２をバンプ
４によって配線を施したフィルム８に接続し、配線を施
したフィルム８とリード５とをバンプ４によって接続し
た後樹脂１により封止した樹脂封止型半導体装置も提案
されている。2. Description of the Related Art In a conventional resin-sealed semiconductor device, as shown in FIG. 3, a semiconductor element 2 fixed to an island 6 and one end of a lead 5 are connected by a conductor wire 7, and the other end side of the lead 5 is external. And has a structure sealed with resin 1. As shown in FIG. 4, the semiconductor element 2 is connected to the film 8 which is wired by the bumps 4, the film 8 which is wired and the leads 5 are connected by the bumps 4, and then is sealed by the resin 1. Type semiconductor devices have also been proposed.
【０００３】[0003]
【発明が解決しようとする課題】前述した従来の樹脂封
止型半導体装置ではアイランドに半導体素子を固着し導
線によりリードと接続する場合、１つの樹脂封止型半導
体装置に１つの半導体素子しか封止することができな
い。また、配線をフィルムの片面のみに施し半導体素子
を接続した場合、フィルムの片面にしか配線がないため
にリードと接続するとリードの両面でそれぞれ１枚ずつ
計２枚の半導体素子しか封止することができないために
それ以上集積度を上げられないという問題点があった。In the above-mentioned conventional resin-sealed semiconductor device, when a semiconductor element is fixed to an island and connected to a lead by a conductive wire, only one semiconductor element is sealed in one resin-sealed semiconductor device. I can't stop. Also, when wiring is provided on only one side of the film and the semiconductor element is connected, since there is wiring only on one side of the film, when connecting to the lead, only one semiconductor element should be sealed on each side of the lead for a total of two semiconductor elements. However, there was a problem that the degree of integration could not be further increased because it could not be done.
【０００４】本発明の目的は、集積度の高い樹脂封止型
半導体装置を提供することにある。An object of the present invention is to provide a resin-sealed semiconductor device having a high degree of integration.
【０００５】[0005]
【課題を解決するための手段】本発明は、半導体素子を
内蔵する樹脂封止型半導体装置において、両面に配線を
施したフィルムの前記配線上にバンプを形成し前記フィ
ルムの両面に前記半導体素子を搭載し複数の半導体素子
を樹脂封止する。According to the present invention, in a resin-sealed semiconductor device having a semiconductor element built-in, bumps are formed on the wiring of a film having wiring on both sides thereof, and the semiconductor element is formed on both sides of the film. And a plurality of semiconductor elements are resin-sealed.
【０００６】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００７】図１は本発明の第１の実施例の断面図であ
る。FIG. 1 is a sectional view of a first embodiment of the present invention.
【０００８】第１の実施例は、図１に示すように、両面
に配線を施したフィルム３にバンプ４を用いて半導体素
子２を両面に接線し、半導体素子２を接線した両面に配
線を施したフィルム３を２つバンプ４を用いてリード５
の両面から接続しているため、４つの半導体素子を１つ
の樹脂封入型半導体装置の中に封止することができる。In the first embodiment, as shown in FIG. 1, the semiconductor element 2 is tangentially connected to both sides by using the bumps 4 on the film 3 having wirings on both sides, and the wiring is provided on both sides tangentially to the semiconductor element 2. Lead 5 using two bumps 4 of the applied film 3
Since they are connected from both sides, four semiconductor elements can be sealed in one resin-encapsulated semiconductor device.
【０００９】このような構造にすることにより集積度が
向上し、メモリ半導体素子の場合、メモリ容量は従来の
構造の樹脂封止型半導体装置に比べて２〜４倍にでき
る。With such a structure, the degree of integration is improved, and in the case of the memory semiconductor element, the memory capacity can be made 2 to 4 times as large as that of the resin-sealed semiconductor device having the conventional structure.
【００１０】図２は本発明の第２の実施例の断面図であ
る。FIG. 2 is a sectional view of the second embodiment of the present invention.
【００１１】第２の実施例は、図２に示すように、両面
に配線を施したフィルム３間とリード５の接続にバンプ
４を用いる。In the second embodiment, as shown in FIG. 2, bumps 4 are used to connect the leads 5 with the films 3 having wiring on both sides.
【００１２】図１に示す第１の実施例と同様に、最初の
両面に配線を施したフィルム３とリード５の接続をバン
プ４を用いて行なった後に、接続後の両面に配線を施し
たフィルム３の配線上に再びバンプ４を形成し、もう一
層の半導体素子２を接続した両面に配線を施したフィル
ム３とリード５との接続を行なう。Similar to the first embodiment shown in FIG. 1, the film 3 and the lead 5 having wiring on both sides at the beginning are connected using the bumps 4, and then the wiring is provided on both sides after the connection. The bumps 4 are formed again on the wiring of the film 3, and the film 3 having wiring on both sides to which the semiconductor element 2 of the other layer is connected and the lead 5 are connected.
【００１３】このような構造にすることにより集積度が
向上し、メモリ容量は従来の構造の樹脂封止型半導体装
置に比べ４〜８倍にできる。With such a structure, the degree of integration is improved, and the memory capacity can be 4 to 8 times as large as that of the resin-sealed semiconductor device having the conventional structure.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、両面に配
線を施したフィルムの両面にバンプによって半導体素子
を接続したフイルムを用い、また、フィルムとリードと
をバンプを介して接続することにより、１つの樹脂封止
型半導体装置の中に複数の半導体素子を持つことができ
集積度が向上し、メモリ半導体素子を８つ封止した場
合、メモリ容量を４〜８倍大きくできるという効果を有
する。As described above, the present invention uses a film in which semiconductor elements are connected by bumps on both sides of a film having wiring on both sides, and by connecting the film and leads through bumps. It is possible to have a plurality of semiconductor elements in one resin-encapsulated semiconductor device, the degree of integration is improved, and when eight memory semiconductor elements are encapsulated, the memory capacity can be increased 4 to 8 times. Have.
【図１】本発明の第１の実施例の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of the present invention.
【図２】本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図３】従来の樹脂封止型半導体装置の一例の断面図で
ある。FIG. 3 is a cross-sectional view of an example of a conventional resin-sealed semiconductor device.
【図４】従来の樹脂封止型半導体装置の他の例の断面図
である。FIG. 4 is a sectional view of another example of a conventional resin-sealed semiconductor device.
１ 樹脂 ２ 半導体素子 ３ 両面に配線を施したフィルム ４ バンプ ５ リード ６ アイランド ７ 導線 ８ 配線を施したフィルム 1 Resin 2 Semiconductor element 3 Film with wiring on both sides 4 Bump 5 Lead 6 Island 7 Conductive wire 8 Film with wiring
Claims (1)
装置において、両面に配線を施したフィルムの前記配線
上にバンプを形成し前記フィルムの両面に前記半導体素
子を搭載し複数の半導体素子を樹脂封止したことを特徴
とする樹脂封止型半導体装置。1. A resin-encapsulated semiconductor device containing a semiconductor element, wherein bumps are formed on the wiring of a film having wiring on both sides, and the semiconductor element is mounted on both sides of the film to form a plurality of semiconductor elements. A resin-sealed semiconductor device, which is resin-sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4176339A JPH0621329A (en) | 1992-07-03 | 1992-07-03 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4176339A JPH0621329A (en) | 1992-07-03 | 1992-07-03 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0621329A true JPH0621329A (en) | 1994-01-28 |
Family
ID=16011858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4176339A Withdrawn JPH0621329A (en) | 1992-07-03 | 1992-07-03 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621329A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069025A (en) * | 1994-11-15 | 2000-05-30 | Lg Semicon Co., Ltd. | Method for packaging a semiconductor device |
| KR20020020088A (en) * | 2000-09-07 | 2002-03-14 | 마이클 디. 오브라이언 | semiconductor package and its manufacturing method |
| US6573608B2 (en) | 2001-05-02 | 2003-06-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with layered semiconductor chips |
-
1992
- 1992-07-03 JP JP4176339A patent/JPH0621329A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069025A (en) * | 1994-11-15 | 2000-05-30 | Lg Semicon Co., Ltd. | Method for packaging a semiconductor device |
| KR20020020088A (en) * | 2000-09-07 | 2002-03-14 | 마이클 디. 오브라이언 | semiconductor package and its manufacturing method |
| US6573608B2 (en) | 2001-05-02 | 2003-06-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with layered semiconductor chips |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |