JPH06177322A - Memory element - Google Patents
Memory elementInfo
- Publication number
- JPH06177322A JPH06177322A JP4325269A JP32526992A JPH06177322A JP H06177322 A JPH06177322 A JP H06177322A JP 4325269 A JP4325269 A JP 4325269A JP 32526992 A JP32526992 A JP 32526992A JP H06177322 A JPH06177322 A JP H06177322A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrodes
- substrate
- memory element
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はコンピュータなどの電気
機器の基板に搭載されるメモリ素子に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device mounted on a substrate of electric equipment such as a computer.
【０００２】[0002]
【従来の技術】メモリ素子を構成するチップはウェハか
ら切り出されたものであり、その一方の面に回路パター
ンが形成されており、この回路パターンの電極を基板の
電極に接続して基板に搭載される。2. Description of the Related Art A chip that constitutes a memory device is cut out from a wafer, and a circuit pattern is formed on one surface of the chip. The electrodes of this circuit pattern are connected to the electrodes of the substrate and mounted on the substrate. To be done.
【０００３】[0003]
【発明が解決しようとする課題】しかしながらチップは
一方の面にのみ回路パターンが形成されており、他方の
面には回路パターンは形成されないため、記憶容量の増
大には限界があった。However, since the circuit pattern is formed only on one surface of the chip and the circuit pattern is not formed on the other surface of the chip, there is a limit to increase the storage capacity.
【０００４】したがって本発明は、記憶容量を増大でき
るメモリ素子を提供することを目的とする。Therefore, it is an object of the present invention to provide a memory device capable of increasing the storage capacity.
【０００５】[0005]
【課題を解決するための手段】このために本発明は、表
面に回路パターンが形成された第１のチップと第２のチ
ップの裏面同士を貼り合わせて一体化してメモリ素子を
構成したものである。To this end, the present invention provides a memory device in which the back surfaces of a first chip and a second chip having a circuit pattern formed on the front surface are bonded together and integrated. is there.
【０００６】[0006]
【作用】上記構成によれば、第１のチップと第２とチッ
プの回路パターンが使用できるのでメモリの記憶容量を
実質的に倍増できる。According to the above structure, since the circuit patterns of the first chip, the second chip and the chip can be used, the storage capacity of the memory can be substantially doubled.
【０００７】[0007]
【実施例】次に、図面を参照しながら本発明の実施例を
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００８】図１は本発明に係るメモリ素子の斜視図、
図２は断面図である。このメモリ素子１は、第１のチッ
プ２と第２のチップ３を一体化して形成されている。第
１のチップ２と第２のチップ３の表面には回路パターン
が形成されており、回路パターンが形成されていない裏
面同士をボンド４で貼り合わせて一体化されている。第
１のチップ２の回路パターンが形成された表面の周縁部
には電極であるパッド５が形成されており、また第２の
チップの回路パターンが形成された表面の周縁部にはバ
ンプ（突出電極）６が突設されている。FIG. 1 is a perspective view of a memory device according to the present invention,
FIG. 2 is a sectional view. The memory element 1 is formed by integrating a first chip 2 and a second chip 3. Circuit patterns are formed on the front surfaces of the first chip 2 and the second chip 3, and the back surfaces on which the circuit patterns are not formed are bonded together by a bond 4 to be integrated. Pads 5 as electrodes are formed on the peripheral portion of the surface of the first chip 2 on which the circuit pattern is formed, and bumps (projections) are formed on the peripheral portion of the surface of the second chip on which the circuit pattern is formed. Electrodes) 6 are projected.
【０００９】このメモリ素子１が搭載される基板７の表
面には回路パターンの電極８が形成されている。第１の
チップ２のパッド５と基板７の電極８はワイヤ９により
接続されている。また第２のチップ３のバンプ６は基板
７の電極８にボンディングされている。したがってバン
プ６とワイヤ９は同一の電極８に接続されており、基板
７の電極８は第１のチップ２のパッド５と第２のチップ
３の突出電極６が接続される共通電極となっている。An electrode 8 having a circuit pattern is formed on the surface of the substrate 7 on which the memory element 1 is mounted. The pads 5 of the first chip 2 and the electrodes 8 of the substrate 7 are connected by wires 9. The bumps 6 of the second chip 3 are bonded to the electrodes 8 of the substrate 7. Therefore, the bump 6 and the wire 9 are connected to the same electrode 8, and the electrode 8 of the substrate 7 serves as a common electrode to which the pad 5 of the first chip 2 and the protruding electrode 6 of the second chip 3 are connected. There is.
【００１０】基板７の表面には切替用電極１０，２０が
形成されている。切替用電極１０はワイヤ９ａにより第
１のチップ２のパッド５に接続されており、切替用電極
２０はバンプ６を介して第２のチップ３のパットに接続
されている。なお基板としては、プリント基板やリード
フレームなどが適用できる。図２に示すように、基板７
に搭載されたメモリ素子１は樹脂１１で被覆される。こ
の樹脂１１は第１のチップ２の表面の回路パターンやワ
イヤ９を保護するものであり、エポキシ樹脂などが適用
される。Switching electrodes 10 and 20 are formed on the surface of the substrate 7. The switching electrode 10 is connected to the pad 5 of the first chip 2 by the wire 9 a, and the switching electrode 20 is connected to the pad of the second chip 3 via the bump 6. A printed circuit board, a lead frame, or the like can be applied as the substrate. As shown in FIG.
The memory element 1 mounted on the substrate is covered with the resin 11. The resin 11 protects the circuit pattern on the surface of the first chip 2 and the wires 9, and epoxy resin or the like is applied.
【００１１】図３はメモリ素子１が配線される電気回路
のブロック図である。第１のチップ２と第２のチップ３
は切替部１２と制御部１３に接続されている。図中、８
ａは図１に示す基板７の多数の電極８で構成されるバス
である。FIG. 3 is a block diagram of an electric circuit to which the memory element 1 is wired. First chip 2 and second chip 3
Is connected to the switching unit 12 and the control unit 13. 8 in the figure
a is a bus composed of a large number of electrodes 8 on the substrate 7 shown in FIG.
【００１２】次に図３を参照しながらこのメモリ素子１
の駆動方法を説明する。制御部１３から「１」の信号が
出力されると、切替部１２は第１のチップ２に「１」を
出力し、第２のチップ３には「０」を出力する。第１の
チップ２及び第２のチップ３は「１」が入力されると駆
動するようになっており、したがってこの場合、第１の
チップ２だけが駆動する。次に制御部１３から「０」の
信号が出力されると、切替部１２は第１のチップに
「０」を出力し、また第２のチップ３には「１」を出力
し、第２のチップ３だけが駆動する。図３において、配
線の右側に示す「１」「０」は第１のチップ２を駆動す
る場合の信号を示しており、また配線の左側に示す
「１」「０」は第２のチップ３を駆動する場合の信号を
示している。Next, referring to FIG. 3, the memory device 1 will be described.
The driving method of will be described. When the control unit 13 outputs the signal “1”, the switching unit 12 outputs “1” to the first chip 2 and outputs “0” to the second chip 3. The first chip 2 and the second chip 3 are designed to be driven when "1" is input, and therefore, in this case, only the first chip 2 is driven. Next, when the control unit 13 outputs a signal of “0”, the switching unit 12 outputs “0” to the first chip, outputs “1” to the second chip 3, and outputs the second signal. Only chip 3 of is driven. In FIG. 3, “1” and “0” shown on the right side of the wiring show signals when driving the first chip 2, and “1” and “0” shown on the left side of the wiring show the second chip 3 7 shows a signal for driving.
【００１３】このように第１のチップ２と第２のチップ
３は、基板７の電極８を共通電極として、切替部１２で
信号を切替えながら、２つのチップ２、３を選択的に駆
動するものであり、２つのチップ２、３の回路パターン
を使用できるので、同一平面積のメモリ素子で記憶容量
を実質的に倍増できる。As described above, the first chip 2 and the second chip 3 use the electrode 8 of the substrate 7 as a common electrode to selectively drive the two chips 2 and 3 while switching the signal by the switching unit 12. Since the circuit patterns of the two chips 2 and 3 can be used, the storage capacity can be substantially doubled with the memory elements having the same plane area.
【００１４】図４は本発明の他の実施例を示している。
このメモリ素子１４は、第１のチップ２と第２のチップ
３をモールド体１７でモールドしており、第２のチップ
３は副基板１５に搭載されている。第１のチップ２のパ
ッド５と副基板１５の電極はワイヤで接続されている。
またこの副基板１５からはリード１６が延出しており、
このリード１６が基板（図外）の電極上に搭載される。FIG. 4 shows another embodiment of the present invention.
In this memory element 14, the first chip 2 and the second chip 3 are molded with a molding body 17, and the second chip 3 is mounted on the sub-board 15. The pad 5 of the first chip 2 and the electrode of the sub-board 15 are connected by a wire.
The leads 16 extend from the sub-board 15,
The leads 16 are mounted on the electrodes of the substrate (not shown).
【００１５】[0015]
【発明の効果】以上説明したように本発明は、表面に回
路パターンが形成された第１のチップと第２のチップの
裏面同士を貼り合わせて一体化してメモリ素子を構成し
ているので、メモリ素子の記憶容量を実質的に倍増で
き、基板の高集積化が可能となる。As described above, according to the present invention, the back surface of the first chip and the back surface of the second chip having the circuit pattern formed on the front surface are bonded together to form a memory device. The storage capacity of the memory element can be substantially doubled, and the substrate can be highly integrated.
【図１】本発明の一実施例のメモリ素子の斜視図FIG. 1 is a perspective view of a memory device according to an exemplary embodiment of the present invention.
【図２】本発明の一実施例のメモリ素子の断面図FIG. 2 is a sectional view of a memory device according to an embodiment of the present invention.
【図３】本発明の一実施例の電気回路のブロック図FIG. 3 is a block diagram of an electric circuit according to an embodiment of the present invention.
【図４】本発明の他の実施例のメモリ素子の断面図FIG. 4 is a sectional view of a memory device according to another embodiment of the present invention.
【符号の説明】 １ メモリ素子 ２ 第１のチップ ３ 第２のチップ ５ パッド ６ バンプ ７ 基板 ８ 電極 ９ ワイヤ １４ メモリ素子[Description of Reference Signs] 1 memory element 2 first chip 3 second chip 5 pad 6 bump 7 substrate 8 electrode 9 wire 14 memory element
Claims (2)
ップと第２のチップの裏面同士を貼り合わせて一体化し
たことを特徴とするメモリ素子。1. A memory device comprising: a first chip having a circuit pattern formed on its front surface and a back surface of a second chip bonded together to be integrated.
電極にワイヤで接続されるパッドを形成し、前記第２の
チップの表面に前記基板の電極を前記第１のチップとの
共通電極としてこの電極にボンディングされるバンプを
突設したことを特徴とする請求項１記載のメモリ素子。2. A pad which is connected to an electrode of a substrate by a wire is formed on a peripheral portion of a surface of the first chip, and an electrode of the substrate is formed on the surface of the second chip together with the first chip. 2. The memory device according to claim 1, wherein a bump bonded to this electrode is provided as a common electrode in a protruding manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4325269A JPH06177322A (en) | 1992-12-04 | 1992-12-04 | Memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4325269A JPH06177322A (en) | 1992-12-04 | 1992-12-04 | Memory element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06177322A true JPH06177322A (en) | 1994-06-24 |
Family
ID=18174929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4325269A Pending JPH06177322A (en) | 1992-12-04 | 1992-12-04 | Memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06177322A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996017505A1 (en) * | 1994-12-01 | 1996-06-06 | Motorola Inc. | Method, flip-chip module, and communicator for providing three-dimensional package |
| US5793108A (en) * | 1995-05-30 | 1998-08-11 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit having a plurality of semiconductor chips |
| US6452279B2 (en) | 2000-07-14 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2005286126A (en) * | 2004-03-30 | 2005-10-13 | Renesas Technology Corp | Semiconductor device |
| JP2015070036A (en) * | 2013-09-27 | 2015-04-13 | ローム株式会社 | Semiconductor device and electronic apparatus |
-
1992
- 1992-12-04 JP JP4325269A patent/JPH06177322A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996017505A1 (en) * | 1994-12-01 | 1996-06-06 | Motorola Inc. | Method, flip-chip module, and communicator for providing three-dimensional package |
| US5793108A (en) * | 1995-05-30 | 1998-08-11 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit having a plurality of semiconductor chips |
| US6452279B2 (en) | 2000-07-14 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2005286126A (en) * | 2004-03-30 | 2005-10-13 | Renesas Technology Corp | Semiconductor device |
| JP4538830B2 (en) * | 2004-03-30 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2015070036A (en) * | 2013-09-27 | 2015-04-13 | ローム株式会社 | Semiconductor device and electronic apparatus |
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