KR940008643Y1 - Lsi package - Google Patents

Lsi package Download PDF

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Publication number
KR940008643Y1
KR940008643Y1 KR2019910024568U KR910024568U KR940008643Y1 KR 940008643 Y1 KR940008643 Y1 KR 940008643Y1 KR 2019910024568 U KR2019910024568 U KR 2019910024568U KR 910024568 U KR910024568 U KR 910024568U KR 940008643 Y1 KR940008643 Y1 KR 940008643Y1
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KR
South Korea
Prior art keywords
chip
conductive pattern
pcb
package
connection
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KR2019910024568U
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Korean (ko)
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KR930016280U (en
Inventor
송웅호
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삼성전자 주식회사
김광호
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Priority to KR2019910024568U priority Critical patent/KR940008643Y1/en
Publication of KR930016280U publication Critical patent/KR930016280U/en
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Publication of KR940008643Y1 publication Critical patent/KR940008643Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

고집적 패키지Highly Integrated Package

제1도는 본 고안에 따른 일실시예를 나타내는 도면.1 is a view showing an embodiment according to the present invention.

제2도는 본 고안에 따른 다른 일실시예를 나타내는 도면.2 is a view showing another embodiment according to the present invention.

제3도는 제1도에 대한 본 고안의 상세배치도.3 is a detailed layout of the present invention with respect to FIG.

제4도는 제3도에 의한 완성된 본 고안의 상세배치도.4 is a detailed arrangement of the present invention completed by FIG.

제5도는 제2도에 대한 본 고안의 상세배치도.5 is a detailed layout of the present invention with respect to FIG.

본 고안은 전자소자의 패키지에 관한 것으로, 특히 칩과 그의 응용회로 또는 칩과 칩간의 연결을 양면 PCB(Printed circuit board; 이하 PCB라 칭함)를 이용하여 집적화시킨 고집적 패키지에 관한 것이다.The present invention relates to a package of an electronic device, and more particularly, to a highly integrated package in which a chip and its application circuit or a chip-to-chip connection are integrated by using a double-sided printed circuit board (PCB).

일반적으로 칩을 패키지화하는 경우는 주로 2가지 방법에 의존한다. 그 첫째가 리이드 프레임위의 패드에 칩을 올려놓고 리이드 프레임과의 와이어본딩(Wire bonding)을 통하여 패키지를 구현하는 것이고, 둘째가 탭(TAB; Tape automatic bonding)등의 필름을 이용하는 것이다.In general, packaging chips depends mainly on two methods. The first is to place the chip on the pad on the lead frame and implement the package through wire bonding with the lead frame, and the second is to use a film such as tape automatic bonding (TAB).

그러나 이들 모두 패키지의 일면만을 사용하므로 나머지 한면에 대한 면적의 손실을 가져오고, 또 응용회로까지 포함하는 패키지를 이룰 수가 없다.However, since both of them use only one side of the package, the loss of area on the other side is lost, and the package including the application circuit cannot be achieved.

따라서 본 고안은 상기와 같은 사정을 감안하여 제안된 것으로, 칩과 그의 응용회로에 이용되는 소자들을 양면 PCB에 모두 집적시키므로써 종래의 같은 크기에 패키지보다 집적도를 휠씬 향상시키고, 면적의 효율화를 이룩하며 집적의 한계를 넓힌 고집적 패키지를 제공하는데 그 목적이 있다.Therefore, the present invention was proposed in view of the above circumstances, and by integrating both the chip and the devices used in the application circuit on the double-sided PCB, the integration degree is much improved than the package of the same size as the conventional, and the efficiency of the area is achieved. The aim is to provide a highly integrated package that extends the limits of integration.

상기와 같은 목적을 달성하기 위한 본 고안은 양면 PCB(3)의 전면(8)중앙부분에 접착제로 본딩된 칩(1)이 놓여져 있으며 그 주변에 칩과의 접속을 위한 전도성 패턴(5)들이 형성되어 있고 상기 전도성 패턴에는 전면(8)과 후면(9)의 전기적접속을 위한 핀홀(Pinhole, 6)이 만들어져 있으며 외부와의 접속을 위한 다수개의 외부접속핀(10, 20, 30, 40, 50, 60)이 전도성 패턴 끝부분을 솔더링(Soldering)되어 있고 또 PCB의 후면(9)에는 전면의 칩과 함께 회로를 구성하는 응용회로 소자(오실레이터, 저항, 커패시터)들이 전도성 패턴에 의해 연결된 구조를 갖추고 있는 것을 특징으로 한다.In order to achieve the above object, the present invention has a chip (1) bonded with an adhesive on a central portion of the front surface (8) of a double-sided PCB (3), and the conductive patterns (5) for connection with the chip are disposed therein. And a pinhole 6 for electrical connection between the front side 8 and the rear side 9 is formed in the conductive pattern, and a plurality of external connection pins 10, 20, 30, 40, 50, 60 are soldered at the end of the conductive pattern, and the back circuit 9 of the PCB is connected to the application circuit elements (oscillators, resistors, capacitors) that make up the circuit together with the chip on the front by a conductive pattern. Characterized in having a.

이하 예시도면을 참조하여 본 고안을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 고안에 따른 일실시예를 나타내는 도면으로, 칩과 그에 대응되는 응용회로 소자들을 나타낸 개략도이며, 커패시터(C)가 와이어본딩용 패드(10')과 (20')에 접속되며, 오실레이터(OSC)는 패드(40')와 (50')에 그리고 저항(R)이 패드(30')과 (60')에 접속된 상태를 나타낸다.1 is a diagram showing an embodiment according to the present invention, a schematic diagram showing a chip and its corresponding application circuit elements, the capacitor (C) is connected to the wire bonding pad (10 ') and (20'), The oscillator OSC represents a state in which the pads 40 'and 50' and the resistor R are connected to the pads 30 'and 60'.

제3도는 제1도에 대한 본 고안의 상세배치도로써, 칩과 전도성 패턴이 와이어본딩된 상태를 나타내는 패키지 전면(a)과 그의 응용회로소자의 연결상태를 나타내는 패키지후면(b)이다.3 is a detailed layout view of the present invention with respect to FIG. 1, which is a front surface of a package showing a state in which a chip and a conductive pattern are wire-bonded and a rear surface of a package showing a connection state of an application circuit device thereof.

먼저 본 고안을 개략적으로 설명하면, 양면PCB(3)의 전면(8)에 전도성패턴(5)을 설계하고, 전후면의 연결을 위하여 필요한 패턴에 핀홀(Pin hole, 6)을 만든다. 그리고 칩(1)을 PCB 전면에 접착제로 부착하여 전도성패턴(5)과 본딩와이어(Bonding wire, 4)로 전기적 연결을 하고 이어 후면(9)에 응용회로소자(오실레이터, 커패시터, 저항)를 납등으로 패턴에 부착연결시킨다.First, a schematic description of the present invention, the conductive pattern 5 is designed on the front surface 8 of the double-sided PCB (3), and a pin hole (6) is made in the pattern necessary for the front and rear surfaces. Then, the chip 1 is attached to the front surface of the PCB with an adhesive to electrically connect the conductive pattern 5 and the bonding wire 4, and then lead the application circuit elements (oscillators, capacitors, resistors) to the back side 9, etc. Attach to the pattern.

또 외부와의 전기적 연결을 위하여 다수개의 외부접속용 핀(10, 20, 30, 40, 50, 60)을 전도성패턴(5)과 납땜하여 연결시키고 소켓(Socket)에 맞도록 포밍(Forming)작업한다.In addition, a plurality of external connection pins (10, 20, 30, 40, 50, 60) are soldered to the conductive pattern (5) for electrical connection to the outside, and forming work to fit the socket (Socket) do.

이렇게하여 완성된 입체도가 제4도(a) (b)이며 이때 칩과 본딩와이어의 보호를 위해 몰딩수지(7)를 이용 전면을 감싸주는 것이 바람직하다.In this way, the completed three-dimensional view is 4 (a) and (b). At this time, it is preferable to wrap the entire surface using the molding resin 7 to protect the chip and the bonding wire.

제2도는 본 고안에 따른 다른 일실시예를 나타내는 도면으로 칩(A)과 칩(B)간의 연결상태를 나타낸 개략도이며, 칩(A)의 와이어본딩용 패드(10', 30', 40')가 칩(B)의 와이어본딩용 패드(10", 30", 40")각각 접속된 상태를 나타낸다.2 is a diagram showing another embodiment according to the present invention is a schematic diagram showing the connection state between the chip (A) and the chip (B), the wire bonding pads 10 ', 30', 40 'of the chip (A) ) Denotes a state in which the wire bonding pads 10 ", 30", and 40 "of the chip B are respectively connected.

제5도는 제2도에 대한 본 고안의 상세배치도로써, 칩(A)과 전도성 패턴이 와이어본딩된 상태를 나타내는 도면(a)과 칩(B)가 전도성 패턴과 와이어본딩된 상태를 나타내는 도면(b)이다.FIG. 5 is a detailed layout view of the present invention with respect to FIG. 2, which illustrates a state in which the chip A and the conductive pattern are wire bonded (a) and a state in which the chip B is the wire bonded with the conductive pattern ( b).

먼저 칩(A)이 양면PCB(3)의 전면(8)중앙에 접착되어 있고 전도성패턴(5)과 칩(1)이 본딩와이어(4)로 전기적 접속되어 있으며 후면의 칩(B)과의 전기적 접속을 위해 각 전도성 패턴에는 핀홀(Pin hoie, 6)이 형성되어 있으며 외부와의 전기적 접속을 위해 전도성 패턴의 끝에 다수개의 외부접속핀(10, 20, 30, 40, 50, 60)이 납땜되어 있다. 또 PCB의 후면(9)에는 다른 칩(B)이 전도성 패턴(5)과 본딩와이어(4)로 전기적 접속된 상태를 나타내며, 전면 칩(A)의 패드(10', 30', 40')와 후면 칩(B)의 패드(10'', 30", 40")가 전기적으로 연결된 상태를 나타낸다.First, the chip A is adhered to the center of the front surface 8 of the double-sided PCB 3, the conductive pattern 5 and the chip 1 are electrically connected to the bonding wires 4, and A pin hole 6 is formed in each conductive pattern for electrical connection, and a plurality of external connection pins 10, 20, 30, 40, 50, and 60 are soldered at the end of the conductive pattern for electrical connection with the outside. It is. In addition, another chip B is electrically connected to the conductive pattern 5 and the bonding wire 4 on the rear surface 9 of the PCB, and the pads 10 ', 30', 40 'of the front chip A are connected to each other. And pads 10 ″, 30 ″, 40 ″ of the rear chip B are electrically connected to each other.

이상에서 설명된 바와같이 본 고안에 의하면, 양면 PCB를 이용하여 집적화함으로 면적의 효율화를 이룩하고 집적도를 향상시킬수 있으며, 응용소자를 포함하여 복수의 칩까지도 하나의 패키지내에 집적화가 가능하므로 패키지의 한계를 넓히는 효과가 있다.As described above, according to the present invention, the integrated area using a double-sided PCB can achieve the efficiency of the area and improve the degree of integration, and it is possible to integrate a plurality of chips including an application device in one package, thereby limiting the package. It is effective to widen.

Claims (2)

양면 PCB(Printed circuit board)의 전면(8)에는 중앙부분에 접착제로 접착된 칩(1)과 상기 칩 주변에 칩과의 접속을 위해 형성된 전도성 패턴(5)과 상기 전도성 패턴에 전면(8)과 후면(9)의 전기적 접속을 위해 형성된 핀홀(Pin hole, 6)과 외부와의 접속을 위해 전도성 패턴에 솔더링(Soldering)된 다수개의 외부접속핀(10, 20, 30, 40, 50, 60)과 PCB(Printed circuit board)의 후면(9)에는 전면의 칩(1)과 함께 회로를 구성하는 응용회로소자들이 전도성 패턴(5)에 의해 연결된 구조를 갖고 있는 것을 특징으로 하는 고집적 패키지.The front surface 8 of the double-sided printed circuit board (PCB) has a chip (1) glued to the center portion and a conductive pattern (5) formed for connection with the chip around the chip and the front surface (8) Pin holes (6) formed for electrical connection to the rear and rear (9) and a plurality of external connection pins (Soldering) soldered to the conductive pattern for connection to the outside (10, 20, 30, 40, 50, 60) ) And a high density package having a structure in which application circuit elements constituting a circuit together with a chip (1) on the front side of the printed circuit board (PCB) are connected by a conductive pattern (5). 양면PCB(Printed circuit board)의 전면(8)과 후면(9) 중앙부분에는 각기 다른 종류의 칩(A, B)이 놓여져 있으며 상기 칩 주변에는 전도성패턴(5)이 칩과 본딩와이어(4)로 접속되어 있으며 상기 전도성 패턴에는 전면과 후면의 전기적인 접속을 위해 핀홀(Pin hole, 6)이 형성되어 있고, 외부와의 전기적 접속을 위해 다수개의 외부접속핀(10, 20, 30, 40, 50, 60)이 전도성패턴에 솔더링되어 있어 회로적으로는 칩(A)의 패드(10', 30', 40')가 칩(B)의 패드(10", 30", 40")에 각각 전기적 접속된 구조를 갖는 것을 특징으로 하는 고집적 패키지.Different types of chips (A, B) are placed at the center of the front side (8) and the rear side (9) of the double-sided printed circuit board (PCB), and the conductive pattern (5) is formed around the chip and the bonding wire (4). And a pin hole 6 is formed in the conductive pattern for electrical connection between the front and rear surfaces, and a plurality of external connection pins 10, 20, 30, 40, for electrical connection with the outside. 50 and 60 are soldered to the conductive pattern so that the pads 10 ', 30' and 40 'of the chip A are connected to the pads 10 ", 30" and 40 "of the chip B, respectively. A highly integrated package, characterized in that it has an electrically connected structure.
KR2019910024568U 1991-12-28 1991-12-28 Lsi package KR940008643Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019910024568U KR940008643Y1 (en) 1991-12-28 1991-12-28 Lsi package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910024568U KR940008643Y1 (en) 1991-12-28 1991-12-28 Lsi package

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KR930016280U KR930016280U (en) 1993-07-28
KR940008643Y1 true KR940008643Y1 (en) 1994-12-26

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KR100288071B1 (en) * 1998-03-10 2001-05-02 김춘호 Duplexer for portable communication terminal

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