JPS6147689A - Plug-in package - Google Patents
Plug-in packageInfo
- Publication number
- JPS6147689A JPS6147689A JP16894084A JP16894084A JPS6147689A JP S6147689 A JPS6147689 A JP S6147689A JP 16894084 A JP16894084 A JP 16894084A JP 16894084 A JP16894084 A JP 16894084A JP S6147689 A JPS6147689 A JP S6147689A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- plug
- package
- pads
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Packages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明はコンピュータなどの電子装置のプリント配線板
に使用するプラグインパッケージに関するもので、特九
電源とグランド間に発生するノイズを有効的に吸収する
ＩＣ搭載用のプラグインパッケージに関するものである
。[Detailed Description of the Invention] Industrial Application Field The present invention relates to a plug-in package used for printed wiring boards of electronic devices such as computers, which effectively absorbs noise generated between a special power supply and ground. This relates to a plug-in package for mounting an IC.
従来の技術
近年、コンピュータなどの電子装置はますます高性能、
高速度のものが要求されてきておシ、とれに使用される
電子回路も高集積化さ・れたＩＣテッグを搭載したプラ
グインパ・ッケージを高密度に実装するようになってい
る。このプラグインパッケージをプリント配線板に実装
して使用する場合、電源とグランド間に発生するノイズ
を吸収することが必要である◇
従来、この種のＩＣｆ、グを搭載するプラグインパッケ
ージは、第３図に示すようにセラミック基ｇ１１の上面
にＩＣｆ、プｌＯのみを搭載する構造を有していた。そ
のために、このプラグインパッケージをプリント配線板
に実装してノイズ吸収を行なうために、第４図及び第５
図に示すような方法をとっていた。すなわち、プリント
配線板１６上で各プラグインパッケージの周Ｈにそれぞ
れ単体のコンデンサ１５を実装して実現していた。Conventional technology In recent years, electronic devices such as computers have become more and more sophisticated.
As high-speed devices are required, the electronic circuits used in the devices are also becoming densely packed in plug-in packages equipped with highly integrated IC chips. When using this plug-in package mounted on a printed wiring board, it is necessary to absorb noise generated between the power supply and ground. Conventionally, plug-in packages equipped with this type of ICf, As shown in FIG. 3, it had a structure in which only ICf and PIO were mounted on the upper surface of the ceramic base g11. Therefore, in order to mount this plug-in package on a printed wiring board and absorb noise,
The method shown in the figure was used. That is, this was realized by mounting a single capacitor 15 on the circumference H of each plug-in package on the printed wiring board 16.
このような実装方法では、プリント配線板１６における
実装密度が高められないという欠点があシ、さらに、第
３図に示すような構造のプラグインパッケージでは、放
熱用のヒートシンクが取シ付けられないため、消費電力
の大きいＩＣチップの搭載に対しては、おのずと限界が
あるという欠点があった。This mounting method has the disadvantage that the mounting density on the printed wiring board 16 cannot be increased, and furthermore, in a plug-in package having the structure shown in FIG. 3, a heat sink for heat dissipation cannot be attached. Therefore, there is a drawback that there is a natural limit to the mounting of IC chips with large power consumption.
発明が解決しようとする問題点
本発明の目的は、上記の欠点すなわち、プリント配線板
における実装密度が高められないという問題点と、放熱
用のヒートシンクの取付けが困難であるという問題点を
解決したプラグインパッケージを提供することにある０
問題点を解決するための手段
本発明は上述の問題点を解決するために、セラミック基
板の下面に形成された１個のＩＣｆ、グ搭載用の複数個
のボンディングパッドと、ボンディングエリアに隣接し
て設けられた少なくとも２個のコンデンサパッドと、こ
れに搭載された少なくとも１個のコンデンサテップと、
前記複数個のボンディングパッドおよびコンデンサパッ
ドのエリアの外側のセラミック基板の下面に植立された
複数個のリードピンと、前記複数個のボンディングパッ
ドと前記複数個のリードピンとをそれぞれ接続する接続
配線およびグイアホール配線とからなり、前記コンデン
サパッドのおのおのが前記接続配線の電源まだはグラン
ドラインに接続される構成を採用するものである０
作用
本発明は上述のように構成したので、プラグインパッケ
ージ内でノイズの吸収が行われ、プリント配線板へ別に
コンデンサを実装する必要がなく。Problems to be Solved by the Invention The purpose of the present invention is to solve the above-mentioned drawbacks, namely, the problem that the mounting density on a printed wiring board cannot be increased and the problem that it is difficult to attach a heat sink for heat dissipation. Means for Solving the Problems The present invention aims to solve the above-mentioned problems by providing a plug-in package. a bonding pad, at least two capacitor pads provided adjacent to the bonding area, and at least one capacitor tip mounted thereon;
A plurality of lead pins planted on the lower surface of the ceramic substrate outside the areas of the plurality of bonding pads and capacitor pads, and connection wiring and guia holes that respectively connect the plurality of bonding pads and the plurality of lead pins. Each of the capacitor pads is connected to the power supply line or the ground line of the connection wiring. absorption, eliminating the need to mount a separate capacitor on the printed wiring board.
またプラグインパッケージの基板が熱良伝導体のセラミ
ック板であるため、その上面にヒートシンクの取シ付け
が容易になる作用がある。Furthermore, since the board of the plug-in package is a ceramic plate that is a good thermal conductor, it is easy to attach a heat sink to the top surface of the board.
実施例 次に本発明の実施例について図面を参照して説明する。Example Next, embodiments of the present invention will be described with reference to the drawings.
本発明の一実施例を断面図で示す第１図を参照すると１
本発明に係るプラグインパッケージは、セラミック基板
ｌと、複数個のボンディングパ。Referring to FIG. 1, which shows a cross-sectional view of one embodiment of the present invention,
A plug-in package according to the present invention includes a ceramic substrate l and a plurality of bonding pads.
ド２と、接続配線３と、複数個のリードピン４と、グイ
アホール配線５と、両端に電極７をもつコンデンサテッ
プ６と、コンデンサパッド８と、コンデンサ接着剤９と
から構成されている。The capacitor pad 2 includes a lead 2, a connecting wire 3, a plurality of lead pins 4, a guia hole wire 5, a capacitor tip 6 having electrodes 7 at both ends, a capacitor pad 8, and a capacitor adhesive 9.
第１図において、セラミック基板ｌの下面には、ＩＣチ
ップの端子数に等しい複数個のボンディングパッド２お
よび少なくとも２個のコンデンサバ、ド８がボンディン
グパッドエリアに隣接して形成されており、ボンディン
グパッド２の各、々には複数個の接続配線３の各々がつ
ながメれておυ、さらに接続配線３の個々は、セラミッ
ク基板ｌ内に形成されたグイアホール配線５の各々を経
由して、リードピン４に接続されている０ポンデイング
パツドエリアに隣接して形成されている２個のコンデン
サパッド８は、ボンディングパッド２とグイアホール配
線５とを接続した電源及びグランドのラインにそれぞれ
接続され、かつ、コンデンサテップ６のコンデンサ電極
７がコンデンサ接着剤９．すなわち半田あるいは導電性
接着剤等によシ固着接続されている。In FIG. 1, a plurality of bonding pads 2 equal to the number of terminals of the IC chip and at least two capacitor pads 8 are formed adjacent to the bonding pad area on the lower surface of the ceramic substrate l. A plurality of connection wires 3 are connected to each of the pads 2, and each of the connection wires 3 is connected via each of the guiahole wires 5 formed in the ceramic substrate l. Two capacitor pads 8 formed adjacent to the 0-pound pad area connected to the lead pin 4 are connected to the power supply and ground lines connecting the bonding pad 2 and the Guiahole wiring 5, respectively. In addition, the capacitor electrode 7 of the capacitor tip 6 is coated with the capacitor adhesive 9. That is, they are firmly connected using solder, conductive adhesive, or the like.
第２図は本発明のプラグインパッケージＫＩＣテッグｌ
Ｏを搭載して、ＩＣｆ、グ１０の保護をするための中ヤ
ッグ１３と、ＩＣチップ搭載対向面には放熱用ヒートシ
ンク１９とを取シ付けた状態を示す断面図であり、１１
はボンディングワイヤ、１２はＩＣＣタッグ着剤、１４
はキヤ、グ接着剤、２０はヒートシンク接着剤である。Figure 2 shows the plug-in package KICTEGl of the present invention.
11 is a sectional view showing a state in which an inner jacket 13 for protecting the ICf and the IC chip 10 is mounted, and a heat sink 19 for heat dissipation is attached to the surface opposite to the IC chip mounting surface.
is bonding wire, 12 is ICC tag adhesive, 14
20 is a heat sink adhesive.
ＩＣチップ接着剤１２およびヒートシンク接着剤２０と
も良好な熱伝導特性材料から成る本ので、一般的にはエ
ボ午り系樹脂接着剤によシ形成される場合が多い。Since both the IC chip adhesive 12 and the heat sink adhesive 20 are made of materials with good thermal conductivity, they are generally formed using Evo-based resin adhesive in many cases.
以上に述べた本発明に係るプラグインパッケージは、従
来のプラグインパッケージと外形寸法を同サイズでしか
もＩＣチップ１０に隣接してコンデンサパッド６を配置
できるので、グリント配線板あるいはボードにおける配
線領域の拡大と配線の高密度化が可能となり、電気的に
優れたよシ効釆的なノイズ吸収が実現できる。さらに、
ＩＣチック実装対向面に放熱用ヒートシンクが搭載でき
るので放熱特性にも優れたプラグインパッケージが可能
となる。The plug-in package according to the present invention described above has the same external dimensions as the conventional plug-in package, and the capacitor pad 6 can be placed adjacent to the IC chip 10, so that the wiring area on the glint wiring board or board can be It is possible to expand the size and increase the wiring density, and achieve electrically superior and highly effective noise absorption. moreover,
Since a heat sink for heat dissipation can be mounted on the surface facing the IC chip mounting, a plug-in package with excellent heat dissipation characteristics is possible.
発明の効果
以上に説明したように、本発明によれば、セラミック基
板の下面にボンディングパッドを備え、これに隣接して
コンデンサパッドを搭載する構成とすることによル、第
１にプリント配線板あるいはボードにおける配線領域の
拡大と、配線ならびに搭載部品の高密度化が実現でき、
第２に電源及びグランドラインのノイズを有効的に吸収
できるという効果がある。さらには、ヒートシンクが取
シ付けられるので、発熱量の大きい超高集積ＩＣチップ
を実装できるという効果がある０Effects of the Invention As explained above, according to the present invention, by providing a bonding pad on the lower surface of a ceramic substrate and mounting a capacitor pad adjacent to the bonding pad, firstly, a printed wiring board can be improved. Alternatively, it is possible to expand the wiring area on the board and increase the density of wiring and mounted components.
Second, it has the effect of effectively absorbing noise from the power supply and ground lines. Furthermore, since a heat sink can be attached, it is possible to mount ultra-highly integrated IC chips that generate a large amount of heat.
第１図は本発明実施例のプラグインパッケージの断面図
、第２図は第１図のプラグインパッケージにＩＣチップ
を搭載して保護用キャップを実装した状態を示す断面図
、第３図は従来のプラグインパッケージの１例の断面図
、第４図はプリント配線板に第３図の従来のプラグイン
パッケージとコンデンサを実装した状態を示す断面図、
第５図はその全体會示ず斜視図である０
１・・・・・セラミック基板、２・・・・・ボンディン
グパッド、３・・・・・・接続配線、４・・・・・リー
ドピン、５・・・・・・グイ７ホール配線、６・・・・
・・コンデンサパッド、７・・・・・・コンテンサ電極
、ｓ ・・・・・コンデンサパッド、９・・・・・・コ
ンデンサ接着剤、１０・・・・・・ＩＣチップ、１１・
・・・・・ボンディングワイヤ、１２・・・・・・ｌＣ
テ。
プ接着剤、１３・・・・保護用キャップ、１４・・・・
・・キャップ接着剤、１５・・・・・・コンデンサ゛、
１６・・・・・・プリント配線板、１７・・・・・・プ
リント接続配線、１ｇ・・・・・・スルポール、１９・
・・・・・ヒートシンク、２０・・・・・・ヒートシン
ク接着剤。
入 リFIG. 1 is a cross-sectional view of a plug-in package according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the plug-in package of FIG. 1 with an IC chip mounted and a protective cap mounted, and FIG. 4 is a sectional view of an example of a conventional plug-in package; FIG. 4 is a sectional view showing the conventional plug-in package of FIG. 3 and a capacitor mounted on a printed wiring board;
Fig. 5 is a perspective view without showing the entire structure.0 1...ceramic substrate, 2...bonding pad, 3...connection wiring, 4...lead pin, 5... Gui 7 hole wiring, 6...
... Capacitor pad, 7 ... Capacitor electrode, s ... Capacitor pad, 9 ... Capacitor adhesive, 10 ... IC chip, 11.
...Bonding wire, 12...lC
Te. Adhesive, 13...Protective cap, 14...
... Cap adhesive, 15 ... Capacitor,
16...Printed wiring board, 17...Printed connection wiring, 1g...Sulpol, 19.
...Heat sink, 20...Heat sink adhesive. Entering
Claims (1)
ィングパッドと、複数個のリードピンと、前記複数個の
ボンディングパッドと前記複数個のリードピンとを接続
する接続配線およびヴィアホール配線とからなるプラグ
インパッケージにおいて、前記複数個のボンディングパ
ッドと前記複数個のリードピンとを前記セラミック基板
の下面に備え、かつ前記ボンディングパッドエリアに隣
接して少なくとも２個のコンデンサパッドと、これに搭
載される少なくとも１個のコンデンサチップとを備え、
前記コンデンサパッドのおのおのが前記接続配線の電源
またはグランドラインに接続されるとともに前記少なく
とも１個のコンデンサチップの電極に固着接続され、更
に前記複数個のリードピンが前記ボンディングパッドエ
リアおよび前記コンデンサパッドエリアの外側に植立さ
れていることを特徴とするプラグインパッケージ。A plug consisting of a ceramic substrate, a plurality of bonding pads for mounting one IC, a plurality of lead pins, and connection wiring and via hole wiring that connect the plurality of bonding pads and the plurality of lead pins. In the in-package, the plurality of bonding pads and the plurality of lead pins are provided on the lower surface of the ceramic substrate, and at least two capacitor pads are provided adjacent to the bonding pad area, and at least one capacitor pad mounted thereon is provided. Equipped with several capacitor chips,
Each of the capacitor pads is connected to the power supply or ground line of the connection wiring and is fixedly connected to an electrode of the at least one capacitor chip, and the plurality of lead pins are connected to the bonding pad area and the capacitor pad area. A plug-in package characterized by being planted on the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16894084A JPS6147689A (en) | 1984-08-13 | 1984-08-13 | Plug-in package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16894084A JPS6147689A (en) | 1984-08-13 | 1984-08-13 | Plug-in package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6147689A true JPS6147689A (en) | 1986-03-08 |
| JPH0476211B2 JPH0476211B2 (en) | 1992-12-03 |
Family
ID=15877360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16894084A Granted JPS6147689A (en) | 1984-08-13 | 1984-08-13 | Plug-in package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6147689A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01166543A (en) * | 1987-09-29 | 1989-06-30 | Bull Sa | Vlsi package |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8940265B2 (en) | 2009-02-17 | 2015-01-27 | Mcalister Technologies, Llc | Sustainable economic development through integrated production of renewable energy, materials resources, and nutrient regimes |
| US9097152B2 (en) | 2009-02-17 | 2015-08-04 | Mcalister Technologies, Llc | Energy system for dwelling support |
| US9231267B2 (en) | 2009-02-17 | 2016-01-05 | Mcalister Technologies, Llc | Systems and methods for sustainable economic development through integrated full spectrum production of renewable energy |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5864095A (en) * | 1981-10-14 | 1983-04-16 | 日本電気株式会社 | Multilayer circuit board with connecting pins |
| JPS5954248A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Semiconductor device |
-
1984
- 1984-08-13 JP JP16894084A patent/JPS6147689A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5864095A (en) * | 1981-10-14 | 1983-04-16 | 日本電気株式会社 | Multilayer circuit board with connecting pins |
| JPS5954248A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01166543A (en) * | 1987-09-29 | 1989-06-30 | Bull Sa | Vlsi package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0476211B2 (en) | 1992-12-03 |
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