JPS5954248A - Semiconductor device - Google Patents

Abstract

PURPOSE:To absorb noises effectively, by providing pads, which are connected to power supply pins and grounding pins, on a multilayer ceramic package containing an IC chip, and mounting a capacitor. CONSTITUTION:Pads 10 and 10 are provided at vacant regions at both ends in the longitudinal direction of a multiple pin package 1. The pads are connected to power source lines, grounding lines, power source pins, and grounding pins of an IC chip 2 through wirings 11 and 12 in the appropriate layers of the multilayer package. External electrodes 5c and 5d of a multilayer ceramic type capacitor 5 are soldered 9. The capacity of said bypass capacitor is about 0.01-5muF. In this constitution, the distance between the capacitor and the IC chip can be shortened, and internal and external noises can be effectively absorbed. Since the capacitor is attached in the vacant space, the mounting density can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device using a multi-layered ceramic circuit, and is intended to incorporate a bypass capacitor between a power supply and a ground in an S product circuit.

Background of the Technology As semiconductor integrated circuits (ICs) become faster and more highly integrated, the importance of noise protection II.1 connected between the power supply and ground, and bypass for preventing malfunctions, is increasing. I'm in the middle of the day. The conventional Ha Ipas '2 J Ndenri' is I
It is generally connected between the power line and ground line of the printed circuit board on which the C package is mounted. This is because noise from the outside world gets on the power supply input and enters the IC.
This is because the main focus is to prevent the IC from malfunctioning. However, as ICs become more highly integrated in order to achieve higher speeds, the inductance of the IC and the inductance distributed in the power supply line between the IC and the capacitor are ignored. The current pulse of the IC itself is not sufficiently absorbed by the capacitor and turns into a voltage), causing the IC to malfunction.
f “R5?:!It has been done.

The present invention is intended to incorporate the two bypass condensers into the IC package-1 to absorb the internal and external types into the 91. original music.

Structure of the Invention The semiconductor device of the present invention is provided with a Ninon capacitor-mounted basso 1 connected to a power supply bin and a ground I pin through inner layer wiring, respectively, in a part of a multilayer ceramic package that accommodates a flat conductor layered circuit depth. The device is characterized in that an electrode of a chip capacitor is connected to the bat, which will be described in detail below without reference to the illustrated embodiment.

Embodiment of the Invention FIG. 1 is an explanatory diagram showing an embodiment of the present invention, in which (al) is an overall perspective view, and (1) is a partially sectional side view.

In the figure, I is a dual in-line type IC multilayer ceramic package, 2 is a jC chip mounted in the four central parts, 3 is a cap that seals the recessed fHH opening 1-1, and 4 is a pin (anchor 1). ), 5υ31 is a multi-IF-12, which is used as another sensor for the 5υ31 bus. l □Chip 2 is Ba.

The eutectic (j゛(chip i', j()) of Δu/','+i is placed in the center of the cage, and the line 7 of ΔIJ or Δp is connected to one part of the end rose disposed at the step around the chip. Soi'
-1- Bonded. In addition, the sealing IL part 8 of the cap 3 is welded using ε, 1ΔU/3n or Pb/Sn, or by the welding method. Then, C is connected to each wiring of the IC chip 2 through the wiring of each layer passing through the basso gauge and the via hole to the terminal pad (1).

As the number of pins 4 increases, the dimensions of the package (2) in the narrow direction become longer, but the mounting area of the IC chip 2 does not increase significantly, so empty areas are created at both ends. :l Densor 5 is mounted in this empty area. For example, solder is used for the adhesive portion 9. Figure 1 (cl LJ multilayer ceramic chip capacitor 5, etc.)
b is a multi-layered j-direction electrode; 5c;

5d is an external electrode that commonly connects one end of these.

((j) is a cross-sectional view of the bonded state, 10a, 1 (11) is a capacitor mounting pad. This pad 10a, IO
b is (wiring installed in the appropriate layer of the multilayer package (preferably a layer above the IC chip mounting surface for ease of wiring) as shown in el) 1.12 to the power supply line and ground on the inner layer of the IC chip. line, and to the power supply pin and ground pin of the IC chip.If two capacitors 5 are used, they are connected in parallel between lines 11 and 12, but one of them may be omitted depending on the required capacity. The capacity of one J-den V'5 varies depending on the IC chip 2 used, but it is approximately 0.0.
It is about 1 to 5 μm.

FIG. 2 shows another embodiment of the present invention, in which a four part 20 is provided at the bottom of the package 1, a chip condenser 5 is provided thereon, and a 1h mounting hole loa, 1( lb. In this way, the displacement will prevent the second sensor 5 from protruding onto the surface of the passo gauge.

Figure (b) is a plan view. ls, 1 side 2 of recess 2o
0a may be blocked, but if it is open, Soranox 6I after half-III implementation of Content 'II-5
The fifth order is easy. (C1 is an example of a concave portion 21 with a narrow open end. This makes it easy to align the condenser '5. Note that there is a 224; l mark in (8).

Effects of the Invention As described above, according to the present invention, the multilayer ceramic two-layer 1. Since the bypass content between the power supply and the clan I is mounted on the CPU, the distance between the connector and the IC chip is shortened, and malfunctions due to internal and external types are prevented. -・layer fr(#becomes fruit.

In addition, since the part where the bypass condenser is mounted is an area that is left over in the package, it is necessary to remove the -1 condenser from the package (to be more specific, to achieve a higher mounting density than when mounting it on a ground board). is Ir1i 31:ru.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing one embodiment of the invention, and FIG. 2 is an explanatory diagram showing another embodiment of the invention. In the figure, 1 is multilayer ceramic material 4-27.24.1
．． 10 chips, 5 is H・f passco 1 tensa, I (12
, 101) is Bano i on -1 and 1h. Applicant Tomijutsu Co., Ltd. 1 Representative Patent Attorney Minoru Aoyagi 1 @ 2 [missing 1 ((1) 3 wo)

Claims (3)

[Claims] (1) A capacitor mounting band is provided in a part of a multilayer ceramic package that houses a semiconductor integrated circuit chip, and is connected to a power supply pin and a ground pin by internal 1i wiring, and the electrodes of a chimbu capacitor are connected to the pads. A semiconductor device characterized by: (2) The semiconductor device according to claim 1, wherein the pad is numbered on the top surface of the multilayer ceramic package. (3) A recess with a depth equivalent to the thickness of the tinop capacitor and an open end surface in the longitudinal direction of the package is provided on the top surface of the multilayer ceramic package, and a power supply bottle and a ground pin are provided on the bottom of the recess. The semiconductor device according to claim 1, further comprising a capacitor mounting bat connected to the semiconductor device.