JPS63208252A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS63208252A
JPS63208252A JP62041881A JP4188187A JPS63208252A JP S63208252 A JPS63208252 A JP S63208252A JP 62041881 A JP62041881 A JP 62041881A JP 4188187 A JP4188187 A JP 4188187A JP S63208252 A JPS63208252 A JP S63208252A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrodes
package
layer
lower layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62041881A
Other languages
Japanese (ja)
Inventor
Masaaki Kanda
神田　正明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62041881A priority Critical patent/JPS63208252A/en
Publication of JPS63208252A publication Critical patent/JPS63208252A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the number of electrodes per unit packaging area, by providing a plurality of staircase parts, and providing the electrodes for external connections at the respective staircase parts. CONSTITUTION:A double-layer structure comprises an upper layer and a lower layer. Electrodes 11 and 12 are provided at the respective staircase parts of the two layers, i.e., at the four sides of the upper side surface of the lower layer and at the four sides of opposite surface of the upper layer with respect to the lower layer. In this way, a package for semiconductor device is constituted so that a plurality of the staircase parts having the electrodes 11 and 12 for outer connection are provided. Therefore, the number of the electrodes per unit packaging area becomes many, and the packaging area is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用パッケージに関し、特に集積回路
を収容する半導体装置用パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor device, and more particularly to a package for a semiconductor device that accommodates an integrated circuit.

〔従来の技術〕[Conventional technology]

従来のかかる半導体装置用パッケージは、第３図に一例
を示すように、一つの面の４辺（ものによっては３辺以
下のこともある）に外部接続用の電極１１が設けられて
いた。通常、この面でプリント基板等に実装され、この
面の面積は電極数が多くなれば大きくなる。In such a conventional package for a semiconductor device, as an example shown in FIG. 3, electrodes 11 for external connection are provided on four sides (or less than three sides depending on the package) of one surface. Usually, this surface is mounted on a printed circuit board or the like, and the area of this surface increases as the number of electrodes increases.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上説明したように従来の半導体装置用パッケージは、
一つの面の辺にしか電極が設けられていないので単位実
装面積当シの電極数には限度があシ、電極数が多くなる
と大きな実装面積を要するという欠点がある。As explained above, conventional semiconductor device packages are
Since the electrodes are provided only on the side of one surface, there is a limit to the number of electrodes per unit mounting area, and a large number of electrodes requires a large mounting area.

本発明の目的は、上記欠点を解決して単位実装面積当シ
の電極数を多くすることができる半導体装置用パッケー
ジを提供することにある。An object of the present invention is to provide a package for a semiconductor device that can solve the above-mentioned drawbacks and increase the number of electrodes per unit mounting area.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置用パッケージは、それぞれ外部接続
用の電極を有する複数層の階段状部分を備えて構成され
る。The package for a semiconductor device of the present invention includes a plurality of stepped portions each having an electrode for external connection.

〔実施例〕〔Example〕

以下実施例を示す図面を参照して本発明について詳細に
説明する。The present invention will be described in detail below with reference to drawings showing embodiments.

第１図は、本発明の半導体装置用パッケージの第一の実
施例を示す斜視図である。FIG. 1 is a perspective view showing a first embodiment of a package for a semiconductor device according to the present invention.

第１図に示す実施例は、上層および下層（面積の小さい
方を上層、大きい方を下層ということにする）の２層構
造をなしておシ、これら２層のそれぞれの階段状部分、
すなわち、下層の上層側面の４辺および上層の下層と反
対側の面の４辺に電極１１および１２が設けられている
。The embodiment shown in FIG. 1 has a two-layer structure of an upper layer and a lower layer (the smaller area is referred to as the upper layer and the larger area is referred to as the lower layer), and the stepped portions of each of these two layers,
That is, the electrodes 11 and 12 are provided on four sides of the upper layer side surface of the lower layer and on four sides of the upper layer side surface opposite to the lower layer.

第２図は、第１図に示す実施例（を用いた半導体装置）
の実装状態を示す縦断面図である。Figure 2 shows the embodiment shown in Figure 1 (semiconductor device using)
FIG.

第２図において、１は第１図に示す半導体装置用パッケ
ージ、２は半導体装置用パッケージｌを実装する積層プ
リント基板である。In FIG. 2, 1 is a semiconductor device package shown in FIG. 1, and 2 is a laminated printed circuit board on which the semiconductor device package 1 is mounted.

積層プリント基板２は、表面層のプリント配線２１と、
内部層のプリント配線２２とを備えている。The laminated printed circuit board 2 includes a surface layer printed wiring 21,
It also includes internal layer printed wiring 22.

ｔｉｔ層プリプリント基板２プリント起部２１を貫通し
てプリント配線２２が露出するように、半導体装置用パ
ッケージ１の上層物分が入る凹部を設ける。半導体装置
用パッケージ１の電極１１．１２を積層プリント基板２
のプリント配線２１．２２に、ろう何部２３を介して接
続する。A recess into which the upper layer of the semiconductor device package 1 is inserted is provided so that the printed wiring 22 is exposed through the printed origin 21 of the tit layer pre-printed board 2. The electrodes 11 and 12 of the semiconductor device package 1 are connected to the laminated printed circuit board 2.
It is connected to the printed wirings 21 and 22 of 2 through the wax part 23.

第４図は、本発明の半導体装置用パッケージの第二の実
施例を示す斜視図である。FIG. 4 is a perspective view showing a second embodiment of the semiconductor device package of the present invention.

第４図に示す実施例は、下層−中央層および上層の３層
構造をなしており、これら各層のそれぞれの階段状部分
に電極１１，１２．１３が設けられている。The embodiment shown in FIG. 4 has a three-layer structure consisting of a lower layer, a middle layer, and an upper layer, and electrodes 11, 12, and 13 are provided at the stepped portions of each of these layers.

第５図は、本発明の半導体装置用パッケージの第三の実
施例を示す斜視図である。FIG. 5 is a perspective view showing a third embodiment of the semiconductor device package of the present invention.

第５図に示す実施例は、２層構造である点では第１図に
示す実施例と同じであるが、下層の階段状部分は相対す
る一組の２辺にしかなく、下層の電極１１もこれら２辺
にのみ設けられている。The embodiment shown in FIG. 5 is the same as the embodiment shown in FIG. 1 in that it has a two-layer structure, but the stepped portions in the lower layer are only on one pair of opposing sides, and the electrodes 11 in the lower layer are provided only on these two sides.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明の半導体装置用パッケ
ージは、複数基の階段状部分を備えておシ、各層のそれ
ぞれの階段状部分に外部接続用の電極を有しているので
、単位実装面積当りの電極数を多くすることができる効
果がある。As described in detail above, the semiconductor device package of the present invention has a plurality of stepped portions, and each stepped portion of each layer has an electrode for external connection. This has the effect of increasing the number of electrodes per area.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の半導体装置用パッケージの第一の実
施例を示す斜視図。 第２図は、第１図に示す実施例の実装状態を示す縦断面
図。 第３図は、従来の半導体装置用パッケージの一例を示す
斜視図。 第４図は、本発明の半導体装置用パッケージの第二の実
施例を示す斜視図。 第５図は同じく第三の実施例を示す斜視図である。 １・・・・・・半導体装置用パッケージ、２・・・・・
・積層プリント基板、１１〜１３・・・・・・電極、２
１・２２・・・・・・プリント配線、２３・・・・・・
ろう何部。 ガ１　回 万３旧FIG. 1 is a perspective view showing a first embodiment of a package for a semiconductor device of the present invention. FIG. 2 is a longitudinal sectional view showing the mounting state of the embodiment shown in FIG. 1. FIG. 3 is a perspective view showing an example of a conventional package for a semiconductor device. FIG. 4 is a perspective view showing a second embodiment of the semiconductor device package of the present invention. FIG. 5 is a perspective view similarly showing the third embodiment. 1...Semiconductor device package, 2...
・Laminated printed circuit board, 11-13... Electrode, 2
1・22...Printed wiring, 23...
How many parts are there? ga 1 times 10,000 old

Claims (1)

【特許請求の範囲】[Claims] それぞれ外部接続用の電極を有する複数層の階段状部分
を備えることを特徴とする半導体装置用パッケージ。A package for a semiconductor device comprising a plurality of stepped portions each having an electrode for external connection.
JP62041881A 1987-02-24 1987-02-24 Package for semiconductor device Pending JPS63208252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62041881A JPS63208252A (en) 1987-02-24 1987-02-24 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62041881A JPS63208252A (en) 1987-02-24 1987-02-24 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS63208252A true JPS63208252A (en) 1988-08-29

Family

ID=12620615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62041881A Pending JPS63208252A (en) 1987-02-24 1987-02-24 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS63208252A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146308A (en) * 1990-10-05 1992-09-08 Micron Technology, Inc. Semiconductor package utilizing edge connected semiconductor dice
DE4238402A1 (en) * 1991-11-14 1993-05-19 Samsung Electronics Co Ltd
US5450289A (en) * 1993-03-05 1995-09-12 Samsung Electronics Co., Ltd. Semiconductor package and a printed circuit board applicable to its mounting
US5604328A (en) * 1992-07-27 1997-02-18 Murata Manufacturing Co., Ltd. Multilayer electronic component
US5635669A (en) * 1992-07-27 1997-06-03 Murata Manufacturing Co., Ltd. Multilayer electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146308A (en) * 1990-10-05 1992-09-08 Micron Technology, Inc. Semiconductor package utilizing edge connected semiconductor dice
DE4238402A1 (en) * 1991-11-14 1993-05-19 Samsung Electronics Co Ltd
US5604328A (en) * 1992-07-27 1997-02-18 Murata Manufacturing Co., Ltd. Multilayer electronic component
US5635669A (en) * 1992-07-27 1997-06-03 Murata Manufacturing Co., Ltd. Multilayer electronic component
US5635670A (en) * 1992-07-27 1997-06-03 Murata Manufacturing Co., Ltd. Multilayer electronic component
US5450289A (en) * 1993-03-05 1995-09-12 Samsung Electronics Co., Ltd. Semiconductor package and a printed circuit board applicable to its mounting

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