JPH0298652U - - Google Patents

Info

Publication number
JPH0298652U
JPH0298652U JP806989U JP806989U JPH0298652U JP H0298652 U JPH0298652 U JP H0298652U JP 806989 U JP806989 U JP 806989U JP 806989 U JP806989 U JP 806989U JP H0298652 U JPH0298652 U JP H0298652U
Authority
JP
Japan
Prior art keywords
package
board
notch
lower surfaces
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP806989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP806989U priority Critical patent/JPH0298652U/ja
Publication of JPH0298652U publication Critical patent/JPH0298652U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Multi-Conductor Connections (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本考案の半導体実装構造の
第1の実施例を示す斜視図、第3図は基板とパツ
ケージの厚さがほぼ同一の場合の実施例の断面図
、第4図は基板よりもパツケージの厚さが大きい
場合の第2の実施例の断面図、第5図は従来例の
断面図である。 1……パツケージ、2……ピン、3……プリン
ト配線基板、5……切欠部。
1 and 2 are perspective views showing a first embodiment of the semiconductor packaging structure of the present invention, FIG. 3 is a sectional view of the embodiment in which the thickness of the board and the package are almost the same, and FIG. 4 5 is a sectional view of the second embodiment in which the thickness of the package is larger than that of the substrate, and FIG. 5 is a sectional view of the conventional example. 1... Package cage, 2... Pin, 3... Printed wiring board, 5... Notch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パツケージに対応した大きさの切欠部を備えた
基板と、左右両側の上面及び下面に各々ピンが配
置されたパツケージとを有し、上記上面及び下面
のピンによつて基板を挟むようにパツケージを切
欠部に実装したことを特徴とする半導体実装装置
It has a board with a notch of a size corresponding to the package, and a package with pins arranged on the upper and lower surfaces of both left and right sides, and the package is held so that the board is sandwiched between the pins on the upper and lower surfaces. A semiconductor mounting device characterized in that it is mounted in a notch.
JP806989U 1989-01-26 1989-01-26 Pending JPH0298652U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP806989U JPH0298652U (en) 1989-01-26 1989-01-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP806989U JPH0298652U (en) 1989-01-26 1989-01-26

Publications (1)

Publication Number Publication Date
JPH0298652U true JPH0298652U (en) 1990-08-06

Family

ID=31213620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP806989U Pending JPH0298652U (en) 1989-01-26 1989-01-26

Country Status (1)

Country Link
JP (1) JPH0298652U (en)

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