JPS6382948U - - Google Patents
Info
- Publication number
- JPS6382948U JPS6382948U JP17680586U JP17680586U JPS6382948U JP S6382948 U JPS6382948 U JP S6382948U JP 17680586 U JP17680586 U JP 17680586U JP 17680586 U JP17680586 U JP 17680586U JP S6382948 U JPS6382948 U JP S6382948U
- Authority
- JP
- Japan
- Prior art keywords
- package
- sides
- mini
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａおよびｂはそれぞれ本考案の実施例を
示す部分平面図および側面図、第２図ａおよびｂ
はそれぞれ本考案の他の実施例を示す部分平面図
および側面図、第３図は本考案のミニフラツト・
パツケージ半導体集積回路装置の基板への実装図
、第４図は従来のミニフラツト・パツケージ半導
体装置の断面図、第５図は従来のミニフラツト・
パツケージを基板両面に搭載した場合の一例を示
す図である。
１……パツケージ、Ａ……パツケージ表面、Ｂ
……パツケージ裏面、２……リード、３……基板
、４，５……一番ピン。
Figures 1a and b are a partial plan view and a side view showing an embodiment of the present invention, respectively; Figures 2a and b are
3 is a partial plan view and a side view respectively showing other embodiments of the present invention, and FIG.
FIG. 4 is a cross-sectional view of a conventional mini-flat package semiconductor device, and FIG. 5 is a diagram of a conventional mini-flat package semiconductor device mounted on a board.
FIG. 3 is a diagram showing an example of a case where packages are mounted on both sides of a substrate. 1...Package, A...Package surface, B
...back of package cage, 2...lead, 3...board, 4,5...first pin.
Claims (1)
において、前記ミニフラツト・パツケージの側面
から引出されるリードがパツケージの裏面および
表面の両側に折曲げられパツケージの２つの面と
それぞれ平行方向に引出されていることを特徴と
する半導体集積回路装置。 The mini-flat package semiconductor integrated circuit device is characterized in that the leads drawn out from the sides of the mini-flat package are bent on both sides of the back and front surfaces of the package, and are drawn out in parallel directions with the two sides of the package. semiconductor integrated circuit devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680586U JPS6382948U (en) | 1986-11-17 | 1986-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680586U JPS6382948U (en) | 1986-11-17 | 1986-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6382948U true JPS6382948U (en) | 1988-05-31 |
Family
ID=31117408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17680586U Pending JPS6382948U (en) | 1986-11-17 | 1986-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6382948U (en) |
-
1986
- 1986-11-17 JP JP17680586U patent/JPS6382948U/ja active Pending