JPS63307751A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS63307751A
JPS63307751A JP14462387A JP14462387A JPS63307751A JP S63307751 A JPS63307751 A JP S63307751A JP 14462387 A JP14462387 A JP 14462387A JP 14462387 A JP14462387 A JP 14462387A JP S63307751 A JPS63307751 A JP S63307751A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
electrode
semiconductor integrated
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14462387A
Other languages
Japanese (ja)
Inventor
Mikio Bessho
別所　幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14462387A priority Critical patent/JPS63307751A/en
Publication of JPS63307751A publication Critical patent/JPS63307751A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To make a chip small in area by a method wherein a through hole section is provided just under the electrode of a semiconductor integrated circuit device which is provided with the externally connecting electrode built on the semiconductor chip and an internal wiring to be electrically connected with the electrode through the intermediary of the through hole section. CONSTITUTION:A semiconductor integrated circuit device is provided with an externally connecting electrode 12 on a semiconductor chip and an internal wiring 22 to be electrically connected with the electrode 12 through the intermediary of a through hole section 13, where the through hole section 13 is formed just under the electrode 12. For instance, the through hole section 13 is provided just under a PAD consisting of the second aluminum 12 and connected with a first aluminum 11 thereunder. Therefore, the PAD can be provided close to the internal wiring 22 so as to enable the chip to be smaller in area.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に係り、特にＣＭＯＳゲー
トアレイなどの多層金属配線を有する外部接続用電極（
ＰＡＤ）に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an external connection electrode (
PAD).

〔従来の技術〕[Conventional technology]

従来、この種の半導体集積回路装置は、第２図（５）、
第２図（Ｂ）に示す様に、半導体チップ上のＰＡＤとな
る最上金属層（第２アルミニウム）１２をスルーホール
部１３を介して中間金属層（第１アルミニウム）１１に
接続し、この第１アルミニウム１１は、内部金属配線２
２の下の絶縁層下を通って、内部配線に接続される。Conventionally, this type of semiconductor integrated circuit device is shown in FIG. 2 (5),
As shown in FIG. 2(B), the uppermost metal layer (second aluminum) 12, which becomes the PAD on the semiconductor chip, is connected to the intermediate metal layer (first aluminum) 11 via the through-hole portion 13, and this 1 Aluminum 11 is internal metal wiring 2
It passes under the insulating layer under 2 and is connected to the internal wiring.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した従来の半導体集積回路装置では、第１アルミニ
ウム１１と第２アルミニウム１２とをスルーホール部１
３を設けて接続しているので、特にワイヤ・ポンディン
グされるＰＡＤと内部配線２２とが互いに近くに配置で
きなくなり、チップ面積が大きくなるという欠点がある
。In the conventional semiconductor integrated circuit device described above, the first aluminum 11 and the second aluminum 12 are connected to the through hole portion 1.
3 for connection, there is a drawback that the PAD to be wire bonded and the internal wiring 22 cannot be placed close to each other, and the chip area becomes large.

本発明の目的は、前記欠点が解決され、ＰＡＤと内部配
線とが極めて近くに配置でき、チップ面積が小さくて済
むようにした半導体集積回路装置を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which the above-mentioned drawbacks are solved, the PAD and internal wiring can be placed extremely close to each other, and the chip area can be reduced.

ｒ問題点を解決するだめの手段〕 本発明の構成は、半導体チップ上の外部接続用電極と、
スルーホール部を介してこの電極と電気的に接続される
内部配線とを備えた半導体集積回路装置において、前記
電極の直下に、前記スルーホール部が形成されているこ
とを特徴とする。[Means for Solving Problems r]] The structure of the present invention includes an external connection electrode on a semiconductor chip,
The semiconductor integrated circuit device includes an internal wiring electrically connected to the electrode via a through-hole portion, wherein the through-hole portion is formed directly below the electrode.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明する。第
１凹穴は本発明の一実施例の半導体集積回路装置を示す
平面図、第１図ＣＢ＋は第１図（５）のＢ−Ｂ’線に沿
って切断して見た断面図である。Next, the present invention will be explained in detail with reference to the drawings. The first recessed hole is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 1 CB+ is a cross-sectional view taken along line BB' in FIG. 1 (5). .

これら図において、第２アルミニウム１２で構成された
ＰＡＤの直下に、スルーホール部１３を設け、下の第１
アルミニウム１１と接続する。従って、ＰＡＤと内部配
線２２とを近づけることができる。特に多層金属配線を
有する半導体集積回路の外部接続用電極をスルーホール
を通して電極直下に多層金属配線を接続丼すると効果的
である。In these figures, a through-hole section 13 is provided directly below the PAD made of second aluminum 12, and the first
Connect with aluminum 11. Therefore, the PAD and internal wiring 22 can be brought close to each other. In particular, it is effective to connect the external connection electrode of a semiconductor integrated circuit having multilayer metal wiring through a through hole and connect the multilayer metal wiring directly below the electrode.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、電極ＰＡＤの直下にス
ルーホールを設けて、ＰＡＬ）の第２アルミニウムと第
１アルミニウムとを接続する事によυ、ＰＡＤ内部配線
との距離が近づける事ができて、チップ面積を縮小でき
る効果がある。As explained above, in the present invention, by providing a through hole directly under the electrode PAD and connecting the second aluminum and the first aluminum of the PAL, the distance to the internal wiring of the PAD can be reduced. This has the effect of reducing the chip area.

【図面の簡単な説明】[Brief explanation of drawings]

第１凹穴は本発明の一実施例の半導体集積回路装置の平
面図、第１図（Ｂｌは第１凹穴のＢ−Ｂ’線に沿って切
断して見た断面図、第２凹穴は従来の半導体集積回路装
置の平面図、第２図（Ｂｌは第２図（５）のＢ−Ｂ’線
に沿って切断して見た断面図である。 １１・・・第１アルミニウム、１２・・・第２アルミニ
ウム、１３・・・スルーホール部、２２・・・内部配線
。 代理人　弁理士　　内　原　　　音 生　１　フ（Ａ） 千　１　羽（Ｂ） 第２図（Ａ） 翳２　凹（Ｂ）The first recess is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. The hole is a plan view of a conventional semiconductor integrated circuit device, and FIG. 2 is a cross-sectional view taken along line BB' in FIG. 2 (5). 11... First aluminum , 12...Second aluminum, 13...Through hole portion, 22...Internal wiring. Agent Patent attorney Otoki Uchihara 1 Fu (A) 101 Feather (B) Fig. 2 (A) Shadow 2 concave (B)

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップ上の外部接続用電極と、スルーホール部
を介してこの電極と電気的に接続される内部配線とを備
えた半導体集積回路装置において、前記電極の直下に、
前記スルーホール部が形成されていることを特徴とする
半導体集積回路装置。In a semiconductor integrated circuit device comprising an external connection electrode on a semiconductor chip and internal wiring electrically connected to this electrode via a through-hole portion, directly below the electrode,
A semiconductor integrated circuit device characterized in that the through-hole portion is formed.
JP14462387A 1987-06-09 1987-06-09 Semiconductor integrated circuit device Pending JPS63307751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14462387A JPS63307751A (en) 1987-06-09 1987-06-09 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14462387A JPS63307751A (en) 1987-06-09 1987-06-09 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS63307751A true JPS63307751A (en) 1988-12-15

Family

ID=15366342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14462387A Pending JPS63307751A (en) 1987-06-09 1987-06-09 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63307751A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105644A (en) * 1980-01-25 1981-08-22 Mitsubishi Electric Corp Semiconductor ic device
JPS6162666A (en) * 1984-09-04 1986-03-31 Mitsubishi Heavy Ind Ltd Pressurized casing
JPS6164147A (en) * 1984-09-05 1986-04-02 Nec Corp Semiconductor device
JPS6262449B2 (en) * 1982-06-29 1987-12-26 Matsushita Electric Ind Co Ltd

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105644A (en) * 1980-01-25 1981-08-22 Mitsubishi Electric Corp Semiconductor ic device
JPS6262449B2 (en) * 1982-06-29 1987-12-26 Matsushita Electric Ind Co Ltd
JPS6162666A (en) * 1984-09-04 1986-03-31 Mitsubishi Heavy Ind Ltd Pressurized casing
JPS6164147A (en) * 1984-09-05 1986-04-02 Nec Corp Semiconductor device

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