JPS63304645A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS63304645A JPS63304645A JP62140222A JP14022287A JPS63304645A JP S63304645 A JPS63304645 A JP S63304645A JP 62140222 A JP62140222 A JP 62140222A JP 14022287 A JP14022287 A JP 14022287A JP S63304645 A JPS63304645 A JP S63304645A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring layer
- wiring
- semiconductor substrate
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 48
- 238000009792 diffusion process Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に基板電位の安定化
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to stabilization of substrate potential.
従来、この種の半導体集積回路は第３図に示す様に半導
体基板１にコンタクトをとるために形成された拡散領域
２とその上部に層間絶縁層３を介して形成された電源用
の配線層４及びカバ一層５から構成されておシ、前記拡
散領域２と配線層４は層間絶縁層３に設けられた接続孔
６によって接続され、更にカバ一層５の一部を削除する
ことによってボンディングパッド７が形成される。Conventionally, this type of semiconductor integrated circuit has a diffusion region 2 formed to make contact with a semiconductor substrate 1 and a wiring layer for power supply formed above the diffusion region 2 with an interlayer insulating layer 3 interposed therebetween, as shown in FIG. 4 and a cover layer 5, the diffusion region 2 and the wiring layer 4 are connected through a contact hole 6 provided in the interlayer insulating layer 3, and bonding pads are formed by removing a part of the cover layer 5. 7 is formed.
以上の様な構成を有する半導体集積回路において拡散領
域２及び配線層４との接続孔６はボンディングパッド７
から離れた位置に形成されていた。In the semiconductor integrated circuit having the above configuration, the connection hole 6 between the diffusion region 2 and the wiring layer 4 is connected to the bonding pad 7.
It was formed at a distance from
上述した従来の半導体集積回路は、半導体基板とコンタ
クトをとるための拡散領域がボンディングパッドから離
れているため配線に流れる電流と配線の持つ抵抗によっ
て雑音電圧が発生し半導体基板の電位が安定しないとい
う欠点がある。In the conventional semiconductor integrated circuit described above, the diffusion region for making contact with the semiconductor substrate is located far from the bonding pad, so the current flowing through the wiring and the resistance of the wiring generate noise voltage, making the potential of the semiconductor substrate unstable. There are drawbacks.
本発明の半導体集積回路は、ボンディングパッドを有す
る半導体集積回路において、該ボンディングパッドを形
成する配線層は、その直下の半導体基板上に形成された
拡散領域と、その上部に形成された層間絶縁層に設けら
れた接続孔によって接続されている。The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a bonding pad, in which a wiring layer forming the bonding pad includes a diffusion region formed on a semiconductor substrate immediately below the wiring layer and an interlayer insulating layer formed on the wiring layer. They are connected through connection holes provided in the.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を示す半導体集積回路の
断面図であシ、半導体基板１にコンタクトをとるために
形成された拡散領域２と、その上部に層間絶縁層３を介
して形成された電源用の配線層４及びカバ一層５から構
成されておシ前記拡散領域２と配線層４は層間絶縁層３
に設けられた接続孔６によって接続され、拡散領域２と
接続孔６はボンディングパッド７の直下に配置されてい
る。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit showing a first embodiment of the present invention. The diffusion region 2 and the wiring layer 4 are formed by an interlayer insulating layer 3.
The diffusion region 2 and the connection hole 6 are arranged directly under the bonding pad 7 .
従って拡散領域２とボンディング７を接続するための配
線の長さが短かく、抵抗を小さな値にすることができる
ため配線層４に流れる電流による雑音電圧の影響が軽減
でき半導体基板ｌの電位を安定化できる。Therefore, the length of the wiring for connecting the diffusion region 2 and the bonding 7 is short, and the resistance can be reduced to a small value, so that the influence of noise voltage due to the current flowing through the wiring layer 4 can be reduced, and the potential of the semiconductor substrate l can be reduced. It can be stabilized.
更にボンディングパッドは比較的大きな面積をしめるた
め拡散領域の面積と接続孔を大きくとることができ半導
体基波とのコンタクトを十分にとることかできる。Furthermore, since the bonding pad has a relatively large area, the area of the diffusion region and the contact hole can be made large, and sufficient contact with the semiconductor fundamental wave can be made.
第２図は本発明の第２の実施例を示す半導体集積回路の
断面図であり、第１の実施例は配線層が１層であるのに
対して同図は配線層の２層の場合である。FIG. 2 is a cross-sectional view of a semiconductor integrated circuit showing a second embodiment of the present invention. The first embodiment has one wiring layer, while the figure shows a case where there are two wiring layers. It is.
半導体基板１上に形成された拡散領域２とその上部に第
１の層間絶縁層１２を介して形向された第１の配線層１
０と第１の配線層の上部に電２の層間絶雰層１３を介し
て形成された第２の配線層１１、更に第２の配線層１１
の上部に形成されたカバ一層５から構成されておシ、前
記拡散領域２と第１の配線層１０は接続孔８によって、
又第１の配線層１０と第２の配線層１１は接続孔９によ
って各々接続されている。A diffusion region 2 formed on a semiconductor substrate 1 and a first wiring layer 1 formed on the diffusion region 2 with a first interlayer insulating layer 12 interposed therebetween.
A second wiring layer 11 is formed on top of the wiring layer 0 and the first wiring layer with an interlayer insulation layer 13 interposed therebetween, and further a second wiring layer 11.
The diffusion region 2 and the first wiring layer 10 are connected to each other by connection holes 8.
Further, the first wiring layer 10 and the second wiring layer 11 are connected to each other through connection holes 9.
従って第１の実施例と同様に雑音電圧による影響が軽減
でき、半導体基板の電位を安定化できる。Therefore, as in the first embodiment, the influence of noise voltage can be reduced and the potential of the semiconductor substrate can be stabilized.
又、本実施例は更に多層配線の場合にも応用できる。Furthermore, this embodiment can also be applied to multilayer wiring.
以上説明したように本発明は、半導体集積回路において
電源用のボンディングパッドを形成する配線層と、その
直下の半導体基板にコンタクトをとるために形成された
拡散領域とを、その間に形成された眉間絶縁層に設けら
れた接続孔によって直接接続されているので、配線によ
る抵抗が小さく、電源電流による雑音電圧の影響を軽減
でき、半導体基板の電位を安定化することができる効果
がある。As explained above, the present invention connects a wiring layer that forms a bonding pad for a power supply in a semiconductor integrated circuit and a diffusion region that is formed to make contact with the semiconductor substrate directly below the wiring layer to form a bonding pad between the eyebrows. Since they are directly connected through connection holes provided in the insulating layer, the resistance caused by the wiring is low, the influence of noise voltage due to power supply current can be reduced, and the potential of the semiconductor substrate can be stabilized.
第１図は本発明の第１の実施例を示す半導体集積回路の
断面図、第２図は本発明の第２の実施例を示す半導体集
積回路の断面図、第３図は従来の半導体集積回路の例を
示す断面図である。
１・・・・・・半導体基板、２・・・・・・拡散領域、
３・・・・・・層間絶縁層、４・・・・・・配線層、５
・・・・・・カバ一層、６゜８．９・・・・・・接続孔
、７・・・・・・ボンディングパッド、１０・・・・・
・第１の配線層、１１・・・・・・第２の配線層、１２
・１・・・・第１の層間絶縁層、１３・・・・・・第２
の層間絶縁層。FIG. 1 is a sectional view of a semiconductor integrated circuit showing a first embodiment of the invention, FIG. 2 is a sectional view of a semiconductor integrated circuit showing a second embodiment of the invention, and FIG. 3 is a sectional view of a conventional semiconductor integrated circuit. FIG. 2 is a cross-sectional view showing an example of a circuit. 1... Semiconductor substrate, 2... Diffusion region,
3... Interlayer insulating layer, 4... Wiring layer, 5
...Cover single layer, 6°8.9... Connection hole, 7... Bonding pad, 10...
・First wiring layer, 11...Second wiring layer, 12
・1...first interlayer insulating layer, 13...second
interlayer insulation layer.
Claims (1)
該ボンディングパッドは、その直下の半導体基板上に形
成された拡散領域と、該拡散領域の上部に形成された層
間絶縁層に設けられた接続孔によって接続されることを
特徴とする半導体集積回路。In a semiconductor integrated circuit having bonding pads,
A semiconductor integrated circuit characterized in that the bonding pad is connected to a diffusion region formed on a semiconductor substrate immediately below the bonding pad through a connection hole provided in an interlayer insulating layer formed above the diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62140222A JPS63304645A (en) | 1987-06-03 | 1987-06-03 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62140222A JPS63304645A (en) | 1987-06-03 | 1987-06-03 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63304645A true JPS63304645A (en) | 1988-12-12 |
Family
ID=15263748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62140222A Pending JPS63304645A (en) | 1987-06-03 | 1987-06-03 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63304645A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03136331A (en) * | 1989-10-23 | 1991-06-11 | Matsushita Electron Corp | Semiconductor device |
-
1987
- 1987-06-03 JP JP62140222A patent/JPS63304645A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03136331A (en) * | 1989-10-23 | 1991-06-11 | Matsushita Electron Corp | Semiconductor device |
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