JPH1041470A - Power supply device - Google Patents

Power supply device

Info

Publication number
JPH1041470A
JPH1041470A JP19681296A JP19681296A JPH1041470A JP H1041470 A JPH1041470 A JP H1041470A JP 19681296 A JP19681296 A JP 19681296A JP 19681296 A JP19681296 A JP 19681296A JP H1041470 A JPH1041470 A JP H1041470A
Authority
JP
Japan
Prior art keywords
film
thin
dielectric isolation
power system
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19681296A
Other languages
Japanese (ja)
Inventor
Tomoko Wakuta
智子 涌田
Kazuo Matsuzaki
一夫 松崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP19681296A priority Critical patent/JPH1041470A/en
Publication of JPH1041470A publication Critical patent/JPH1041470A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To make a power supply device small. SOLUTION: A control system semiconductor element 4 is formed on a surface layer of a semiconductor area 3 isolated by a dielectric isolation area 2 of a dielectric isolation substrate 1, and a power system element 6 is formed on a rear side 5 of the dielectric isolation substrate 1. The control system semiconductor element 4 and the power system element 6 are connected by a bonding wire 7. A power system element 9 which cannot be formed on the dielectric isolation substrate 1 is formed on, e.g. a dielectric isolation substrate 8 and connected to the control system semiconductor element 5 by a bump 10. The power system elements 6, 9 are thin film elements formed by using the thin film forming technology and passive elements such as coil or capacitors. Furthermore, the diameter of the bonding wire 7 is selected usually to be about 20μm and smaller than the thickness of the bump whose thickness is 50μm or over.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は半導体基板や絶縁
体基板等に形成される各種電子部品からなるDC−DC
コンバーダなどの電源装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC comprising various electronic parts formed on a semiconductor substrate, an insulator substrate or the like.
The present invention relates to a power supply device such as a converter.

【0002】[0002]

【従来の技術】従来の電源装置において、制御系半導体
素子と電力系素子の接続はバンプ技術を用いて行ってい
た。図4は従来の電源装置の要部構成図である。半導体
基板8の表面層に制御系半導体素子4を形成し、また例
えば2個の半導体基板8にそれぞれ電力系素子9を形成
する。制御系半導体素子4としては例えばMOSデバイ
スなどの能動素子であり、電力系素子9としてはコイ
ル、コンデンサなどの受動素子である。この制御系半導
体素子4および電力系素子9はバンプで接続されてい
る。尚、バンプは配線用のはんだの突起のことで、図示
されていないが、半導体基板8内にピンホールを掘って
金属を埋めて形成された配線でバンプと半導体基板8の
表面とは接続されている。
2. Description of the Related Art In a conventional power supply device, a connection between a control semiconductor element and a power element has been performed by using a bump technique. FIG. 4 is a main part configuration diagram of a conventional power supply device. The control system semiconductor element 4 is formed on the surface layer of the semiconductor substrate 8, and the power system element 9 is formed on each of the two semiconductor substrates 8, for example. The control system semiconductor element 4 is an active element such as a MOS device, for example, and the power system element 9 is a passive element such as a coil and a capacitor. The control system semiconductor element 4 and the power system element 9 are connected by bumps. The bumps are projections of solder for wiring and are not shown, but are formed by digging pinholes in the semiconductor substrate 8 and filling the metal, and the bumps are connected to the surface of the semiconductor substrate 8. ing.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来の電源装
置では、薄膜形成技術を用いて電力系素子の薄膜化を図
っているが、制御系半導体素子と電力系素子は別々の誘
電体分離基板などの基板に形成して、各素子をバンプ技
術を用いて接続していた。このバンプによる接続は、バ
ンプ自身に0.5mm程度の厚みがあるため、装置の小
型化が困難であった。
However, in the conventional power supply device, the power element is made thinner by using a thin film forming technique. However, the control semiconductor element and the power element are separated from each other by a dielectric isolation substrate. Such elements are connected to each other by using a bump technique. In connection by this bump, since the bump itself has a thickness of about 0.5 mm, it was difficult to reduce the size of the device.

【0004】この発明の目的は、前記の課題を解決し
て、小型の電源装置を提供することにある。
An object of the present invention is to solve the above-mentioned problems and to provide a compact power supply.

【0005】[0005]

【課題を解決するための手段】前記目的を達成するため
に、制御系半導体素子と電力系素子を有する電源装置に
おいて、誘電体分離基板の表面側に制御系半導体素子を
形成し、裏面側に薄膜の電力系素子を形成し、制御系半
導体素子と薄膜の電力系素子とがボンディングワイヤで
接続される構成とする。前記の薄膜の電力系素子が薄膜
コイル、積層型薄膜コンデンサもしくはトレンチ型薄膜
コンデンサのいずれかであるとよい。また、制御系半導
体素子と薄膜の電力系素子とをパッケージに形成された
導体薄膜を介してボンディングワイヤで接続されるとよ
い。
In order to achieve the above object, in a power supply device having a control system semiconductor element and a power system element, a control system semiconductor element is formed on a front surface side of a dielectric isolation substrate, and is formed on a back surface side. A thin film power system element is formed, and the control semiconductor element and the thin film power system element are connected by bonding wires. The thin-film power system element may be any one of a thin-film coil, a laminated thin-film capacitor, and a trench-type thin-film capacitor. Further, it is preferable that the control system semiconductor element and the thin-film power system element are connected by a bonding wire via a conductive thin film formed on a package.

【0006】従来のバンプ接続をボンディングワイヤ接
続に代えることで、厚みを低減し装置の小型化を図るこ
とができる。
By replacing the conventional bump connection with the bonding wire connection, the thickness can be reduced and the size of the device can be reduced.

【0007】[0007]

【発明の実施の形態】図1はこの発明の第1実施例の要
部構成図である。誘電体分離基板1の誘電体分離領域2
で分離された表面側の半導体領域3(この領域は図示さ
れている誘電体分離領域と図示されていない側面の誘電
体分離領域で囲まれている場合もある)の表面層に制御
系半導体素子4を形成し、誘電体分離基板1の裏面側の
面(裏面5)に電力系素子6を形成する。制御系半導体
素子4と電力系素子6をボンディングワイヤ7で接続す
る。この誘電体分離基板1に形成できない電力系素子9
を例えば半導体基板8上に形成し、制御系半導体素子4
とバンプ10により接続する。この電力系素子6、9は
薄膜形成技術を用いて形成された薄膜素子であり、その
構造を図2に示す。制御系半導体素子4としてはMOS
FETやIGBTなどのMOSデバイスやバイポーラト
ランジスタなどの能動素子である。また電力系素子6、
9はコイル、コンデンサなどの受動素子である。尚、誘
電体分離基板1の表面側および裏面側に制御系半導体素
子4と電力系素子6を形成することで個別の半導体基板
に形成するより厚みを半減できる。さらに、ボンディン
グワイヤ7の直径は50μmから100μm程度であ
り、そのため制御系半導体素子4上および電力系素子6
上に電気絶縁用の絶縁膜を1μm程度の厚さで形成し、
その上にボンディングワイヤ7を配線した場合、0.5
mm程度の高さがあるバンプで配線した場合より配線部
を薄くできる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a main part of a first embodiment of the present invention. Dielectric isolation region 2 of dielectric isolation substrate 1
A control semiconductor element is formed on the surface layer of the semiconductor region 3 on the front side (this region may be surrounded by a dielectric isolation region shown in the drawing and a dielectric isolation region on the side surface not shown in the figure). 4 is formed, and a power-related element 6 is formed on the back surface (back surface 5) of the dielectric isolation substrate 1. The control system semiconductor element 4 and the power system element 6 are connected by bonding wires 7. A power element 9 that cannot be formed on the dielectric isolation substrate 1
Is formed, for example, on a semiconductor substrate 8 and the control system semiconductor element 4
And the bump 10. The power system elements 6 and 9 are thin film elements formed by using a thin film forming technique, and the structure is shown in FIG. MOS is used as the control system semiconductor element 4
Active devices such as MOS devices such as FETs and IGBTs and bipolar transistors. Also, the power system element 6,
9 is a passive element such as a coil and a capacitor. In addition, by forming the control system semiconductor element 4 and the power system element 6 on the front surface side and the back surface side of the dielectric isolation substrate 1, the thickness can be reduced by half as compared with the case where the semiconductor element is formed on an individual semiconductor substrate. Further, the diameter of the bonding wire 7 is about 50 μm to 100 μm, so that the
An insulating film for electric insulation is formed on top with a thickness of about 1 μm,
When the bonding wire 7 is provided thereon, 0.5
The wiring portion can be made thinner than when wiring is performed with bumps having a height of about mm.

【0008】図2に薄膜素子の要部構造図を示し、同図
(a)は薄膜コイルの要部断面図、同図(b)は積層型
薄膜コンデンサの要部断面図、同図(c)はトレンチ型
薄膜コンデンサの要部断面図を示す。同図(a)におい
て、誘電体絶縁基板1の裏面側に絶縁膜21、磁性膜2
2、絶縁膜23コイルとなる導電膜24、絶縁膜25、
磁性膜26および絶縁膜27がそれぞれ積層されて薄膜
コイル11を形成する。尚、絶縁膜27は保護用であ
る。また、誘電体分離基板1の表面側の半導体領域の表
面層には制御系半導体素子4が形成される。同図(b)
において、誘電体分離基板1の裏面側に絶縁膜28、導
電膜29および絶縁膜30を積層して積層型薄膜コンデ
ンサ12を形成する。コンデンサの一方の電極は誘電体
分離基板1の裏面であり、他方の電極は導電膜29であ
る。尚、絶縁膜30は保護用である。同図(c)におい
て、誘電体分離基板1の裏面側の半導体領域32に溝3
1を形成し、この溝31の表面に絶縁膜33を形成し、
その絶縁膜33上に導電膜34を形成し、この導電膜3
4で溝31を埋め、表面を平坦に、導電膜34上に絶縁
膜35を形成する。この導電膜34と誘電体分離基板1
の裏面でコンデンサが形成される。このトレンチ型構造
とすることで小面積で大きな容量のコンデンサを形成す
ることができる。また絶縁膜35は保護用である。
FIG. 2 is a structural view of a principal part of a thin-film element. FIG. 2A is a sectional view of a principal part of a thin-film coil, FIG. 2B is a sectional view of a principal part of a multilayer thin-film capacitor, and FIG. () Shows a sectional view of a main part of the trench type thin film capacitor. In FIG. 1A, an insulating film 21 and a magnetic film 2 are formed on the back side of a dielectric insulating substrate 1.
2, insulating film 23, conductive film 24 serving as a coil, insulating film 25,
The magnetic film 26 and the insulating film 27 are respectively laminated to form the thin film coil 11. The insulating film 27 is for protection. Further, a control semiconductor element 4 is formed on a surface layer of the semiconductor region on the surface side of the dielectric isolation substrate 1. FIG.
In the above, the insulating film 28, the conductive film 29 and the insulating film 30 are laminated on the back side of the dielectric isolation substrate 1 to form the multilayer thin film capacitor 12. One electrode of the capacitor is the back surface of the dielectric isolation substrate 1, and the other electrode is a conductive film 29. Note that the insulating film 30 is for protection. In FIG. 1C, a groove 3 is formed in a semiconductor region 32 on the back surface of the dielectric isolation substrate 1.
1, an insulating film 33 is formed on the surface of the groove 31,
A conductive film 34 is formed on the insulating film 33 and the conductive film 3
4, the trench 31 is filled, the surface is flattened, and an insulating film 35 is formed on the conductive film 34. The conductive film 34 and the dielectric separation substrate 1
A capacitor is formed on the back surface of. With this trench type structure, a capacitor having a small area and a large capacity can be formed. The insulating film 35 is for protection.

【0009】図3はこの発明の第2実施例の要部構成図
である。図1との違いはパッケージ14に形成された図
示されていない導電膜と電力系素子6とが固着され、こ
の導電膜と制御系半導体素子4とがボンディングワイヤ
7で接続されている点である。
FIG. 3 is a block diagram of a main part of a second embodiment of the present invention. The difference from FIG. 1 is that a conductive film (not shown) formed on the package 14 and the power element 6 are fixed, and the conductive film and the control semiconductor element 4 are connected by bonding wires 7. .

【0010】[0010]

【発明の効果】この発明によれば、DC−DCコンバー
タなどの電源装置において、誘電体分離基板の裏面1薄
膜形成技術を用いて、薄膜コイルや薄膜コンデンサなど
の電力系素子を形成し、この電力系素子と誘電体分離基
板の表面に形成される制御系半導体素子とを細いボンデ
ィングワイヤで接続することで電源装置の厚みを低減
し、小型化を図る。
According to the present invention, in a power supply device such as a DC-DC converter, a power system element such as a thin film coil or a thin film capacitor is formed by using a thin film forming technique on the back surface of a dielectric separation substrate. By connecting the power system element and the control system semiconductor element formed on the surface of the dielectric isolation substrate with thin bonding wires, the thickness of the power supply device is reduced and the size of the power supply device is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1実施例の要部構成図FIG. 1 is a configuration diagram of a main part of a first embodiment of the present invention.

【図2】薄膜素子の要部構造図を示し、(a)は薄膜コ
イルの要部断面図、(b)は積層型薄膜コンデンサの要
部断面図、(c)はトレンチ型薄膜コンデンサの要部断
面図
FIGS. 2A and 2B are structural views of a principal part of a thin film element, FIG. 2A is a sectional view of a principal part of a thin film coil, FIG. 2B is a sectional view of a principal part of a multilayer thin film capacitor, and FIG. Partial sectional view

【図3】この発明の第2実施例の要部構成図FIG. 3 is a configuration diagram of a main part of a second embodiment of the present invention.

【図4】従来の電源装置の要部構成図FIG. 4 is a main part configuration diagram of a conventional power supply device.

【符号の説明】[Explanation of symbols]

1 誘電体分離基板 2 誘電体分離領域 3 半導体領域 4 制御系半導体領域 5 裏面 6 電力系素子 7 ボンディングワイヤ 8 半導体基板 9 電力系素子 10 バンプ 11 薄膜コイル 12 積層型薄膜コンデンサ 13 トレンチ型薄膜コンデンサ 14 パッケージ 21 絶縁膜 22 磁性膜 23 絶縁膜 24 導電膜 25 絶縁膜 26 磁性膜 27 絶縁膜 28 絶縁膜 29 導電膜 30 絶縁膜 31 溝 32 半導体領域 33 絶縁膜 34 導電膜 35 絶縁膜 DESCRIPTION OF SYMBOLS 1 Dielectric isolation substrate 2 Dielectric isolation region 3 Semiconductor region 4 Control system semiconductor region 5 Back surface 6 Power system element 7 Bonding wire 8 Semiconductor substrate 9 Power system element 10 Bump 11 Thin film coil 12 Stacked thin film capacitor 13 Trench thin film capacitor 14 Package 21 insulating film 22 magnetic film 23 insulating film 24 conductive film 25 insulating film 26 magnetic film 27 insulating film 28 insulating film 29 conductive film 30 insulating film 31 groove 32 semiconductor region 33 insulating film 34 conductive film 35 insulating film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】制御系半導体素子と電力系素子を有する電
源装置において、誘電体分離基板の表面側に制御系半導
体素子を形成し、裏面側に薄膜の電力系素子を形成し、
制御系半導体素子と薄膜の電力系素子とがボンディング
ワイヤで接続されることを特徴とする電源装置。
In a power supply device having a control system semiconductor element and a power system element, a control system semiconductor element is formed on a front surface side of a dielectric separation substrate, and a thin film power system element is formed on a back surface side.
A power supply device wherein a control system semiconductor element and a thin-film power system element are connected by a bonding wire.
【請求項2】薄膜の電力系素子が薄膜コイル、積層型薄
膜コンデンサもしくはトレンチ型薄膜コンデンサのいず
れかであることを特徴とする請求項1記載の電源装置。
2. The power supply device according to claim 1, wherein the thin-film power system element is one of a thin-film coil, a laminated thin-film capacitor and a trench-type thin-film capacitor.
【請求項3】制御系半導体素子と薄膜の電力系素子とを
パッケージに形成された導体薄膜を介してボンディング
ワイヤで接続されることを特徴とする請求項1記載の電
源装置。
3. The power supply device according to claim 1, wherein the control semiconductor element and the thin-film power element are connected by a bonding wire via a conductive thin film formed on the package.
JP19681296A 1996-07-26 1996-07-26 Power supply device Pending JPH1041470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19681296A JPH1041470A (en) 1996-07-26 1996-07-26 Power supply device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19681296A JPH1041470A (en) 1996-07-26 1996-07-26 Power supply device

Publications (1)

Publication Number Publication Date
JPH1041470A true JPH1041470A (en) 1998-02-13

Family

ID=16364074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19681296A Pending JPH1041470A (en) 1996-07-26 1996-07-26 Power supply device

Country Status (1)

Country Link
JP (1) JPH1041470A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007318954A (en) * 2006-05-29 2007-12-06 Fuji Electric Device Technology Co Ltd Micro dc-dc converter module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007318954A (en) * 2006-05-29 2007-12-06 Fuji Electric Device Technology Co Ltd Micro dc-dc converter module

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