JPH0636592Y2 - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0636592Y2 JPH0636592Y2 JP1988136213U JP13621388U JPH0636592Y2 JP H0636592 Y2 JPH0636592 Y2 JP H0636592Y2 JP 1988136213 U JP1988136213 U JP 1988136213U JP 13621388 U JP13621388 U JP 13621388U JP H0636592 Y2 JPH0636592 Y2 JP H0636592Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- signal
- conductor
- small
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
【考案の詳細な説明】 （イ）産業上の利用分野 本考案は混成集積回路に関し、特に同一基板上に大信号
系、小信号系の半導体素子が固着された混成集積回路に
関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit in which large-signal type and small-signal type semiconductor elements are fixed on the same substrate.
（ロ）従来の技術 従来混成集積回路に複数の発熱を有する大信号系の半導
体素子と発熱を有さない複数の小信号系の半導体素子と
を集積化する場合には通常大信号系の半導体素子の発熱
を考慮して夫々異った基板上に大信号系の半導体素子と
小信号系の半導体素子とを区別して混成集積回路として
いた。(B) Conventional technology When integrating a large signal semiconductor element having a plurality of heat generations and a plurality of small signal semiconductor elements having no heat generation in a conventional hybrid integrated circuit, a large signal semiconductor is usually used. Considering the heat generation of the element, a large signal type semiconductor element and a small signal type semiconductor element are distinguished on different substrates to form a hybrid integrated circuit.
第３図はその代表例であり、アルミニウム基板等の一方
の混成集積回路基板（11）上に発熱を有する大信号系の
半導体素子（13）が、他方の混成集積回路基板（12）上
に発熱しない小信号系の半導体素子（14）が固着され、
ケース材（15）で一体化されている。FIG. 3 is a typical example thereof, in which a large-signal type semiconductor element (13) having heat is formed on one hybrid integrated circuit substrate (11) such as an aluminum substrate and the other hybrid integrated circuit substrate (12). The small-signal type semiconductor element (14) that does not generate heat is fixed,
It is integrated with the case material (15).
斯る混成集積回路では大、小信号系用の二枚の基板を必
要とするためのコスト高となる問題点があった。また夫
々の基板上に形成された導体を接続するために作業工程
数増となる問題点があった。In such a hybrid integrated circuit, there is a problem that the cost is high because two substrates for large and small signal systems are required. Further, there is a problem that the number of working steps is increased because the conductors formed on the respective substrates are connected.
（ハ）考案が解決しようとする課題 斯る問題点を解決するために第４図に示す如く、同一基
板（21）上に大、小信号系の夫々の半導体素子を実装す
ることで解決した。(C) Problems to be Solved by the Invention In order to solve such problems, as shown in FIG. 4, the problems were solved by mounting large and small signal semiconductor devices on the same substrate (21). .
しかしながら、同一基板上に発熱を有する大信号系の半
導体素子（22）と発熱しない小信号系の半導体素子とを
実装配置すると、高密度実装となり、パターン配線が制
約され、特に大信号系の導体ライン幅が制約され幅細の
導体となり、導体ライン抵抗値が高くなり電流容量の低
下から混成集積回路自体が発熱する問題点があった。第
４図において斜線領域部分は小信号系の回路が形成され
る。However, when a large-signal semiconductor element (22) that generates heat and a small-signal semiconductor element that does not generate heat are mounted and arranged on the same substrate, high-density mounting is achieved, and pattern wiring is restricted. There is a problem in that the hybrid integrated circuit itself generates heat due to the conductor width being restricted and the conductor width being narrow, the conductor line resistance being high and the current capacity being low. In FIG. 4, a small signal circuit is formed in the shaded area.
（ニ）課題を解決するための手段 本考案は上述した課題に鑑みて為されたものであり、発
熱を有する複数の大信号系の半導体素子と発熱を有しな
い複数の小信号系の半導体素子とが同一絶縁基板上に固
着された混成集積回路において、前記複数の小信号系の
半導体素子は絶縁基板を介して固着して解決する。(D) Means for Solving the Problems The present invention has been made in view of the above problems, and includes a plurality of large-signal semiconductor elements that generate heat and a plurality of small-signal semiconductor elements that do not generate heat. In the hybrid integrated circuit in which and are fixed on the same insulating substrate, the plurality of small-signal semiconductor elements are fixed via the insulating substrate to solve the problem.
（ホ）作用 この様に本考案に依れば発熱を有さない小信号系の半導
体素子のみを絶縁基板を介して前記金属基板上に固着す
ることにより、絶縁金属基板上に小信号系の半導体素子
が固着されずスペース空間が広くなり、大信号系の半導
体素子が固着される導体幅を大きく設定することができ
る。(E) Action As described above, according to the present invention, by fixing only the small-signal type semiconductor element that does not generate heat onto the metal substrate via the insulating substrate, the small-signal type semiconductor device can be formed on the insulating metal substrate. Since the semiconductor element is not fixed and the space space is widened, the conductor width to which the large signal semiconductor element is fixed can be set large.
（ヘ）実施例 以下に第１図及び第２図に示した実施例に基づいて本考
案を詳細に説明する。(F) Embodiments The present invention will be described in detail below based on the embodiments shown in FIGS. 1 and 2.
本考案の混成集積回路は第１図に示す如く、絶縁金属基
板（１）と、絶縁金属基板（１）上に固着される大信号
系の半導体素子（２）と、絶縁金属基板（１）上に固着
された絶縁基板（３）と、絶縁基板（３）上に固着され
た小信号系の半導体素子（４）とから構成される。As shown in FIG. 1, the hybrid integrated circuit of the present invention includes an insulating metal substrate (1), a large signal semiconductor element (2) fixed on the insulating metal substrate (1), and an insulating metal substrate (1). It is composed of an insulating substrate (3) fixed on the upper side and a small signal system semiconductor element (4) fixed on the insulating substrate (3).
絶縁金属基板（１）はアルミニウム基板が用いられ、絶
縁とするためにその表面には酸化アルミニウム膜が形成
されている。絶縁金属基板（１）の一主面にはエポキシ
樹脂等の絶縁性接着剤を介して所望膜厚の銅箔が貼着さ
れ、その銅箔が所望形状にエッチングされ導体（５）が
形成される。この導体（５）には発熱を有する大信号系
の半導体素子（２）が固着されるため導体（５）パター
ンの幅は熱の発生をおさえるために十分に広く形成され
ている。ここで絶縁金属基板（１）はアルミニウム基板
を用いたが、特に限定されるものではなく、鉄基板、ケ
イ素鋼板等の基板を使用することも可能である。An aluminum substrate is used as the insulating metal substrate (1), and an aluminum oxide film is formed on its surface for insulation. A copper foil having a desired film thickness is attached to one main surface of the insulating metal substrate (1) via an insulating adhesive such as an epoxy resin, and the copper foil is etched into a desired shape to form a conductor (5). It Since the large-signal type semiconductor element (2) having heat generation is fixed to the conductor (5), the width of the conductor (5) pattern is formed sufficiently wide to suppress heat generation. Here, the insulating metal substrate (1) is an aluminum substrate, but it is not particularly limited, and a substrate such as an iron substrate or a silicon steel plate can also be used.
絶縁金属基板（１）上に形成された導体（５）上にパワ
ートランジスタ等の発熱を有する大信号系の半導体素子
（２）が銅片（６）を介して所定の接着剤によって固着
され、近傍の導体（５）とワイヤで接続されている。ま
た、絶縁金属基板（１）上の導体（５）間はパワー用の
ニッケルメッキ抵抗体が所定位置に形成されている。即
ち、絶縁金属基板（１）上には発熱を有するもののみが
実装される。A large signal semiconductor element (2) having heat generation such as a power transistor is fixed on a conductor (5) formed on an insulating metal substrate (1) with a predetermined adhesive via a copper piece (6), It is connected to a nearby conductor (5) by a wire. Further, a nickel-plated resistor for power is formed at a predetermined position between the conductors (5) on the insulating metal substrate (1). That is, only those which generate heat are mounted on the insulating metal substrate (1).
絶縁基板（３）はセラミック、ガラエポ、絶縁処理され
た金属等の種々の基板を使用することができ、ここでは
絶縁処理された金属基板を用いるものとする。この金属
基板は絶縁金属基板（１）と同様のものであり、説明は
省略する。絶縁基板（３）上には銅箔により、所望形状
の導体（７）が形成されている。この導体（７）には発
熱を有さない小信号系のトランジスタ等の半導体素子
（４）、チップ抵抗及びチップコンデンサー等の電子部
品（５）が所望の接着剤によって固着されている。ま
た、Niメッキ抵抗体及びカーボン抵抗体等からなる抵抗
体も形成されている。即ち、絶縁基板（３）上には発熱
を有さないもののみが固着あるいは実装される。As the insulating substrate (3), various substrates such as ceramic, glass epoxy, and metal subjected to insulation treatment can be used, and here, the metal substrate subjected to insulation treatment is used. This metal substrate is the same as the insulating metal substrate (1), and its explanation is omitted. A conductor (7) having a desired shape is formed of copper foil on the insulating substrate (3). A semiconductor element (4) such as a small signal transistor which does not generate heat, an electronic component (5) such as a chip resistor and a chip capacitor, etc. are fixed to the conductor (7) by a desired adhesive. In addition, a resistor including a Ni-plated resistor and a carbon resistor is also formed. That is, only those that do not generate heat are fixed or mounted on the insulating substrate (3).
発熱を有さないもののみが実装された絶縁基板（３）は
絶縁金属基板（１）上の導体（５）パターン上にシリコ
ン系の絶縁性接着剤（８）によって接着一体化される。
絶縁基板（３）と絶縁金属基板（１）との絶縁は絶縁性
接着剤（８）によって十分に絶縁されるが、更に絶縁性
を考慮する場合には絶縁金属基板（１）上の導体（５）
パターン上に樹脂膜をコートしておけばよい。絶縁基板
（３）と絶縁金属基板（１）とを接着一体化した後、大
信号系用の導体（５）と小信号系の導体（７）とがワイ
ヤで接続される。The insulating substrate (3) on which only one that does not generate heat is mounted is bonded and integrated with the conductor (5) pattern on the insulating metal substrate (1) by a silicon-based insulating adhesive (8).
Insulation between the insulating substrate (3) and the insulating metal substrate (1) is sufficiently insulated by the insulating adhesive (8), but in the case of further considering the insulating property, the conductor (on the insulating metal substrate (1) ( 5)
A resin film may be coated on the pattern. After the insulating substrate (3) and the insulating metal substrate (1) are bonded and integrated, the conductor for large signal system (5) and the conductor for small signal system (7) are connected by wires.
斯る本考案に依れば、発熱を有さない小信号系の半導体
素子のみを絶縁基板上に実装し、絶縁金属基板上に固着
一体化することにより、絶縁金属基板上には大信号系の
半導体素子のみが固着されるので、大信号系用の導体幅
を広く設定することができライン抵抗を小さく設定する
ことが可能となり電流容量が大となる。According to the present invention, by mounting only the small-signal type semiconductor element that does not generate heat on the insulating substrate and fixing and integrating the same on the insulating metal substrate, the large-signal type is formed on the insulating metal substrate. Since only the semiconductor element of (3) is fixed, the conductor width for a large signal system can be set wide, and the line resistance can be set small, resulting in a large current capacity.
（ト）考案の効果 以上に詳述した如く、本考案に依れば、小信号系の半導
体素子のみを絶縁基板上に実装し、大信号系の半導体素
子が実装された絶縁金属基板上に固着することにより、
一枚基板で大電流（大信号系）と小信号系の回路を高密
度に実装することができ、低コスト、軽薄短小化の混成
集積回路を提供することができる。(G) Effect of the Invention As described in detail above, according to the present invention, only the small signal type semiconductor element is mounted on the insulating substrate, and the large signal type semiconductor element is mounted on the insulating metal substrate. By sticking,
It is possible to mount a high-current (large-signal system) and a small-signal system on a single substrate with high density, and it is possible to provide a hybrid integrated circuit that is low in cost, light, thin, and short.
第１図は本考案の実施例を示す断面図、第２図は第１図
の平面図、第３図及び第４図は従来例を示す図である。 （１）……絶縁金属基板、（２）……大信号系半導体素
子、（３）……絶縁基板、（４）……小信号系半導体素
子、（５）（７）……導体。FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1, and FIGS. 3 and 4 are views showing a conventional example. (1) ... Insulating metal substrate, (2) ... Large signal semiconductor device, (3) ... Insulating substrate, (4) ... Small signal semiconductor device, (5) (7) ... Conductor.
Claims (1)
号系の半導体素子とが少なくとも表面が絶縁性を有する
第１の基板上に固着された混成集積回路装置において、 前記第１の基板上には、この第１の基板と絶縁固着され
少なくとも表面が絶縁性を有する第２の基板が設けら
れ、前記第１の基板には前記大信号系の半導体素子およ
びこれらを接続し、一部が前記第２基板の下層に延在さ
れる大信号系の導体が設けられ、前記第２の基板には前
記小信号系の半導体素子およびこれらを接続する小信号
系の導体が設けられ、前記大信号系の導体と前記小信号
系の導体が金属細線にて接続されることを特徴とした混
成集積回路装置。1. A hybrid integrated circuit device in which a plurality of large-signal semiconductor elements and a plurality of small-signal semiconductor elements are fixed on a first substrate having an insulating property at least on the surface thereof. A second substrate is provided on the substrate, which is fixedly insulated from the first substrate and has at least a surface having an insulating property. The large signal semiconductor device and the second substrate are connected to the first substrate. A large signal system conductor whose part extends to a lower layer of the second substrate is provided, and the second signal substrate is provided with the small signal system semiconductor element and a small signal system conductor connecting them. A hybrid integrated circuit device characterized in that the conductor for the large signal system and the conductor for the small signal system are connected by a thin metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988136213U JPH0636592Y2 (en) | 1988-10-19 | 1988-10-19 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988136213U JPH0636592Y2 (en) | 1988-10-19 | 1988-10-19 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0256460U JPH0256460U (en) | 1990-04-24 |
| JPH0636592Y2 true JPH0636592Y2 (en) | 1994-09-21 |
Family
ID=31396510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988136213U Expired - Lifetime JPH0636592Y2 (en) | 1988-10-19 | 1988-10-19 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0636592Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6063622B2 (en) * | 2011-11-24 | 2017-01-18 | 株式会社ケーヒン | Electronic control unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6241594U (en) * | 1985-04-26 | 1987-03-12 |
-
1988
- 1988-10-19 JP JP1988136213U patent/JPH0636592Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0256460U (en) | 1990-04-24 |
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