JPH04114452A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH04114452A JPH04114452A JP2235212A JP23521290A JPH04114452A JP H04114452 A JPH04114452 A JP H04114452A JP 2235212 A JP2235212 A JP 2235212A JP 23521290 A JP23521290 A JP 23521290A JP H04114452 A JPH04114452 A JP H04114452A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- thin film
- metal
- film
- ceramic thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000010409 thin film Substances 0.000 claims abstract description 32
- 239000010408 film Substances 0.000 claims abstract description 28
- 239000000919 ceramic Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000853 adhesive Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- 229910052802 copper Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、動作に大電流を要し、また、発熱量も多い半
導体素子を搭載する配線基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring board on which a semiconductor element that requires a large current to operate and generates a large amount of heat is mounted.
首記の用途に利用される従来の配線基板としては、第３
図に示すように、焼結セラミック基材１上に金属ペース
トを印刷焼成して配線２を形成した厚膜配線基板や、第
４図に示すように、金属基材５上に樹脂絶縁層６を塗布
形成後、接着剤７を使って銅箔をつけ、その後エツチン
グにより配線２を形成した金属ベース基板がある。なお
、第３図、第４図の３は半導体素子、４はポンディング
ワイヤである。As a conventional wiring board used for the above purpose, the third
As shown in the figure, there is a thick film wiring board in which wiring 2 is formed by printing and firing a metal paste on a sintered ceramic base material 1, and as shown in FIG. There is a metal base substrate in which wiring 2 is formed by coating and forming, then attaching copper foil using adhesive 7, and then forming wiring 2 by etching. Note that 3 in FIGS. 3 and 4 is a semiconductor element, and 4 is a bonding wire.
従来のこの種の配線基板は、配線のシート抵抗が高い、
半導体素子及び配線からの熱放散性が悪いという欠点が
あった。Conventional wiring boards of this type have high wiring sheet resistance,
There was a drawback that heat dissipation from the semiconductor element and wiring was poor.
厚膜配線基板は、配線にＡｇ−ＰｄもしくはＡＵペース
トを印刷焼成したものを用いるため、シート抵抗は２−
３０ｍΩ／口と非常に大きい、また、基材は通常アルミ
ナ焼結体を用いるが、アルミナ焼結体は熱伝導率が小さ
く （７Ｘ１０”’ ｋｃａｌ／■・Ｓ・℃）熱放散性
が悪い。Thick film wiring boards use printed and fired Ag-Pd or AU paste for the wiring, so the sheet resistance is 2-
It is extremely large at 30 mΩ/port, and the base material is usually an alumina sintered body, but the alumina sintered body has a low thermal conductivity (7×10'' kcal/■・S・℃) and poor heat dissipation.
金属ベース基板は、配線に銅箔を用いているが、その厚
みは通常３５μ程度であり、シート抵抗は０．５ｍΩ／
口と大きい。また、金属基材は熱伝導率が大きいものの
、樹脂絶縁層は熱伝導率が小さく （フィラー人樹脂０
．４Ｘ Ｉ ０−６ｋｃａｌ ／ｇｏ −ｓ−’ｃ、フ
ィラー無樹脂０．０４ Ｘ １０−’ ｋｃａｌ ７ｍ
ｍ・Ｓ・’Ｃ）基板全体の熱放散性は悪くなっている。The metal base board uses copper foil for wiring, and its thickness is usually about 35μ, and the sheet resistance is 0.5mΩ/
Mouth and big. In addition, although the metal base material has a high thermal conductivity, the resin insulation layer has a low thermal conductivity (filler resin 0
．． 4X I 0-6kcal/go-s-'c, filler-free resin 0.04 X 10-'kcal 7m
m・S・'C) The heat dissipation of the entire board is poor.
このような課題が残されていると電子製品の動作性能や
耐久性に問題が生しる。If these issues remain, problems will arise in the operating performance and durability of electronic products.
このため、現在は、動作に大電流を要するパワーＭＯＳ
ＦＥＴ等の配線基板としては、シート抵抗０．２ｍΩ／
口以下、基板の熱伝導率４０Ｘ１０−’ ｋｃａｌ ／
閣・Ｓ・℃以上のものが要求されている。For this reason, power MOS devices that require large currents to operate are currently used.
For wiring boards such as FET, the sheet resistance is 0.2mΩ/
The thermal conductivity of the substrate is 40X10-'kcal/
Kaku・S・℃ or higher is required.
本発明は、かかる要求に応えた基板を提供しようとする
ものである。The present invention aims to provide a substrate that meets such demands.
本発明の配線基板は、上記の８８を解決するため、金属
基材の素子搭載側の表面にセラミック薄膜をコーティン
グし、半導体素子搭載部の周辺部には樹脂フィルムに保
持された低シート抵抗の配線金属を、金属側を接着剤で
セラミック薄膜上に接着して設け、さらに上記配線金属
の一部を樹脂フィルムの側縁から結線の可能な幅をもっ
て側方に突出させる構成を採用する。In order to solve the problem 88 above, the wiring board of the present invention has a ceramic thin film coated on the element mounting side surface of the metal base material, and a low sheet resistance film held in a resin film around the semiconductor element mounting area. A configuration is adopted in which the metal wiring is provided by bonding the metal side onto the ceramic thin film with an adhesive, and further, a part of the wiring metal protrudes laterally from the side edge of the resin film with a width that allows connection.
この基板は、セラミック薄膜上に半導体素子を直接搭載
するか又は、半導体素子搭載部のセラミック薄膜上に金
属薄膜を設けてその上に素子を搭載する。In this substrate, a semiconductor element is directly mounted on the ceramic thin film, or a metal thin film is provided on the ceramic thin film of the semiconductor element mounting portion, and the element is mounted thereon.
〔作用］
かかる基板は、配線金属のシート抵抗が小さいため大電
流が流せる。また半導体素子及び配線は熱伝導率の大き
い金属基材上にセラミック薄膜を介して搭載されるが、
セラミックｍ１ｌｌは非常に薄くかつ熱伝導率も樹脂に
比べ比較的高い（Ａ１．０薄膜７ＸＸ１０−” ｋｃａ
ｌ ７ｍ−ｓ ・’Ｃ）ため、良好な熱放散性を保つ。[Function] Such a board allows a large current to flow because the sheet resistance of the wiring metal is small. Furthermore, semiconductor elements and wiring are mounted on a metal base material with high thermal conductivity via a ceramic thin film.
Ceramic ml is very thin and has relatively high thermal conductivity compared to resin (A1.0 thin film 7XX10-”kca
l 7m-s ・'C), thus maintaining good heat dissipation.
また、セラミック薄膜上に金属薄膜を形成したものはそ
の金属薄膜と樹脂フィルムに保持された配線との間をワ
イヤーボンディング等で接続することによって、半導体
裏面の電位を変え、複数の半導体素子を搭載することが
可能になる。In addition, when a metal thin film is formed on a ceramic thin film, the electric potential on the back side of the semiconductor can be changed by connecting the metal thin film and the wiring held in the resin film with wire bonding, etc., and multiple semiconductor elements can be mounted. It becomes possible to do so.
（実施例〕
第１図は本発明の一興体例である。熱伝導率４０ＸＩ
Ｏ−’ ｋｃａｌ ７ｍ−ｓ ・”Ｃ以上の金属基材５
上に、セラミック薄膜９を全面にコーティングし、半導
体素子搭載部のセラミック薄膜上にＡｕ、ＡＩ、Ｃｕ等
の金属Ｆｉ膜１０を形成しである。また、シート抵抗が
０．２ｍΩ／口以下となる厚みを持った安価で比抵抗の
小さい材料、例えばＡＩ、Ｃｕを樹脂フィルム８で保持
した後エツチングによって配＆ｌ１２を形成したものを
コーテイング面側に配線金属を位置させて接着剤７によ
り接合しである。(Example) Fig. 1 shows an example of the present invention.Thermal conductivity 40XI
O-'kcal 7m-s ・Metal base material 5 of "C or higher"
A ceramic thin film 9 is coated on the entire surface, and a metal Fi film 10 of Au, AI, Cu, etc. is formed on the ceramic thin film in the semiconductor element mounting area. In addition, a material having a thickness such that the sheet resistance is 0.2 mΩ or less and having a low specific resistance, such as AI or Cu, is held in a resin film 8 and then etched to form a pattern 12 on the coating surface side. The wiring metal is positioned and bonded with adhesive 7.
半導体素子搭載部分には予め配線、樹脂フィルムを配置
せず、フィル７．８の周縁部には配線２が露出する構造
にしておく。そしてセラミック蒲Ｗｌ！Ｂ上に形成した
金属薄Ｗ！１１０と樹脂フィルムに保持された配線２と
の間をボンディングワイヤ４等で接続し、配線基板を形
成する。No wiring or resin film is placed in advance on the semiconductor element mounting portion, and the wiring 2 is exposed at the peripheral edge of the fill 7.8. And ceramic bowl Wl! Metal thin W formed on B! 110 and the wiring 2 held by the resin film are connected using bonding wires 4 or the like to form a wiring board.
第２図は本発明の他の具体例であり、半導体素子裏面に
！極が必要でない場合である。この場合はセラミック薄
膜上に金属薄膜を形成しなければよい。この場合、半導
体素子３はセラミンク薄膜Ｓ上に搭載する。FIG. 2 shows another specific example of the present invention. This is the case when poles are not required. In this case, the metal thin film may not be formed on the ceramic thin film. In this case, the semiconductor element 3 is mounted on the ceramic thin film S.
以下に、より詳細な実施例を挙げる。More detailed examples are given below.
（実 験］） 第１図の構造の配線基板を以下の構成で作成した。(experiment]) A wiring board having the structure shown in FIG. 1 was created with the following configuration.
金属基材５−Ｃｕ（ｔ２ｍ）、
接着剤７−ポリイミド系接着剤、
樹脂フィルム８−ポリイミドフィルム（ｔ７５４）配ｖ
Ａ２−Ｃｕ （”１．００ｎ）、
セラミック薄膜５−Ａ１ｚｏｓ＊膜（ＪＯｍ）、金属薄
膜１Ｑ−ＡＩ （ｔ５趨）、
結果・・・・・・配線Ｃｕのシート抵抗を測定したとこ
ろ０．１８ｍΩ／口前後の値が得られた。また５０Ｑｐ
ｍ幅の配線を形成し、ＩＯＡの電流を流すことが可能に
なった。Metal base material 5 - Cu (t2m), adhesive 7 - polyimide adhesive, resin film 8 - polyimide film (t754) arrangement
A2-Cu ("1.00n), ceramic thin film 5-A1zos* film (JOm), metal thin film 1Q-AI (t5 trend), Result: The sheet resistance of the wiring Cu was measured and was 0.18 mΩ Values around /mouth were obtained.Also, 50Qp
It became possible to form a wiring with a width of m and to flow an IOA current.
（実 験２） 第１図の構造の配線基板を以下の構成で作成した。(Experiment 2) A wiring board having the structure shown in FIG. 1 was created with the following configuration.
金属基材５−Ｃｕ（Ｌ２ｍ）、
接着剤？−エポキシ系接着剤、
樹脂フィルム８−ポリイミドフィルム（’７５７１１１
）配’１Ａ２−Ｃｕ （Ｊ ＯＯｍ）、
セラミック薄膜９ ＡｌｚＯ：＋Ｆｌ膜（ＪＯｕ）、
金属薄膜ＩＱ−Ｃｕ （’５ｍ）、
結果・・・・・・実験（１）と同じ特性が得られた。Metal base material 5-Cu (L2m), adhesive? - Epoxy adhesive, resin film 8 - Polyimide film ('757111
)1A2-Cu (JOOm), Ceramic thin film 9 AlzO:+Fl film (JOu),
Metal thin film IQ-Cu ('5m) Results: Same characteristics as in experiment (1) were obtained.
（実 験３）
基板の熱放散性について、基板の熱抵抗をシュミレーシ
ョンによって調査した。基板をを第５図のようにモデル
化し、基材の部分がＡ１□Ｏ１（厚膜配線基板の場合に
対応）、フィラー大エポキシ樹脂絶縁層＋Ａ１．（金属
ベース基板に対応）、ＡＩ！０３薄膜＋ＡＩ（本発明に
対応）のそれぞれの場合について計算を行った。結果を
下表に示す。(Experiment 3) Regarding the heat dissipation properties of the substrate, the thermal resistance of the substrate was investigated by simulation. The board is modeled as shown in Fig. 5, and the base material part is A1□O1 (corresponding to the case of thick film wiring board), filler large epoxy resin insulating layer + A1. (Compatible with metal-based substrates), AI! Calculations were performed for each case of 03 thin film + AI (corresponding to the present invention). The results are shown in the table below.
これから判るように本発明の構造は熱放散性に非常に優
れたものとなっている。As can be seen, the structure of the present invention has excellent heat dissipation properties.
〔効果］
以上説明したように、本発明の基板はシート抵抗が低く
熱放散性に優れているため、動作に大電流を要しかつ発
熱量の多い半導体素子を搭載する配線基板として利用す
ると効果的である。[Effects] As explained above, the substrate of the present invention has low sheet resistance and excellent heat dissipation, so it is effective when used as a wiring board on which semiconductor elements that require large currents to operate and generate a large amount of heat are mounted. It is true.
第１図及び第２図は、本発明の配線基板の一実施例を示
す断面図、第３図は厚膜配線基板の断面図、第４図は金
属ベース基板の断面図、第５図（ａ）、Ｃｂ）は熱抵抗
の調査に用いたモデル基板の斜視図と側面図である。
２・・・・・・配線、 ３・・・・・・半導体素
子、４・・・・・・ボンディングワイヤ、
５・・・・・・金属基材、 ７・・・・・・接着剤、
８・・・・・・樹脂フィルム、９・・・・・・セラミッ
ク薄膜、１０・・・・・・金ＩＥｆｌ膜。
第４図
（ａ）
第５図
（ｂ）
理想放熱1 and 2 are cross-sectional views showing one embodiment of the wiring board of the present invention, FIG. 3 is a cross-sectional view of a thick film wiring board, FIG. 4 is a cross-sectional view of a metal base substrate, and FIG. a) and Cb) are a perspective view and a side view of a model board used for investigating thermal resistance. 2... Wiring, 3... Semiconductor element, 4... Bonding wire, 5... Metal base material, 7... Adhesive,
8... Resin film, 9... Ceramic thin film, 10... Gold IEfl film. Figure 4 (a) Figure 5 (b) Ideal heat radiation
Claims (2)
コーティングし、半導体素子搭載部の周辺部には樹脂フ
ィルムに保持された低シート抵抗の配線金属を、金属側
を接着剤でセラミック薄膜上に接着して設け、さらに上
記配線金属の一部を樹脂フィルムの側縁から結線の可能
な幅をもって側方に突出させてある配線基板。(1) A ceramic thin film is coated on the element mounting side surface of the metal base material, a low sheet resistance wiring metal held in a resin film is coated around the semiconductor element mounting area, and a ceramic thin film is coated on the metal side with an adhesive. A wiring board in which a part of the wiring metal is bonded onto the resin film and further has a part of the wiring metal protruding laterally from the side edge of the resin film with a width that allows wire connection.
けるセラミック薄膜上に、金属薄膜を設けてある配線基
板。(2) A wiring board in which a metal thin film is provided on the ceramic thin film in the semiconductor element mounting portion of the board according to claim (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2235212A JPH04114452A (en) | 1990-09-04 | 1990-09-04 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2235212A JPH04114452A (en) | 1990-09-04 | 1990-09-04 | Wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04114452A true JPH04114452A (en) | 1992-04-15 |
Family
ID=16982744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2235212A Pending JPH04114452A (en) | 1990-09-04 | 1990-09-04 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04114452A (en) |
-
1990
- 1990-09-04 JP JP2235212A patent/JPH04114452A/en active Pending
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