JPS5853854A - High integration density lsi package - Google Patents
High integration density lsi packageInfo
- Publication number
- JPS5853854A JPS5853854A JP15172981A JP15172981A JPS5853854A JP S5853854 A JPS5853854 A JP S5853854A JP 15172981 A JP15172981 A JP 15172981A JP 15172981 A JP15172981 A JP 15172981A JP S5853854 A JPS5853854 A JP S5853854A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- wiring board
- chip
- density
- lsi package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は高密度ＬＳＩパッケージに関する。[Detailed description of the invention] The present invention relates to high-density LSI packages.
一般に、高密度ＬＳＩパッケージは、（１）ＩＣ実装部
、（２）外部接続部、（３）放熱部とを多層配線基板上
に設けて構成されている。Generally, a high-density LSI package is constructed by providing (1) an IC mounting section, (2) an external connection section, and (3) a heat dissipation section on a multilayer wiring board.
ここで、多層配線基板としては、セラｔｙり多層配線基
板や、金属ベース多層配線基板や、ガラスセラミック積
層配線基板が用いられる。Here, as the multilayer wiring board, a ceramic multilayer wiring board, a metal-based multilayer wiring board, or a glass ceramic laminated wiring board is used.
セラミック多層配線基板は、セラミ、り基板の表層に無
機又は有機の絶縁材と導電材とを用いて形成され大多層
配線層をもつ配線基板であシ、金属ペース多層配線基板
は金属板を絶縁材で被覆し。A ceramic multilayer wiring board is a wiring board with a large number of wiring layers formed using an inorganic or organic insulating material and a conductive material on the surface layer of a ceramic board, and a metal-based multilayer wiring board is a wiring board with an insulating metal plate. covered with wood.
その表層に絶縁材と導電材とを用いて形成された多層配
線層をもつ配線基板であり、ガラスセラミック積層配線
基板は表面に配線パターンの形成されたガラス板又はセ
ラ電ツク板を複数枚積層する事によって多層化を達成し
た配線基板である。It is a wiring board that has a multilayer wiring layer formed using an insulating material and a conductive material on its surface layer, and a glass ceramic laminated wiring board is a wiring board that is made by laminating multiple glass plates or ceramic electrical boards with wiring patterns formed on the surface. This is a wiring board that achieves multilayer structure by doing this.
従来の高密［ＬＳＩパ、ケージは、多層配線基板のＩＣ
搭載面ＫＩ（：！ｌ！装部を設け、このＩＣ搭載面と対
向する対向面に外部接続部および放熱部の一方を設け、
他方を、［［、Ｃ搭載面と対向面とのいずれかの面に設
けて構成される。Conventional high-density [LSI packages and cages are ICs with multilayer wiring boards]
A mounting surface KI (:!l! mounting section is provided, and one of an external connection section and a heat dissipation section is provided on the opposite surface facing this IC mounting surface,
The other is provided on either the [[, C mounting surface or the opposing surface.
以下に、従来の高密度Ｌ８１バ、ケージの例について、
図面を参照して説明する。Below, examples of conventional high-density L81 bars and cages are shown.
This will be explained with reference to the drawings.
ａｔ図−第４図はいずれも従来の高密度Ｌ８Ｉパッケー
ジの第１〜第４の例を示す側断図である。FIG. 4 is a side sectional view showing first to fourth examples of the conventional high-density L8I package.
第１図に示、す高密度ＬＳＩパッケージは、ＩＣ実装部
と外部接続部とを同一平面に配置し、放熱部を対向面に
配置したものであ夛、第２図および第３図に示す高密度
ＬＳＩパッケージは、ＩＣ実装部と放熱部とを同一平面
に配置し、外部接続部を対向面に配置したものである。The high-density LSI package shown in Fig. 1 has the IC mounting part and the external connection part arranged on the same plane, and the heat dissipation part arranged on the opposite surface, as shown in Figs. 2 and 3. A high-density LSI package has an IC mounting section and a heat dissipation section arranged on the same plane, and an external connection section arranged on the opposite surface.
また、第４図に示す高密度ＬＳＩパッケージは、外部接
続部と放熱部とを同一平面に配置し、ＩＣ実装部を対向
面に配置したものマ゛′ある。Furthermore, the high-density LSI package shown in FIG. 4 has an external connection section and a heat dissipation section disposed on the same plane, and an IC mounting section disposed on the opposite surface.
第１図に示す高密度ＬＳＩパッケージは、ＩＣ実装部と
外部接続部が同一平面にあるため、搭載ＩＣ数を増やせ
ば外部接続端子数が不足するので、実装密度を高くでき
ないという欠点がある。The high-density LSI package shown in FIG. 1 has the disadvantage that since the IC mounting part and the external connection part are on the same plane, if the number of mounted ICs is increased, the number of external connection terminals becomes insufficient, and therefore the packaging density cannot be increased.
また、第２図に示す高密度ＬＳＩパッケージは、ＩＣ搭
載面に放熱体が接着されているため搭載ＩＣ数を増やせ
ばその分散熱体を減らさねばならず、放熱効果の不足か
ら実装密度を高くできないという欠点があった。In addition, in the high-density LSI package shown in Figure 2, a heat dissipating body is bonded to the IC mounting surface, so if the number of mounted ICs is increased, the number of dispersing heat bodies must be reduced. The drawback was that it couldn't be done.
さらにまた、第３図に示す高密度ＬＳＩパックジは第２
図に示す高密度ＬＳＩパッケージと同様にＩＣ実装部と
放熱部が同一平面上にあるが、放課
熱体をＩＣ上に取付けているために、実装密度を高くす
ることが可能である。Furthermore, the high-density LSI package shown in FIG.
Similar to the high-density LSI package shown in the figure, the IC mounting section and the heat dissipation section are on the same plane, but since the heat dissipation body is mounted on the IC, it is possible to increase the packaging density.
しかしながら、この構造では、放熱体をＩＣチ、プ自体
、およびＩＣチップ内配線と配線基板との接続部で保持
することになるので、ＩＣチップの消費電力が大きい場
合にはそれに見合った大形の放熱体の取付けは、ＩＣチ
ップの機械的強度の上から困難があった。その上、ＩＣ
チップ１個毎に放熱体を取シ付けねばならないという繁
雑さも欠点であった。However, in this structure, the heat dissipation body is held in the IC chip itself and at the connection between the wiring inside the IC chip and the wiring board, so if the power consumption of the IC chip is large, it is necessary to Attaching the heat sink was difficult due to the mechanical strength of the IC chip. Besides, I.C.
Another drawback was the complexity of having to attach a heat sink to each chip.
第４図に示す高密度ＬＳＩパッケージは、外部接続部と
放熱部とが同一平面にあるため、搭載ＩＣ数を増やせば
、放熱部も外部接続部もともに不足するので、実装密度
を高くできないという欠点があった。In the high-density LSI package shown in Figure 4, the external connection part and the heat dissipation part are on the same plane, so if the number of mounted ICs is increased, both the heat dissipation part and the external connection part become insufficient, so it is not possible to increase the packaging density. There were drawbacks.
すなわち、従来の高密度ＬＳＩノくツケージはＩＣ実装
部と、外部接続部と、放熱部とをＩＣ搭載面および対向
面のいずれかに分けて搭載しなけれならず、実装密度を
向上できないという欠点があった。 ・
一本発明の目的は実装密度を向上できる
高密度ＬＳＩパッケージを提供することにある。In other words, conventional high-density LSI chip cages have the disadvantage that the IC mounting section, external connection section, and heat dissipation section must be mounted separately on either the IC mounting surface or the opposing surface, and the mounting density cannot be improved. was there.・
One object of the present invention is to provide a high-density LSI package that can improve packaging density.
すなわち、本発明の目的は、ＩＣ実装部を配線一基板の
第１の面に配置し、放熱部を配線基板の第１・の面、と
対向する第２の面に配置し、外部接続部を第４の面、第
２の面と、は異なる＠３の面に配置することＫよって、
上記欠点を除去し、−装密度を向上できるようにした高
密度ＬＳＩパッケージを提供することにある。That is, an object of the present invention is to arrange the IC mounting section on the first surface of the wiring board, arrange the heat dissipation section on the second surface opposite to the first surface of the wiring board, and dispose the IC mounting section on the first surface of the wiring board. The fourth surface and the second surface are placed on different @3 surfaces. Therefore,
The object of the present invention is to provide a high-density LSI package that eliminates the above drawbacks and improves packing density.
本発明の高密度ＬＳＩパッケージはＩＣチ、プと、前記
ＩＣチップと接続される配線が多層に形成されＬ字状を
がし前記ＩＣチップを搭載するＩＯ２載面と前記ＩＣ搭
載面に対向する対向面と前記ＩＣ搭載面および前記対向
面と垂直な接続面とを有する多層配線基板と、前記対向
面に取シ付けられた放熱体と、前記接続面に形成され前
記配縁と接続される導体パッドとを含んで構成される。The high-density LSI package of the present invention has an IC chip and wiring connected to the IC chip formed in multiple layers, and is peeled off in an L-shape to face the IO2 mounting surface on which the IC chip is mounted and the IC mounting surface. a multilayer wiring board having an opposing surface, the IC mounting surface, and a connecting surface perpendicular to the opposing surface; a heat sink attached to the opposing surface; and a heat sink formed on the connecting surface and connected to the wiring. The conductor pad is configured to include a conductor pad.
すなわち、本発明のＬＳＩパッケージは％（１）セラミ
、り基板の表層に無機又社有機の絶縁材と導電材とを用
いて形成された多層配線層をもつセラミック多層配線基
板および（２）金属板を絶縁材で被覆し、その表層に絶
縁材と導電材とを用いて形成された多層配線層をもつ金
属ベース多層配線基板および（３）表面に配線パターン
の形成されたガラス板又はセラミック板を複・数枚積層
することによって多層化を達成したガラスセラミック積
層配線基板のいずれかの配線基板と該配線基板表面に搭
載されたＩＣチップと、前記配線基板のＩＣ搭載面と対
向する面の広い領域に接して取り付けられた放熱体と、
上記ＩＣ搭載面と垂直又は麩直に近い角度をなす接続面
に形成された導体パッド又はとの面に取り付叶られた導
体ビンを介して外部の配線と前記配線基板に設けられた
配線との電気的接続を行なうように構成される。That is, the LSI package of the present invention consists of (1) a ceramic multilayer wiring board having a multilayer wiring layer formed using an inorganic or organic insulating material and a conductive material on the surface layer of the ceramic board; and (2) a metal A metal-based multilayer wiring board that has a board covered with an insulating material and a multilayer wiring layer formed using an insulating material and a conductive material on the surface layer, and (3) a glass plate or a ceramic board with a wiring pattern formed on the surface. A glass-ceramic laminated wiring board that has achieved multilayering by laminating multiple sheets, an IC chip mounted on the surface of the wiring board, and a surface of the wiring board facing the IC mounting surface. A heat sink attached in contact with a wide area,
The external wiring and the wiring provided on the wiring board are connected to each other through a conductor pad formed on a connection surface that is perpendicular to or at an angle close to the above-mentioned IC mounting surface, or through a conductor bottle attached to the surface. is configured to make an electrical connection.
すなわち、本発明の高密［ＬＳＩパッケージは、セラミ
ック基板の表層に無機又は有機の絶縁材と金ペーストの
焼成或いは金めつき、銅めっきなどの手法による導電材
とを用いて形成された多層配線層をもつセラミック多層
配線基板または、金属板を絶縁材で被覆し、その表層に
絶縁材と導電材とを用いて形成された多層配線層をもつ
金属ベース多層配線基板または、表面に配線パターンの
形成されたガラス板又はセラミック板を複数積層する事
によって多層化を達成したガラスセラミ、り積層配線基
板と上記配線基板の第１の面に搭載されたＩＣチップと
該ＩＣチップの搭載面と対向する上記配線基板の第２の
面の広い領域に秘して取付けられた放熱体と、上記第１
の面及び第２の面に対して垂直又は垂直に近い角度をな
す面に形成された導体パッド又は導体ピンとから構成さ
れ、この導体バッド又は導体ピンを介して、外部の配線
と前記配線基板に設けられた配線との電気的接続を行な
うように構成される。That is, the high-density [LSI package] of the present invention is a multilayer wiring layer formed on the surface layer of a ceramic substrate using an inorganic or organic insulating material and a conductive material by firing a gold paste, gold plating, copper plating, etc. or a metal base multilayer wiring board with a multilayer wiring layer formed by covering a metal plate with an insulating material and using an insulating material and a conductive material on the surface layer, or forming a wiring pattern on the surface. A glass-ceramic laminated wiring board that achieves multilayering by laminating a plurality of glass plates or ceramic plates, an IC chip mounted on a first surface of the wiring board, and an IC chip facing the mounting surface of the IC chip. a heat radiator secretly attached to a wide area of the second surface of the wiring board;
and a conductor pad or conductor pin formed on a surface that is perpendicular or at an angle close to perpendicular to the second surface, and is connected to external wiring and the wiring board via this conductor pad or conductor pin. It is configured to make an electrical connection with the provided wiring.
次に、本発明の実施例について、図面を参照して詳細に
説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
第５図は本発明の一実施例を示す側断面図で、第５図に
示す高密度ＬＳＩパ、ケージは、セラミック積層配線基
板２１にＩＣチップ２２が実装されており、このＩＣチ
、プ内の配線は、微細な金属１ｉ１２３を介して、セラ
ン、り積層配線基板内に形成された配置！２４と接続さ
れている。このセラミ、り積層配線基板２１はＬ字形に
折れ曲りており、その折れ曲った面、即ち■ＣＣチップ
装面に対して垂直な金属バッド２５が形成されており、
この金属バッド２５には金属ピン２６がノ１ンダ付けさ
れている。上記セラミック積層配線基板内の配置！２４
はこの金属バッド２５と接続されておシ、外部との電気
的接続は金属ピン２６と嵌合するコネクターによって行
なわれる。セラミック積層配線基板２１の、ＩＣ搭載面
と対向する面にはヒーに冷風又は冷却液を通すことによ
って放散される。FIG. 5 is a side sectional view showing an embodiment of the present invention. The high-density LSI package shown in FIG. The wiring inside is arranged in a laminated wiring board using Ceran via fine metal 1i123! It is connected to 24. This ceramic laminated wiring board 21 is bent into an L shape, and a metal pad 25 is formed perpendicular to the bent surface, that is, the CC chip mounting surface.
A metal pin 26 is soldered to this metal pad 25. Arrangement inside the ceramic laminated wiring board above! 24
is connected to the metal pad 25, and electrical connection to the outside is made by a connector that fits into the metal pin 26. The heat is dissipated by passing cold air or a cooling liquid through the surface of the ceramic laminated wiring board 21 facing the IC mounting surface.
本発明は、以上説明した様にＩＣチップ実装部と外部接
続部と放熱部とをそれぞれ独立した面に構成できるため
、それぞれの部分の占有面積をパ、ケージ全体としての
実装密度が最大に＆る最適な割合にする事ができるとい
う効果がある。As explained above, the present invention allows the IC chip mounting section, external connection section, and heat dissipation section to be configured on independent surfaces, thereby maximizing the area occupied by each section and maximizing the packaging density of the entire cage. This has the effect of making it possible to set the optimum ratio.
第１図、第２図、第３図、第４図は従来の第１〜第４の
例を示す側断面図、第５図は本発明の一実施例を示す側
断面図である。
１１・・・・・・配線基板、１２・・・・・・ＩＣチ、
プ、１３・・・・・・外部接続バッド、１４°°゛・・
・外部接続ピン、１５・・・・・・放熱体、２１・・・
・・・セラミック積層配線基板、２２・・・・・・ＩＣ
チップ、２３・・・・・・微細金属線、２４・・・・・
・配線、２５・・・・・・金属バッド、２６・・・・′
・・金属ビ第１図 第２図
第３図 第４図
拾５図1, 2, 3, and 4 are side sectional views showing first to fourth conventional examples, and FIG. 5 is a side sectional view showing one embodiment of the present invention. 11...Wiring board, 12...IC chip,
Tap, 13...External connection pad, 14°°゛...
・External connection pin, 15...Heat sink, 21...
...Ceramic laminated wiring board, 22...IC
Chip, 23...Fine metal wire, 24...
・Wiring, 25...Metal pad, 26...'
・・Metal vinyl Figure 1 Figure 2 Figure 3 Figure 4 Figure 15
Claims (1)
に形成されＬ字状を表し前記ＩＣチップを搭載するＩＣ
搭載面と前記ＩＣ搭載面に対向する対向面と前記ＩＣ搭
載面および前記対向面と垂直な接続面とを有する多層配
線基板と、前記対向面に取シ付けられた放熱体と、前記
接続面に形成され前記配線と接続される導体パッドとを
含むことを特徴とする高密度ＬＳＩパッケージ。An IC on which the IC chip and the wiring connected to the IC chip are formed in multiple layers and have an L-shape, and the IC chip is mounted on the IC chip.
a multilayer wiring board having a mounting surface, an opposing surface facing the IC mounting surface, a connection surface perpendicular to the IC mounting surface and the opposing surface, a heat sink attached to the opposing surface, and the connection surface. A high-density LSI package, comprising: a conductor pad formed on the substrate and connected to the wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15172981A JPS5853854A (en) | 1981-09-25 | 1981-09-25 | High integration density lsi package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15172981A JPS5853854A (en) | 1981-09-25 | 1981-09-25 | High integration density lsi package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5853854A true JPS5853854A (en) | 1983-03-30 |
| JPS6139739B2 JPS6139739B2 (en) | 1986-09-05 |
Family
ID=15525009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15172981A Granted JPS5853854A (en) | 1981-09-25 | 1981-09-25 | High integration density lsi package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5853854A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5742927U (en) * | 1980-08-25 | 1982-03-09 | ||
| JPS60262032A (en) * | 1984-06-09 | 1985-12-25 | Mazda Motor Corp | Color discrimination apparatus |
| JPS62117670U (en) * | 1986-01-16 | 1987-07-25 | ||
| JPH07202370A (en) * | 1993-12-21 | 1995-08-04 | Internatl Business Mach Corp <Ibm> | Printed circuit card |
-
1981
- 1981-09-25 JP JP15172981A patent/JPS5853854A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5742927U (en) * | 1980-08-25 | 1982-03-09 | ||
| JPS6122250Y2 (en) * | 1980-08-25 | 1986-07-04 | ||
| JPS60262032A (en) * | 1984-06-09 | 1985-12-25 | Mazda Motor Corp | Color discrimination apparatus |
| JPS62117670U (en) * | 1986-01-16 | 1987-07-25 | ||
| JPH07202370A (en) * | 1993-12-21 | 1995-08-04 | Internatl Business Mach Corp <Ibm> | Printed circuit card |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6139739B2 (en) | 1986-09-05 |
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