JPS6219072B2 - - Google Patents
Info
- Publication number
- JPS6219072B2 JPS6219072B2 JP17078381A JP17078381A JPS6219072B2 JP S6219072 B2 JPS6219072 B2 JP S6219072B2 JP 17078381 A JP17078381 A JP 17078381A JP 17078381 A JP17078381 A JP 17078381A JP S6219072 B2 JPS6219072 B2 JP S6219072B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- chip
- wiring
- insulating layer
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 30
- 239000000919 ceramic Substances 0.000 claims description 25
- 239000011368 organic material Substances 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は、LSIパツケージの構造に関するもの
で、特にICチツプの発生する熱を効率よく放散
させ、かつ高密度な配線を収容することのできる
LSIパツケージに関するものである。[Detailed Description of the Invention] The present invention relates to the structure of an LSI package, and in particular is capable of efficiently dissipating heat generated by an IC chip and accommodating high-density wiring.
It concerns LSI packages.
最近の集積回路の高密度化の進展には著しいも
のがあり、コンピユータ用の論理回路用のLSIに
いたつては、数年前に100ゲート／チツプであつ
たものが、最近では500〜1000ゲート／チツプの
ものまでもが使用されるようになつてきた。それ
とともにコンピユータ回路実装の高密度化に対す
る要求はますます高まり、この要求を満す実装方
法として、従来から、多層配線を施したセラミツ
ク基板の上に前記100ゲート／チツプのLSIを複
数個実装する方法が採用されてきた。 The recent progress in increasing the density of integrated circuits has been remarkable, and LSIs for logic circuits for computers used to have 100 gates per chip a few years ago, but now they have 500 to 1000 gates. / Even chips have come to be used. At the same time, the demand for high-density computer circuit packaging is increasing, and the mounting method that satisfies this demand has traditionally been to mount multiple LSIs of 100 gates/chip on a ceramic substrate with multilayer wiring. method has been adopted.
上記多層配線セラミツク基板を用いる主なる理
由は２つあり、１つはアルミナを主成分とするセ
ラミツク基板の良好な熱伝導性であり、あと１つ
は、無機絶縁材料と金属ペースト材料の厚膜印刷
法による配線パターンの微細化である。 There are two main reasons for using the above multilayer wiring ceramic substrate. One is the good thermal conductivity of the ceramic substrate mainly composed of alumina, and the other is the thick film of inorganic insulating material and metal paste material. This is the miniaturization of wiring patterns using printing methods.
しかるに、前述のように、LSIチツプのゲート
密度が向上し500〜1000ゲート／チツプのLSIが
実現されるに至るとき、LSIのゲート密度の向上
に追従できる高密度配線の基板を実現しようとす
ると、最早従来の技術では対処できないという問
題が明らかになりつつある。 However, as mentioned above, when the gate density of LSI chips improves and LSIs with 500 to 1000 gates/chip are realized, it becomes difficult to realize a substrate with high density wiring that can keep up with the increase in LSI gate density. It is becoming clear that there are problems that can no longer be addressed with conventional technology.
その主なる理由は、ゲート密度の向上による
LSIチツプのピン数の増大と消費電力の増大によ
る発熱量の増大である。特にピン数の増大は、基
板上の配線パターンの微細化に対して非常に大き
なインパクトを与えている。例えば、100ゲー
ト／チツプでは60ピンであつたものが500ゲー
ト／チツプでは160ピンになり、基板上に搭載さ
れるチツプ数を100ゲート／チツプの場合も500ゲ
ート／チツプの場合も同じであるとすれば、概ね
３倍の配線パターンを収容することが必要とな
り、例えば200ミクロン間隔で配線を行なつてい
たものは60ミクロンにまで微細化しなければなら
ない。このような微細化は従来の厚膜印刷法では
不可能である。 The main reason for this is the improvement in gate density.
The increase in the number of pins on an LSI chip and the increase in power consumption result in an increase in heat generation. In particular, the increase in the number of pins has a very large impact on the miniaturization of wiring patterns on substrates. For example, what was 60 pins for a 100 gate/chip becomes 160 pins for a 500 gate/chip, and the number of chips mounted on a board is the same whether it is 100 gates/chip or 500 gates/chip. If this is the case, it will be necessary to accommodate approximately three times as many wiring patterns, and for example, wiring patterns that used to be 200 microns apart will have to be miniaturized to 60 microns. Such miniaturization is not possible with conventional thick film printing methods.
本発明の目的は、ICチツプの発生する熱を効
率よく放散させ、かつLSIチツプのゲート密度の
向上に追従できる高密度LSIパツケージを提供し
ようとすることにある。 An object of the present invention is to provide a high-density LSI package that can efficiently dissipate heat generated by an IC chip and can follow the increase in gate density of LSI chips.
本発明によるマルチチツプLSIパツケージは、
表面にICチツプの収納搭載の可能な凹みを複数
個持ち内部に多層配線を含む積層型多層セラミツ
ク基板と、前記凹みの中に個々に埋没して実装さ
れた複数個のICチツプと、前記凹みを覆いかつ
基板の凹んでない部分に接着された放熱器と、前
記セラミツク基板の前記表面とは反対側の他の表
面に形成された少なくとも１層のポリイミドの如
き有機物の絶縁層と、該絶縁層の内部と表面に形
成された少なくとも１層の配線パターンと、前記
絶縁層の表面に接続された端子ブロツクとを有す
ることを特徴とする。 The multi-chip LSI package according to the present invention is
A laminated multilayer ceramic substrate having a plurality of recesses on its surface capable of storing and mounting IC chips and containing multilayer wiring inside, a plurality of IC chips embedded and mounted individually in the recesses, and the recesses. at least one insulating layer of an organic material such as polyimide formed on the other surface of the ceramic substrate opposite to the surface; and the insulating layer. It is characterized by having at least one layer of wiring patterns formed inside and on the surface of the insulating layer, and a terminal block connected to the surface of the insulating layer.
以下、本発明について図面を参照して詳細に説
明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は、本発明の一実施例を示すLSIパツケ
ージの断面図である。図において、１はICチツ
プ、２はICチツプの端子リード、３は端子リー
ドがボンデイングされるボンデイングパツド、４
は積層型多層セラミツク基板（以下セラミツク基
板と略す）、５はセラミツク基板中に形成された
電源配線、６は同じくグランド配線、７はセラミ
ツク基板中に形成されたスルーホール、８はスル
ーホールパツド、９はセラミツク基板の裏面に形
成されたポリイミドの如き有機絶縁層、１０は有
機絶縁層中に形成された配線パターン、１１は端
子パツド、１２は端子ブロツク、１３は入出力ピ
ン、１４は放熱器、１５はセラミツク基板４に表
面に形成された凹みである。 FIG. 1 is a sectional view of an LSI package showing an embodiment of the present invention. In the figure, 1 is an IC chip, 2 is a terminal lead of the IC chip, 3 is a bonding pad to which the terminal lead is bonded, and 4 is a bonding pad to which the terminal lead is bonded.
is a laminated multilayer ceramic substrate (hereinafter abbreviated as ceramic substrate), 5 is a power supply wiring formed in the ceramic substrate, 6 is also a ground wiring, 7 is a through hole formed in the ceramic substrate, and 8 is a through hole pad. , 9 is an organic insulating layer such as polyimide formed on the back side of the ceramic substrate, 10 is a wiring pattern formed in the organic insulating layer, 11 is a terminal pad, 12 is a terminal block, 13 is an input/output pin, and 14 is a heat radiation. 15 is a recess formed on the surface of the ceramic substrate 4.
第２図は第１図のLSIパツケージを斜め上から
見た図であり、放熱器１４の下の凹み１５および
この凹みに埋没されて実装されたICチツプ１を
透視的に示している。 FIG. 2 is a view of the LSI package of FIG. 1 viewed diagonally from above, and transparently shows the recess 15 below the heat sink 14 and the IC chip 1 embedded and mounted in this recess.
第３図は同様に第１図のLSIパツケージを斜め
下から見た図である。 Similarly, FIG. 3 is a diagram of the LSI package shown in FIG. 1 viewed diagonally from below.
次に第１図に従つて本発明の詳細を説明する。
セラミツク基板４には積層型多層セラミツク基板
を使用する。積層型多層セラミツク基板は周知の
グリーンシートと呼ばれるアルミナ粉末を主成分
とする焼結前のシートを積み重ねて焼結すること
により製造される。 Next, details of the present invention will be explained with reference to FIG.
As the ceramic substrate 4, a laminated multilayer ceramic substrate is used. A laminated multilayer ceramic substrate is manufactured by stacking and sintering well-known green sheets, which are mainly composed of alumina powder and are not yet sintered.
第１図で４−１〜４−４で示したものは焼結前
にそれぞれ分離していたグリーンシートを示して
いる。図からも容易に理解できるようにセラミツ
ク基板４はグリーンシート４−１〜４−４を積層
焼結して形成されたものであり、特にグリーンシ
ート４−１に正方形の大きい穴を明けたものを使
用し、グリーンシート４−２には正方形の小さい
穴を明けかつボンデイングパツド３およびスルー
ホール７の印刷形成されたものを使用し、グリー
ンシート４−３にはスルーホール７および電源配
線５が印刷形成されたものを使用し、グリーンシ
ート４−４には裏面にスルーホールパツド８が表
面にグランド配線６およびスルーホール７が印刷
形成されたものを使用する。このように構成する
ことにより、凹み１５、ボンデイングパツド３、
スルーホール７、電源配線５、グランド配線６、
スルーホールパツド８を具えたセラミツク基板４
の導入は何ら問題なく可能である。 In FIG. 1, 4-1 to 4-4 indicate green sheets that were separated before sintering. As can be easily understood from the figure, the ceramic substrate 4 is formed by stacking and sintering green sheets 4-1 to 4-4, and in particular, the green sheet 4-1 has large square holes. The green sheet 4-2 is made with small square holes and the bonding pads 3 and through holes 7 are printed on it, and the green sheet 4-3 is made with through holes 7 and power wiring 5. The green sheet 4-4 has through-hole pads 8 printed on its back side and ground wiring 6 and through-holes 7 printed on its front side. With this configuration, the recess 15, the bonding pad 3,
Through hole 7, power supply wiring 5, ground wiring 6,
Ceramic substrate 4 with through-hole pads 8
can be introduced without any problems.
ICチツプ１は凹み１５の中に埋没して搭載さ
れ、チツプ本体は電源配線５の上にダイボンデイ
ングされる。端子リード２はボンデイングパツド
３にワイヤボンデイングされる。ボンデイングパ
ツド３にボンデイング接続されたICチツプ１の
各々の端子は、全てスルーホール７を通してスル
ーホールパツド８に接続される。従つてICチツ
プ１の全ての端子は、基板４の裏面の各々のスル
ーホールパツド８に取り出されることになる。 The IC chip 1 is embedded and mounted in the recess 15, and the chip body is die-bonded onto the power supply wiring 5. Terminal lead 2 is wire bonded to bonding pad 3. All terminals of the IC chip 1 bonded to the bonding pad 3 are connected to the through-hole pad 8 through the through-hole 7. Therefore, all the terminals of the IC chip 1 are taken out to the respective through-hole pads 8 on the back surface of the substrate 4.
またセラミツク基板４内の内層の電源配線５お
よびグランド配線６は、主としてICチツプ１に
電源を供給するためのものであり、ICチツプ１
の端子の各々に接続されたボンデイングパツド３
のうち、電源およびグランドに相当するボンデイ
ングパツドの下のスルーホール７と基板４の内層
において接続される。 Further, the power supply wiring 5 and the ground wiring 6 on the inner layer of the ceramic substrate 4 are mainly for supplying power to the IC chip 1.
bonding pads 3 connected to each of the terminals of
Among them, the through hole 7 under the bonding pad corresponding to the power supply and ground is connected in the inner layer of the substrate 4.
セラミツク基板４の裏面のスルーホールパツド
８に導通接続されたICチツプ１の各々の端子
は、ポリイミドの如く、耐熱温度が約400℃と耐
熱性が高く、しかも成膜の緻密性が高くかつ滑ら
かな表面が得やすい有機絶縁層９の中に形成され
た配線パターン１０によつて相互接続される。す
なわち、ICチツプ１の各々において相互に接続
する必要のある信号配線は、配線パターン１０に
よつて実現される。 Each terminal of the IC chip 1 which is electrically connected to the through-hole pad 8 on the back side of the ceramic substrate 4 is made of polyimide, which has a high heat resistance of about 400°C, and has a highly dense film formation. The wiring patterns 10 are interconnected by a wiring pattern 10 formed in an organic insulating layer 9 that easily provides a smooth surface. That is, the signal wiring that needs to be connected to each other in each IC chip 1 is realized by the wiring pattern 10.
さらに、ICチツプ１の各々の端子において、
外部との入出力接続を行なう必要のある端子は、
同様に配線パターン１０のうち、１０′と記号を
付した配線パターンによつて端子パツド１１に接
続され、この端子パツド１１に接続された端子ブ
ロツク１２上の入出力ピン１３に電気的に導通接
続され外部との接続がなされる。 Furthermore, at each terminal of the IC chip 1,
Terminals that require external input/output connections are
Similarly, among the wiring patterns 10, the wiring pattern marked 10' is connected to the terminal pad 11, and is electrically connected to the input/output pin 13 on the terminal block 12 connected to this terminal pad 11. connection with the outside world.
放熱器１４はセラミツク基板４の表面すなわち
凹んでない部分に接着され、ICチツプ１の発生
する熱をセラミツク基板４を介して放熱する。前
述のようにセラミツク基板４はアルミナを主成分
とした熱伝導性の良好なものであり、放熱器１４
と直接接続されるので、効率的な放熱が可能とな
る。 The heat radiator 14 is bonded to the surface of the ceramic substrate 4, that is, the portion that is not recessed, and radiates the heat generated by the IC chip 1 through the ceramic substrate 4. As mentioned above, the ceramic substrate 4 is made of alumina as a main component and has good thermal conductivity.
Since it is directly connected to the PCB, efficient heat dissipation is possible.
また、前述のように、配線パターン１０として
は極めて高密度な配線を必要とするが、絶縁層９
にポリイミドの如き有機絶縁材料を使用すること
により、表面が無機絶縁層に比べて極めて平滑に
なり、従つて50〜100μ間隔の配線パターンの形
成が可能である。 Furthermore, as described above, the wiring pattern 10 requires extremely high-density wiring, but the insulating layer 9
By using an organic insulating material such as polyimide, the surface becomes much smoother than that of an inorganic insulating layer, making it possible to form wiring patterns with an interval of 50 to 100 microns.
本発明は以下説明したように、セラミツク基板
の表面であるICチツプ搭載面に放熱器を密着し
て取りつけ効率的な放熱を行なうとともに、裏面
に有機絶縁材料を使用した微細高密度配線を形成
することにより、高密度実装のLSIパツケージを
実現できるという効果がある。 As explained below, the present invention involves attaching a heat sink in close contact with the IC chip mounting surface, which is the front surface of a ceramic substrate, for efficient heat dissipation, and forming fine high-density wiring using an organic insulating material on the back surface. This has the effect of realizing a high-density packaging LSI package.
第１図は本発明の一実施例を示すLSIパツケー
ジの断面図、第２図は第１図のLSIパツケージを
斜め上から見た斜視図、第３図は第１図のLSIパ
ツケージを斜め下から見た斜視図である。
記号の説明：１はICチツプ、３はボンデイン
グパツド、４は積層型セラミツク基板、５は電源
配線、６はグランド配線、８はスルーホールパツ
ド、９は有機絶縁層、１０は配線パターン、１１
は端子パツド、１２は端子ブロツク、１４は放熱
器をそれぞれあらわしている。
Fig. 1 is a cross-sectional view of an LSI package showing an embodiment of the present invention, Fig. 2 is a perspective view of the LSI package shown in Fig. 1 viewed diagonally from above, and Fig. 3 is a cross-sectional view of the LSI package shown in Fig. 1 diagonally below. FIG. Explanation of symbols: 1 is an IC chip, 3 is a bonding pad, 4 is a laminated ceramic substrate, 5 is a power supply wiring, 6 is a ground wiring, 8 is a through-hole pad, 9 is an organic insulating layer, 10 is a wiring pattern, 11
12 represents a terminal pad, 12 represents a terminal block, and 14 represents a heat sink, respectively.
Claims (1)
複数個持ち内部に多層配線を含む積層型多層セラ
ミツク基板と、前記凹みの中に個々に埋没して実
装された複数個のICチツプと、前記凹みを覆い
かつ基板の凹んでない部分に接着された放熱器
と、前記セラミツク基板の前記表面とは反対側の
他の表面に形成された少なくとも１層の有機物の
絶縁層と、該絶縁層の内部と表面に形成された少
なくとも１層の配線パターンと、前記絶縁層の表
面に接続された端子ブロツクとを有するマルチチ
ツプLSIパツケージ。1. A laminated multilayer ceramic substrate having a plurality of recesses on its surface capable of storing and mounting IC chips and containing multilayer wiring inside; a plurality of IC chips embedded and mounted individually in the recesses; a heat sink covering the recess and bonded to the non-recessed portion of the substrate; at least one insulating layer of an organic material formed on another surface of the ceramic substrate opposite to the surface; and an interior of the insulating layer. A multi-chip LSI package comprising at least one layer of wiring patterns formed on the surface of the insulating layer, and a terminal block connected to the surface of the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078381A JPS5873142A (en) | 1981-10-27 | 1981-10-27 | Multichip lsi package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078381A JPS5873142A (en) | 1981-10-27 | 1981-10-27 | Multichip lsi package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873142A JPS5873142A (en) | 1983-05-02 |
| JPS6219072B2 true JPS6219072B2 (en) | 1987-04-25 |
Family
ID=15911281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17078381A Granted JPS5873142A (en) | 1981-10-27 | 1981-10-27 | Multichip lsi package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873142A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63198565A (en) * | 1987-02-12 | 1988-08-17 | Sony Corp | Flat brushless motor and manufacture thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6061791U (en) * | 1983-09-30 | 1985-04-30 | 日本メクトロン株式会社 | High density pattern cooling device |
| JPS60187098A (en) * | 1984-03-07 | 1985-09-24 | イビデン株式会社 | Plug-in package substrate |
| US4771366A (en) * | 1987-07-06 | 1988-09-13 | International Business Machines Corporation | Ceramic card assembly having enhanced power distribution and cooling |
-
1981
- 1981-10-27 JP JP17078381A patent/JPS5873142A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63198565A (en) * | 1987-02-12 | 1988-08-17 | Sony Corp | Flat brushless motor and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5873142A (en) | 1983-05-02 |
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