JPS5843553A - Multi-chip lsi package - Google Patents
Multi-chip lsi packageInfo
- Publication number
- JPS5843553A JPS5843553A JP56141934A JP14193481A JPS5843553A JP S5843553 A JPS5843553 A JP S5843553A JP 56141934 A JP56141934 A JP 56141934A JP 14193481 A JP14193481 A JP 14193481A JP S5843553 A JPS5843553 A JP S5843553A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring layer
- multilayer
- hole
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【発明の詳細な説明】
、本発明は高密度Ｌ ８ Ｉ （Ｌａｒｇｅ Ｓｃａｌ
ｅＩｎｔｅｇｒａｔｉｏｎ ）パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides high density L 8 I (Large Scal
eIntegration) package.
。、近年、コンビ二一タの高性能化、小形化の要求がま
すます高マ）、このためハードウェアの主たる部分を占
めるＬ８Ｉチップおよびこれらを搭載するＬ８Ｉパッケ
ージに・ついて−高速度、高密度の条件を満す構造を必
要とするようｋなって自た。. In recent years, demands for high performance and miniaturization of combinators have become increasingly high.For this reason, the L8I chips that make up the main part of the hardware and the L8I packages that carry them - high speed, high density. It became necessary to have a structure that satisfies the following conditions.
一方、Ｌ８Ｉチップについてはチップ自身の高速化をは
かるとともに、チップ間を亀高速に信号を伝送する必要
性から高速、ｉつ高負荷駆動能力をもクエ宅ツタ７オー
ア形出力回路を有する鬼のが使用されている。On the other hand, as for the L8I chip, in addition to increasing the speed of the chip itself, due to the need to transmit signals between chips at extremely high speed, the L8I chip also has a high-speed and high-load drive capability. is used.
従来技術の例では−ＩＯチップ自身の速度本現在のもの
に比べれば比較的低速であり、従ってＬ８Ｉバック−２
内の信号配線による信号伝搬回路は集中定数回路とみな
すことができたため信号波形の終端方法は、厳密性を要
求されず、例えばＩＣチップ内に形成された抵抗値精１
１０夷〈な一半導体抵抗を使用するヒと４可能であった
。 ・
ところが前述のように鍛近になって超高速のＬ８Ｉチッ
プが開発され工電ツタフオ四ア形出力回路でさらに信号
波形も極めて高速なパルスが扱われゐように１つてくる
と、もはやｆ、８Ｉパッケージ内め信号配線も分布定数
回路として扱わなければならなく１にり、従って信号波
形に対する正確な終端が必要となるとともに信号配線の
遅延を少表くするために信号配線長も最短に従ってＬ８
Ｉチップをできるだ叶近接して実装する工夫がなされな
ければならない。In the prior art example - the speed of the IO chip itself is relatively slow compared to the current one, so the L8I back-2
Since the signal propagation circuit using the signal wiring inside the IC chip can be regarded as a lumped constant circuit, the termination method of the signal waveform is not required to be exact.
It was possible to use a single semiconductor resistor of 10 or more.・However, as mentioned above, with the development of the ultra-high-speed L8I chip and the introduction of the Koden Tsutao four-way output circuit, which handles extremely high-speed pulses in signal waveforms, it is no longer f, The signal wiring inside the 8I package must also be treated as a distributed constant circuit, so accurate termination for the signal waveform is required, and in order to minimize the signal wiring delay, the signal wiring length is also shortened to L8.
Efforts must be made to mount the I chips as close together as possible.
このため、Ｌ８Ｉパッケージとしては前記Ｌ８Ｉチップ
を高密度に搭載して高密度配線を収容するとともＫＬβ
Ｉチップから発生する熱を効率よく放散させることが要
求され、さらに高速度の条件を満たす丸、めに前記信号
配線の正確な終端のための高精度の終端抵抗を収容す”
ることか要求されている。Therefore, as an L8I package, the L8I chips are mounted at high density to accommodate high-density wiring, and the KLβ
It is required to efficiently dissipate the heat generated from the I-chip, and it also accommodates a high-precision termination resistor for accurate termination of the signal wiring in a round shape that satisfies high-speed requirements.
That is what is required.
本発明の目的はセラ電ツク基板上に実装するＩＯチップ
間の信号伝書の高速化が実現でき、″″＊に″０ｆ９１
：遭！１ｊｆＫｌｌＩｉｉＷｍ＆−ｒルチチツプＬ８Ｉ
バッ ジを提供するととｋある。The purpose of the present invention is to realize high-speed transmission of signals between IO chips mounted on a ceramic board, and to
: Encounter! 1jfKllIiiiWm&-rruchitip L8I
It is possible to provide a badge.
前記目的を達成するために本発明によるマルチチップＬ
８Ｉパッケージは基板表面に終端抵抗体およびスルーホ
ールパッドを有し、基板裏面に入出力端子を有し、内層
に多層電源配線層お、よびつ層を貫通して前記スルーホ
ールパッドと入出力端子間を接続するスルーホールを有
する積層形多層セラミック基板と、前記セラミツ″り基
板表面の終端抵抗体およびスルーホールバブキャリアと
で構成しである。To achieve the above object, a multi-chip L according to the present invention
The 8I package has a terminating resistor and a through-hole pad on the front surface of the board, input/output terminals on the back surface of the board, a multilayer power supply wiring layer on the inner layer, and the through-hole pads and input/output terminals that penetrate through the two layers. The device is composed of a laminated multilayer ceramic substrate having through holes for connection therebetween, a terminating resistor on the surface of the ceramic substrate, and a through hole bubble carrier.
以下、図面を参照して本発明をさらに詳しく説明する。Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第１図は本発明の実施例でｉルチチツプＬ８Ｉパッケー
ジの断面を示す図である。FIG. 1 is a cross-sectional view of an i-multichip L8I package according to an embodiment of the present invention.
第１図においてｌはＬ８Ｉチップ、２はチップキャリア
、３はヒートシンク、４はチップ命ヤ、・、：
リア接続パッド、：、：Ｐ竺多層配線層、・は多層配線
、７はスルーホールハツト、８は終端抵抗、９は多層セ
ラミツク基板、１０は多層電源配線、１１は入出力端子
、戎はスルーホールである。In Fig. 1, l is an L8I chip, 2 is a chip carrier, 3 is a heat sink, 4 is a chip protector, . . . : rear connection pad, :, : P vertical multilayer wiring layer, . is a multilayer wiring, 7 is a through hole hat. , 8 is a terminal resistor, 9 is a multilayer ceramic substrate, 10 is a multilayer power supply wiring, 11 is an input/output terminal, and 11 is a through hole.
第２図は本発明によるマルチチップＬ８Ｉパッケージの
平面図、第３図は第２図よ）多層配線層Ｓを取り除いて
示した平面図である６、第１図において、多層セラミツ
ク基板９はその内部に多層の電源配線１０とスルーホー
ル１２を含んでいる。このようなセラζツク基板は周知
のグリーンシー゛ト積層法による積層形多層セラミック
基板として現在の技術で容易に実現できるものである。2 is a plan view of a multi-chip L8I package according to the present invention, and FIG. 3 is a plan view with the multilayer wiring layer S (as shown in FIG. 2) removed.6 In FIG. 1, the multilayer ceramic substrate 9 is It includes multilayer power supply wiring 10 and through holes 12 inside. Such a ceramic substrate can be easily realized using current technology as a laminated multilayer ceramic substrate using the well-known green sheet lamination method.
基板９０表面には第３図で示すようにスルーホール１ｚ
と接続されたスルーホールパッド７と終端抵抗魯が形成
されている。A through hole 1z is formed on the surface of the substrate 90 as shown in FIG.
A through-hole pad 7 and a terminating resistor are formed.
終端抵抗Ｓは例えば中性雰囲気中で焼成できる周知の厚
膜抵抗ペーストを用いて基板９０表面に印刷焼成によっ
て形成されえものである。The terminating resistor S may be formed on the surface of the substrate 90 by printing and baking, for example, using a well-known thick film resistor paste that can be baked in a neutral atmosphere.
またスルーホールパッド７は基１［９を製造するときに
用いられる金属材料ペースト（タング堺テン中モリブデ
ン）を印刷焼成し、その上に化学的な保護および低接触
抵抗をうるために金メッキが施されえもので娶る。The through-hole pads 7 are made by printing and firing the metal material paste (Tung, Sakai ten, molybdenum) used when manufacturing the base 1 [9], and gold plating is applied thereon to provide chemical protection and low contact resistance. Marry something you can afford.
また基板参の裏面には入出力端子１１が横端されている
。端子１１は本実施例ではビンを銀ろう材などによりス
ルーホール１２に導通するようＫろう付けしたものであ
る。Further, input/output terminals 11 are provided on the back side of the board. In this embodiment, the terminal 11 is a bottle which is K-brazed with silver brazing material or the like so as to be electrically connected to the through hole 12.
多層配線層５は前記多層セラζツク基板、嘗の表面にお
いて終端抵抗８およびスルーホールパッド７を覆うよう
に形成したものであり、内部には多層配線６が収容され
ている。The multilayer wiring layer 5 is formed on the surface of the multilayer ceramic substrate so as to cover the termination resistor 8 and the through hole pad 7, and the multilayer wiring 6 is housed inside.
多層配線６は各々のＬ８Ｉチップ１の信号端子間、各々
のＬＳＩチップ１の端子と入出力端子１１との間、各々
のＬＳＩチップ１の信号端子と終端抵抗８との間を導通
して接続する丸めの′ものであり、多層配線層の内部を
縦、横上下に走る配線パターンである。The multilayer wiring 6 conducts and connects between the signal terminals of each L8I chip 1, between the terminals of each LSI chip 1 and the input/output terminal 11, and between the signal terminal of each LSI chip 1 and the terminating resistor 8. It is a rounded wiring pattern that runs vertically, horizontally, up and down inside a multilayer wiring layer.
多層配線層５を形成す□るためには、例えばポリイミド
のよ・うな有機絶縁膜の上にスパッタによ）下地金属を
付着させ、仁の金属膜上にフォトレジストをコーティン
グし配線−（ターンを露光現俸してエツチングにより不
要金属膜を取９除き、しかる後配線パターンに良導体例
えば銅などをメッキする手順をく）返せばよい。In order to form the multilayer wiring layer 5, a base metal (by sputtering) is deposited on an organic insulating film such as polyimide, a photoresist is coated on the layered metal film, and the wiring (turn pattern) is formed. Then, the unnecessary metal film is removed by exposure and etching, and then the process of plating the wiring pattern with a good conductor, such as copper, is repeated.
チップキャリア２は多層配線層５０表面に股けられたチ
ップキャリア接続パッド４に接続される。チップキャリ
ア２の端子およびチップキャリア接続パッド４は第２図
で示すような構造になっている。The chip carrier 2 is connected to chip carrier connection pads 4 straddled on the surface of the multilayer wiring layer 50. The terminals of the chip carrier 2 and the chip carrier connection pads 4 have a structure as shown in FIG.
Ｌ８Ｉチップ１の端子は、チップキャリア２の内部にお
いてボンディング接続されチップキャリア２０４辺の端
子部に導通しており、、チップキャリア２を接続パッド
４Ｋ例えばｊＢＢＮ接−するととにより多層配線層Ｓの
内部の多！配！′６との導通接続が可能である。The terminals of the L8I chip 1 are bonded inside the chip carrier 2 and are electrically connected to the terminals on the 4th side of the chip carrier 20. When the chip carrier 2 is connected to the connection pad 4K, for example, jBBN, the inside of the multilayer wiring layer S is connected. Many! Delivery! '6 can be electrically connected.
またチ、ツブキャリア２においてＬ８Ｉチップ１の搭載
面と対向する面にヒートシレク３が接 、続されＬ８Ｉ
チップｌの発生する熱ｉ効率よ七゛ □、
゛
放熱することができる。Also, in the tube carrier 2, the heatshirek 3 is connected to the surface opposite to the surface on which the L8I chip 1 is mounted.
The heat i efficiency generated by the chip l is 7゛ □,
゛It can radiate heat.
本発明による一ルチチップＬ８Ｉパンケーレ゛は以上の
ような構成であるので次のようなすぐゎえ。□オ、。パ
：１１□１１□・、、（１）多層セラミック基Ｉ［９の
内層に設けた多層配線層を電源導体配線としているので
電源配線）低インピーダンス化が可能とｉｋＤ電源雑音
の減少により高速化が可能である。Since the single multi-chip L8I pankey according to the present invention has the above-mentioned configuration, it can be used as follows. □Oh. P: 11□11□・,, (1) Multilayer ceramic base I [power supply wiring because the multilayer wiring layer provided on the inner layer of 9 is used as power supply conductor wiring) Low impedance is possible and ikD power supply noise is reduced, increasing speed is possible.
（２）同時に多層配線層５の内部に大きな面積を占める
電源配線が不要となるので高密度の信号多層配線が可能
となる。(2) At the same time, since power supply wiring occupying a large area inside the multilayer wiring layer 5 is not required, high-density multilayer signal wiring becomes possible.
（３） 多層配線層Ｓを終端抵抗８を覆うように形成
するため終端抵抗＄をセラミック基板・の宍面市面に多
層配線−が必要とするに十分な°個数１、高密度に配置
することができ、同時に信号−〇完全終端ができるので
高速度化も実現できる。４
（４）多層配線６から入出力端子１１への接続はスルー
ホー・ルバツド７およびスルーホールｔｚヲ□介して最
短距離で行なっているためＩＯチツ□、ニア１の端子か
ら入出力端子ｌｉｔでの配線長が短くでき高速度化が可
能となる。(3) In order to form the multilayer wiring layer S so as to cover the terminating resistor 8, the terminating resistors are placed on the surface of the ceramic substrate at a high density and in a sufficient number to meet the requirements of the multilayer wiring. At the same time, the signal can be completely terminated, making it possible to achieve higher speeds. 4 (4) Since the connection from the multilayer wiring 6 to the input/output terminal 11 is made via the through-hole rubad 7 and the through-hole tzwo□, the connection from the IO chip□ and near 1 terminal to the input/output terminal lit Wiring length can be shortened and high speed can be achieved.
（５）ＬＳＩチップ−１′はチップキャリア２を介し、
□ｔｌン：１＝・１、アップやヤ、ア２え、−。(5) LSI chip-1' passes through chip carrier 2,
□tln: 1=・1, up, ya, a2e, -.
シンク３を＊Ｊ）つければより効率的な放熱が可能とな
）従って発熱の制＠に係るＬＳＩチップの搭載個数を増
大させることができ、ＬＳＩチップの高密度実装が可能
と表る。If a sink 3 is attached *J), more efficient heat dissipation becomes possible) Therefore, it is possible to increase the number of mounted LSI chips related to heat generation control, and high-density mounting of LSI chips becomes possible.
本発明は以上詳しく説明したように終端抵抗８および入
出力端子１１に＊続されたスルーホールパッド７を有す
る多層セラミック基板９とその表面に構築された多層配
線層５およびチップキャリア２とから構成することによ
り高密度、高速＆なマルチチップＬ８Ｉパッケージを実
現できる。As described in detail above, the present invention is composed of a multilayer ceramic substrate 9 having a through-hole pad 7 connected to a termination resistor 8 and an input/output terminal 11, a multilayer wiring layer 5 constructed on the surface thereof, and a chip carrier 2. By doing so, a high-density, high-speed & multi-chip L8I package can be realized.
第１図乃至第３図は本発明の実施例を示す図である。
１・・、Ｌ ８ Ｉチップ ２・・・チップキャリ
アト４層配置１１層？・・・スルーホールパッドノド・
・終端抵抗 ９・・・多層セラミック基板１１・・
・入出力端子 ｉｚ−・・スルーホール特許出願人
日本電気株式会社
代理人 弁理士 井 ノ ロ 壽
″４ｐ７図
、（
才２図
９1 to 3 are diagrams showing embodiments of the present invention. 1..., L 8 I chip 2... Chip carrier 4-layer arrangement 11 layers?・・・Through hole pad throat・
・Terminal resistor 9...Multilayer ceramic board 11...
・Input/output terminal iz-...Through hole patent applicant
Hisashi Inoro, Patent Attorney, NEC Co., Ltd. Figure 4, page 7, Figure 2, Figure 9
Claims (1)
、基板裏１ｉｆＫ入出力端子を有し、内層に・多層電源
配線層および内層を貫通して前記スルーホールノ（ラド
と入出力端子間を接続するスルーホールを有する積層形
多層セラミック基板と、前記上う電ツク基板表面の終端
抵抗体シよびスルーホールパラ・ドを覆うように形成さ
れた多層配線層と、前記多層配線層上に配設された複数
個のＩＯチップ中キャリアで構成したことを特徴とする
宜ルチチップＬＳＩパッケージ。It has a termination resistor and a through-hole pad on the surface of the board, and a 1ifK input/output terminal on the back of the board, and a through-hole pad (between the pad and the input/output terminal) that penetrates the inner layer and the multilayer power supply wiring layer and the inner layer. A laminated multilayer ceramic substrate having through holes for connection, a multilayer wiring layer formed so as to cover the terminating resistor layer and the through hole parallel on the surface of the upper electrical board, and a multilayer wiring layer disposed on the multilayer wiring layer. A multi-chip LSI package comprising a plurality of IO chip carriers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141934A JPS5843553A (en) | 1981-09-08 | 1981-09-08 | Multi-chip lsi package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141934A JPS5843553A (en) | 1981-09-08 | 1981-09-08 | Multi-chip lsi package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5843553A true JPS5843553A (en) | 1983-03-14 |
| JPS6135703B2 JPS6135703B2 (en) | 1986-08-14 |
Family
ID=15303540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56141934A Granted JPS5843553A (en) | 1981-09-08 | 1981-09-08 | Multi-chip lsi package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843553A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02119164A (en) * | 1989-09-20 | 1990-05-07 | Hitachi Ltd | Semiconductor module |
| US5045922A (en) * | 1989-09-20 | 1991-09-03 | Hitachi, Ltd. | Installation structure of integrated circuit devices |
| JP2002111222A (en) * | 2000-10-02 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
| JP2007165932A (en) * | 2007-02-22 | 2007-06-28 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
-
1981
- 1981-09-08 JP JP56141934A patent/JPS5843553A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02119164A (en) * | 1989-09-20 | 1990-05-07 | Hitachi Ltd | Semiconductor module |
| US5045922A (en) * | 1989-09-20 | 1991-09-03 | Hitachi, Ltd. | Installation structure of integrated circuit devices |
| JPH0544190B2 (en) * | 1989-09-20 | 1993-07-05 | Hitachi Ltd | |
| JP2002111222A (en) * | 2000-10-02 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
| JP2007165932A (en) * | 2007-02-22 | 2007-06-28 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6135703B2 (en) | 1986-08-14 |
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