JP2677087B2 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JP2677087B2
JP2677087B2 JP3318761A JP31876191A JP2677087B2 JP 2677087 B2 JP2677087 B2 JP 2677087B2 JP 3318761 A JP3318761 A JP 3318761A JP 31876191 A JP31876191 A JP 31876191A JP 2677087 B2 JP2677087 B2 JP 2677087B2
Authority
JP
Japan
Prior art keywords
electrode pad
resistor
integrated circuit
semiconductor integrated
external electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3318761A
Other languages
Japanese (ja)
Other versions
JPH0613438A (en
Inventor
勝彦 矢部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3318761A priority Critical patent/JP2677087B2/en
Publication of JPH0613438A publication Critical patent/JPH0613438A/en
Application granted granted Critical
Publication of JP2677087B2 publication Critical patent/JP2677087B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体集積回路に関し、
特に高速演算回路を有する半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having a high speed arithmetic circuit.

【０００２】[0002]

【従来の技術】近年電子計算機の発達により、半導体集
積回路の高速演算回路に要求される演算速度の向上、高
集積化の要請が増大している。高速演算を実現するのに
半導体集積回路としてＥＣＬ回路又はＣＭＬ回路を使用
する場合、インピーダンス整合のため高精度の抵抗値を
有する終端抵抗を必要とする。2. Description of the Related Art With the development of electronic computers in recent years, there has been an increasing demand for higher operation speed and higher integration required for high-speed operation circuits of semiconductor integrated circuits. When using an ECL circuit or a CML circuit as a semiconductor integrated circuit for realizing high-speed calculation, a terminating resistor having a highly accurate resistance value is required for impedance matching.

【０００３】従来この終端抵抗は、抵抗値のばらつきを
小さくする為に、半導体集積回路を実装する多層配線基
板もしくは、半導体チップを収容するチップキャリア等
のパッケージ内に設けていた。（例えば特公昭６３−０
０４７０９号公報参照）。なお半導体チップ内に５％以
下のばらつき範囲の５０Ω程度の終端抵抗を形成する事
は、抵抗のサイズを非常に大きくする必要があったり、
規格内抵抗の歩留が非常に低下する為、実用上製造する
事は非常に困難である。Conventionally, this terminating resistor has been provided in a package such as a multilayer wiring board for mounting a semiconductor integrated circuit or a chip carrier for accommodating a semiconductor chip in order to reduce variations in resistance value. (For example, Japanese Patent Publication Sho 63-0
No. 04709). Note that forming a terminating resistance of about 50Ω in the semiconductor chip with a variation range of 5% or less requires a very large resistance size,
Since the yield of in-specification resistance is very low, it is very difficult to manufacture practically.

【０００４】[0004]

【発明が解決しようとする課題】半導体集積回路を高密
度に実装するための多層配線基板においては、終端抵抗
を形成するのに必要な特別の領域を設けなければならな
いため、高密度化を阻害し性能を低下させるという問題
がある。また、チップキャリヤ内に抵抗体を設ける場
合、多数個の抵抗体を設ける事が出来ないため、半導体
集積回路の全ての入出力端子（入力又は出力端子のいず
れか全ての場合も）に対応して終端抵抗を設ける事は困
難である。In a multilayer wiring board for mounting a semiconductor integrated circuit at a high density, it is necessary to provide a special region necessary for forming a terminating resistor, which hinders high density. However, there is a problem that the performance is lowered. Also, when a resistor is provided in the chip carrier, it is not possible to provide a large number of resistors, so it is possible to support all input / output terminals (even if either input or output terminal) of the semiconductor integrated circuit. It is difficult to provide a terminating resistor.

【０００５】更に多層基板の場合でも、チップキャリア
の場合でも、終端抵抗の取付け位置が半導体チップの入
出力端近傍に設けられないため、インピーダンス整合性
に限界を生じ、またノイズ等が増加し、高速演算に支障
を起たすという問題がある。Further, in the case of both the multilayer substrate and the chip carrier, since the mounting position of the terminating resistor is not provided in the vicinity of the input / output end of the semiconductor chip, impedance matching is limited and noise and the like increase. There is a problem that it hinders high-speed calculation.

【０００６】[0006]

【課題を解決するための手段】本発明の半導体集積回路
は、素子が形成された半導体チップの外周部に設けられ
入出力信号用電極パッドに配線導体により接続された第
１の外部電極パッドと、この第１の外部電極パッドに隣
接して設けられ電源用電極パッドに接続された第２の外
部電極パッドと、前記第１の外部電極パッドと前記第２
の外部電極パッドとの間に接続された外部接続端子付の
抵抗体とを含むものである。A semiconductor integrated circuit according to the present invention includes a first external electrode pad which is provided on an outer peripheral portion of a semiconductor chip on which an element is formed and which is connected to an input / output signal electrode pad by a wiring conductor. A second external electrode pad provided adjacent to the first external electrode pad and connected to a power source electrode pad, the first external electrode pad and the second external electrode pad
And a resistor with an external connection terminal connected between the external electrode pad and the external electrode pad.

【０００７】[0007]

【実施例】次に本発明について図面を参照して説明す
る。図１（ａ），（ｂ）は本発明の第１の実施例を示す
半導体集積回路の平面図及びＡ−Ａ線断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B are a plan view and a sectional view taken along line AA of a semiconductor integrated circuit showing a first embodiment of the present invention.

【０００８】図１（ａ），（ｂ）に示すように半導体集
積チップ１の主表面上には、入力信号用電極パッド２と
出力信号用電極パッド３及びＧＮＤ電源パッド４とが配
置されている。また半導体チップ１の外周部には、配線
導体１２により入力信号用電極パッド２と電気的に接続
された抵抗体接続用の第１の外部電極パッド５とＧＮＤ
電源パターン６に接続された抵抗体接続用の第２外部電
極パッド７とが隣接して配置してある。一方半導体チッ
プ１を使用して構成するシステムで必要とする入力イン
ピーダンスに整合する様に、抵抗値を調整されたチップ
抵抗８は、両端に電極端子１０を有し、第１及び第２の
外部電極パッド５，７との間にリード１１で接続されて
いる。As shown in FIGS. 1A and 1B, an input signal electrode pad 2, an output signal electrode pad 3 and a GND power supply pad 4 are arranged on the main surface of the semiconductor integrated chip 1. There is. Further, on the outer peripheral portion of the semiconductor chip 1, a first external electrode pad 5 for connecting a resistor, which is electrically connected to the input signal electrode pad 2 by a wiring conductor 12, and a GND.
The second external electrode pad 7 for connecting the resistor, which is connected to the power supply pattern 6, is arranged adjacent to the second external electrode pad 7. On the other hand, the chip resistor 8 whose resistance value is adjusted so as to match the input impedance required in the system configured by using the semiconductor chip 1 has the electrode terminals 10 at both ends, and has the first and second external terminals. The leads 11 are connected to the electrode pads 5 and 7.

【０００９】以上の様に半導体集積回路を構成する事に
より、ＥＣＬ又はＣＭＬ回路で構成された半導体集積回
路の入力端に高精度の終端抵抗が配置された事になり、
高速演算に必要なインピーダンス整合を企る事が出来
る。なお抵抗体接続用第１の外部電極パッド５との接続
を入力信号用電極パッドの代わりに出力信号用電極パッ
ドに代えた場合でも同様である。By configuring the semiconductor integrated circuit as described above, a highly accurate terminating resistor is arranged at the input end of the semiconductor integrated circuit configured by the ECL or CML circuit.
The impedance matching required for high speed calculation can be attempted. The same applies to the case where the connection with the first external electrode pad 5 for resistor connection is replaced with the output signal electrode pad instead of the input signal electrode pad.

【００１０】図２（ａ），（ｂ）は本発明の第２の実施
例を示す半導体集積回路の平面図及びＢ−Ｂ線断面図で
ある。2A and 2B are a plan view and a sectional view taken along line BB of a semiconductor integrated circuit showing a second embodiment of the present invention.

【００１１】第１の実施例と同様の半導体チップ１Ａを
準備する。チップ１Ａの外周部の第１及び第２の外部電
極パッド５Ａ，７Ａに１：１に対応する様に配備したＴ
ＡＢリード１４を有するポリイミドテープ１３上におい
て、第１及び第２の外部電極パッド５Ａ，７Ａに対応す
るＴＡＢリード１４の間に薄膜抵抗１５を第１の実施例
と同様に所望の抵抗値に対し高精度に形成する。更に半
導体チップ１Ａの外周部の各外部電極パッド５Ａ，７Ａ
とポリイミドテープ１３上のＴＡＢリード１４の先端を
熱圧着で接続して、半導体集積回路を構成する。A semiconductor chip 1A similar to that of the first embodiment is prepared. The T arranged to correspond 1: 1 to the first and second external electrode pads 5A and 7A on the outer peripheral portion of the chip 1A
On the polyimide tape 13 having the AB leads 14, a thin film resistor 15 is provided between the TAB leads 14 corresponding to the first and second external electrode pads 5A and 7A with respect to a desired resistance value as in the first embodiment. Form with high precision. Further, each external electrode pad 5A, 7A on the outer peripheral portion of the semiconductor chip 1A
And the tips of the TAB leads 14 on the polyimide tape 13 are connected by thermocompression bonding to form a semiconductor integrated circuit.

【００１２】このように構成された第２の実施例におい
ては、抵抗体として薄膜抵抗１５を用いているため薄膜
抵抗の抵抗値を５％以内のばらつきで容易に形成できる
と共に、半導体集積回路をより小さくできるという利点
がある。In the second embodiment thus constructed, since the thin film resistor 15 is used as the resistor, the resistance value of the thin film resistor can be easily formed within a variation of 5% and the semiconductor integrated circuit can be formed. It has the advantage of being smaller.

【００１３】次に第３の実施例を図３の断面図を用いて
説明する。第３の実施例は熱拡散板を用いる半導体集積
回路に本発明を適用した場合である。Next, a third embodiment will be described with reference to the sectional view of FIG. The third embodiment is a case where the present invention is applied to a semiconductor integrated circuit using a heat diffusion plate.

【００１４】まず第１の実施例と同様の半導体チップ１
Ｂを準備する。更に熱抵抗の低いＡｌＮ板１７の外周部
は絶縁膜１８，抵抗体１９電極メタライズ層２０を形成
した熱拡散板を準備する。次にＡｌＮ板１７の抵抗体１
９が存在する面の中央部に、半導体チップ１Ｂの裏面を
Ａｕ−Ｓｉ１６でダイマウントする。更に抵抗体１９上
の電極メタライズ層２０と半導体チップ１Ｂ上の第１及
び第２の外部電極５Ｂ，７Ｂを金又はＡｌのワイヤ２１
でワイヤボンディングする。以上の様にして半導体集積
回路を構成する。First, a semiconductor chip 1 similar to that of the first embodiment.
Prepare B. Further, a heat diffusion plate having an insulating film 18 and a resistor 19 electrode metallized layer 20 formed on the outer peripheral portion of the AlN plate 17 having a lower heat resistance is prepared. Next, the resistor 1 of the AlN plate 17
The back surface of the semiconductor chip 1B is die-mounted with Au—Si 16 at the center of the surface where 9 is present. Furthermore, the electrode metallization layer 20 on the resistor 19 and the first and second external electrodes 5B and 7B on the semiconductor chip 1B are connected to the wire 21 of gold or Al.
Wire bonding with. The semiconductor integrated circuit is configured as described above.

【００１５】このように構成された第３の実施例におい
ては、ＡｌＮ板１７の空いた領域に抵抗体１９を設ける
ことができるので、特に抵抗体による面積増加を考慮す
る必要はない。更に、表面平面化したＡｌＮ板を用いる
事により、チップ１の反りをダイマウント後で吸収出来
チップ１表面の平面度を改善出来、チップ主表面上の外
部電極の実装性が高められる。In the thus constructed third embodiment, the resistor 19 can be provided in the vacant region of the AlN plate 17, so that it is not necessary to consider the area increase due to the resistor. Further, by using the surface-planarized AlN plate, the warp of the chip 1 can be absorbed after die mounting, the flatness of the surface of the chip 1 can be improved, and the mountability of external electrodes on the main surface of the chip can be enhanced.

【００１６】次に第４の実施例を図４の平面図を参照し
て説明する。Next, a fourth embodiment will be described with reference to the plan view of FIG.

【００１７】半導体チップ１Ｃの主表面上に配された入
出力信号用電極パッド２２（２２ａ〜２２ｃ）と、チッ
プ外周部に配された抵抗体接続用の第１の外部電極パッ
ド５（５ａ〜５ｃ）との間の配線２３（２３ａ〜２３
ｃ）の抵抗が、設計パターン上同一になる様にした半導
体チップ１Ｃを準備する。この半導体チップ１Ｃと第１
〜第３の実施例で示した抵抗体を第１〜第３の実施例の
如くに接続して終端抵抗付半導体集積回路を構成する。The input / output signal electrode pads 22 (22a to 22c) arranged on the main surface of the semiconductor chip 1C and the first external electrode pads 5 (5a to 5a) for connecting the resistors arranged on the outer periphery of the chip. 5c) wiring 23 (23a-23)
A semiconductor chip 1C is prepared in which the resistance of c) is the same on the design pattern. This semiconductor chip 1C and the first
~ The resistors shown in the third embodiment are connected as in the first to third embodiments to form a semiconductor integrated circuit with a terminating resistor.

【００１８】この場合入出力信号用電極パッド２２ａ，
２２ｂ，２２ｃと、抵抗体接続用の第１の外部電極パッ
ド５ａ，５ｂ，５ｃを各々接続する配線２３ａ，２３
ｂ，２３ｃは同一の抵抗値になる様、配線長，配線幅が
設計されている。従ってこれら配線２３ａ〜２３ｃ各々
の抵抗値と終端抵抗の抵抗値の合計の値はよりばらつき
の少い（５％以内）値となるため、第１〜第３の実施例
のものに比べインピーダンス整合性がよく、歩留の高い
半導体集積回路が得られる。In this case, the input / output signal electrode pads 22a,
Wirings 23a and 23 for respectively connecting 22b and 22c and the first external electrode pads 5a, 5b and 5c for resistor connection.
The wiring length and wiring width are designed so that b and 23c have the same resistance value. Therefore, the total value of the resistance value of each of the wirings 23a to 23c and the resistance value of the terminating resistance is a value with less variation (within 5%), so that impedance matching is better than that of the first to third embodiments. It is possible to obtain a semiconductor integrated circuit having good performance and high yield.

【００１９】第１〜第３の実施例においては、外付け抵
抗の抵抗値を、チップ主表面上の入出力信号用電極パッ
ドと抵抗体接続用の外部電極パッド間の配線抵抗との合
計値で調整できるため、１ｎｓ以下のクロック周波数で
の高速演算で必要とされる５％以内でのインピーダンス
整合が容易になる。In the first to third embodiments, the resistance value of the external resistor is the total value of the wiring resistance between the input / output signal electrode pad on the main surface of the chip and the external electrode pad for resistor connection. The impedance matching within 5%, which is required for high-speed calculation with a clock frequency of 1 ns or less, is facilitated because it can be adjusted by

【００２０】また第４の実施例においては、入出力信号
用電極パッドと抵抗体接続用の外周部電極パッド間の配
線抵抗ばらつきを５％以内にする事が容易である為、外
付け抵抗の値を一定にする事が出来る。Further, in the fourth embodiment, it is easy to make the wiring resistance variation between the input / output signal electrode pad and the outer peripheral electrode pad for connecting the resistor within 5%. The value can be constant.

【００２１】[0021]

【発明の効果】以上説明したように本発明は、入出力信
号用電極パッドと、電源用電極パッドの間に抵抗値のば
らつきを高精度で抑えた外付け抵抗を具備する事によ
り、インピーダンス整合を高精度で合せる事が出来、Ｅ
ＣＬ又はＣＭＬ回路を使用した高速演算が可能な半導体
集積回路が得られるという効果を有する。As described above, according to the present invention, the impedance matching is achieved by providing the external resistor between the input / output signal electrode pad and the power supply electrode pad with highly accurate variation in resistance value. Can be matched with high precision, and E
This has the effect of obtaining a semiconductor integrated circuit capable of high-speed calculation using a CL or CML circuit.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施例の平面図及び断面図。FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.

【図２】本発明の第２の実施例の平面図及び断面図。FIG. 2 is a plan view and a sectional view of a second embodiment of the present invention.

【図３】本発明の第３の実施例の断面図。FIG. 3 is a sectional view of a third embodiment of the present invention.

【図４】本発明の第４の実施例の平面図。FIG. 4 is a plan view of the fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１，１Ａ〜１Ｃ 半導体チップ ２ 入力信号用電極パッド ３ 出力信号用電極パッド ４ ＧＮＤ電源パッド ５，５Ａ，５Ｂ，５ａ〜５ｃ 第１の外部電極パッド ６ ＧＮＤ電源パターン ７，７Ａ 第２の外部電極パッド ８ チップ抵抗 ９ 層間絶縁膜 １０ 電極端子 １１ リード １２ 配線導体 １３ ポリイミドテープ １４ ＴＡＢリード １５ 薄膜抵抗 １６ Ａｕ−Ｓｉ １７ ＡｌＮ板 １８ 絶縁膜 １９ 抵抗体 ２０ 電極メタライズ層 ２１ ワイヤ ２２ 入出力信号用電極パッド ２３ 配線 1, 1A to 1C Semiconductor chip 2 Input signal electrode pad 3 Output signal electrode pad 4 GND power supply pad 5, 5A, 5B, 5a to 5c First external electrode pad 6 GND power supply pattern 7, 7A Second external electrode Pad 8 Chip resistance 9 Interlayer insulation film 10 Electrode terminal 11 Lead 12 Wiring conductor 13 Polyimide tape 14 TAB lead 15 Thin film resistance 16 Au-Si 17 AlN plate 18 Insulation film 19 Resistor 20 Electrode metallized layer 21 Wire 22 Input / output signal electrode Pad 23 wiring

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 素子が形成された半導体チップの外周部
に設けられ入出力信号用電極パッドに配線導体により接
続された第１の外部電極パッドと、この第１の外部電極
パッドに隣接して設けられ電源用電極パッドに接続され
た第２の外部電極パッドと、前記第１の外部電極パッド
と前記第２の外部電極パッドとの間に接続された外部接
続端子付の抵抗体とを含むことを特徴とする半導体集積
回路。1. A first external electrode pad provided on an outer peripheral portion of a semiconductor chip on which an element is formed and connected to an input / output signal electrode pad by a wiring conductor, and adjacent to the first external electrode pad. A second external electrode pad provided and connected to the power supply electrode pad; and a resistor with an external connection terminal connected between the first external electrode pad and the second external electrode pad A semiconductor integrated circuit characterized by the above. 【請求項２】 抵抗体の抵抗値と入出力信号用電極パッ
ドと第１の外部電極パッド間の配線導体の抵抗値の合計
の値が規定の範囲内になるように抵抗体が選択されてい
る請求項１記載の半導体集積回路。2. The resistor is selected so that the total value of the resistance of the resistor and the resistance of the wiring conductor between the input / output signal electrode pad and the first external electrode pad is within a specified range. The semiconductor integrated circuit according to claim 1, wherein
JP3318761A 1991-12-03 1991-12-03 Semiconductor integrated circuit Expired - Lifetime JP2677087B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3318761A JP2677087B2 (en) 1991-12-03 1991-12-03 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3318761A JP2677087B2 (en) 1991-12-03 1991-12-03 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH0613438A JPH0613438A (en) 1994-01-21
JP2677087B2 true JP2677087B2 (en) 1997-11-17

Family

ID=18102648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3318761A Expired - Lifetime JP2677087B2 (en) 1991-12-03 1991-12-03 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2677087B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2434537B1 (en) 2004-05-18 2017-08-30 Nippon Telegraph And Telephone Corporation Electrode pad on conductive semiconductor substrate

Also Published As

Publication number Publication date
JPH0613438A (en) 1994-01-21

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