JPH0828392B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly to a mounting structure of a high speed operation integrated circuit represented by a GaAs integrated circuit.

(Prior Art) GaAs integrated circuits are known as semiconductor integrated circuits that perform high-speed theoretical operation. In recent years, GaAs MESFETs have been integrated to achieve high-speed operation with a switching speed of 100 psec. However, when an integrated circuit chip that performs such a high-speed operation is mounted in a conventional package, there is a problem that the high-speed performance obtained by the chip alone cannot be obtained.
The cause of the performance deterioration is how to make a matching termination of the wiring part where a high-speed input signal enters and the effect of the bonding wire. Let's take a closer look at these issues.

When a high-speed input signal is supplied to the MESFET of the signal input section of the GaAs logic integrated circuit through signal wiring, signal reflection at the gate section of the MESFET causes waveform distortion, which interferes with normal logic operation. In order to prevent this, it is necessary to provide a matching resistor and terminate. For example, it is conceivable to mount a GaAs logic integrated circuit chip using an ordinary package and provide a terminating resistor at a lead terminal which is a signal input terminal. FIG. 8 shows an equivalent circuit when such termination is performed. Reference numeral 11 is a signal input wiring outside the package, 12 is a package, 13 is an input terminal MESFET of an integrated circuit chip mounted in this package, and 14 is a terminating resistor. However, in a high-speed integrated circuit with a switching speed of 100 psec or less, even if a terminating resistor is provided outside the package, the problem cannot be completely solved. Input terminal MESF inside the package from the matching end point A
This is because the wiring to the point B of the ET gate terminal becomes an open stub, which causes ringing of the input signal. To avoid this, it is necessary to mount the matching resistor inside the package near the integrated circuit chip.
Specifically, a method of providing a terminating resistor in the package by thick film printing, a method of disposing a chip resistor, or the like can be considered. However, it is usually difficult to form a resistor by thick film printing in a package having a step inside. Also, mounting the chip resistor requires a large space in the package, which is also not preferable.

As a method of taking a terminating resistance different from that shown in FIG. 8, there is a method called a feedthrough shown in FIG. This is the signal wiring from point A of the package input terminal
The gate terminal B of 13 is passed through to the other terminal C of the package, and a terminating resistor 14 is provided at this terminal C. In this method, the open stub length is shorter than in the method shown in FIG. 8, but the number of signal input wirings in the package is simply doubled. Therefore, if the degree of integration of the integrated circuit is further improved, the number of input terminals is increased, and the density of the bonding pads is increased, the wiring inside the package becomes difficult.

A problem common to the schemes of FIGS. 8 and 9 is that of wire bonding. When the package internal wiring and the terminals on the integrated circuit chip are connected by bonding, the bonding wires that are normally connected in an arc are ignored as open stubs in integrated circuits that perform high-speed signal processing at gigabit / sec. It becomes a length that can not be. Moreover, the variation impairs the uniformity of characteristics. As integrated circuits become more highly integrated and the density of bonding pads becomes higher, the bonding tool will not be able to make contact with adjacent wires, and the size and pitch of the bonding pads cannot be reduced to some extent. Moreover, there is a problem that the integrated circuit chip size cannot be made too small and the signal wiring length on the chip cannot be shortened.

(Problems to be Solved by the Invention) As described above, in the normal semiconductor integrated circuit mounting structure,
When operating at high speed like a GaAs logic integrated circuit, there was a problem that the high speed performance could not be sufficiently obtained.

An object of the present invention is to provide a semiconductor integrated circuit device that solves such problems.

[Structure of the Invention] (Means for Solving Problems) In the present invention, TAB (Tap
e Automated Bonding) method is adopted. TAB board is
A hole is made in a portion of the tape-shaped resin film on which the integrated circuit chip is mounted, and a plurality of lead wirings having a tongue protruding in the hole portion are radially arranged. This TA
The tongue piece is directly connected to the terminal portion of the integrated circuit chip on the B board to mount the integrated circuit chip. This mounting method is also called a tape carrier or a film carrier.
In such a TAB type integrated circuit structure, the present invention provides a feed-through wiring in which the lead wiring portion connected to the high-speed signal input terminal of the integrated circuit chip among the lead wiring on the resin film is adjusted to a predetermined characteristic impedance. It is characterized in that it is a folded wiring constituting the.

(Operation) By using the TAB substrate as described above, the length of the above-mentioned open stub becomes extremely short, the variation in the length is small, and the waveform distortion of the high-speed input signal can be sufficiently reduced. Also, since the tongue piece that is a part of the lead wiring on the TAB substrate is directly connected to the terminal pad of the integrated circuit chip,
Eliminates the need for wire bonding when using conventional packages. As a result, restrictions on the size and pitch of the terminal pads on the integrated circuit chip are relaxed, and the integrated circuit chip can be made smaller. As a result, the wiring length on the integrated circuit chip can be shortened. Also, the length of the open stub is smaller and more uniform than the bonding wire.

Further, since the lead wiring on the TAB substrate is formed by using the photo-etching technique, the wiring width and spacing can be set sufficiently small and highly accurate as compared with the lead wiring in the ceramic package. Therefore, the feedthrough wiring can be easily realized even for an integrated circuit having a large number of input terminals.

(Example) Hereinafter, the Example of this invention is described.

FIG. 1 is a plan view showing a GaAs integrated circuit mounting structure of an embodiment of the present invention. GaAs integrated circuits are specifically GaAsME
It is a multiplexer that uses SFET and operates at high speed with a switching speed of 100 psec or less. FIG. 2 is an enlarged plan view of the integrated circuit chip mounting area a of FIG. 1, and FIGS. 3 (a) and 3 (b) are plan views of the essential portion of FIG.
It is a -A 'sectional view. FIG. 4 is a plan view and a cross-sectional view of the external connection terminal area b on the TAB substrate of FIG.

The TAB substrate is a resin film 1 such as polyimide or glass epoxy, on which lead wirings are formed by photo-etching. Usually, as shown in FIG. 5, a repeated wiring pattern is formed on a long tape-shaped film, and integrated circuit chips are mounted one after another on this. FIG. 1 shows the one-chip mounting portion and the lead wiring portion around it. That is, a hole 9 is opened in the integrated circuit chip mounting portion of the resin film 1, and the GaAs integrated circuit chip 6 is mounted therein. The lead wiring on the resin film 1 is a Cu pattern radially formed from the integrated circuit chip mounting portion.
It is a film, and a part of the lead wiring protrudes as a tongue piece at the hole 9 portion, and this tongue piece is directly connected to the terminal pad on the integrated circuit chip 6.

Of the lead wiring on the TAB substrate, focusing on the signal input wiring portion connected to one input terminal of the integrated circuit chip 6,
As shown in FIG. 1, there are lead wires 2 ₁ to form the forward path from the external connection terminal portions 2 ₄ on the TAB board to the vicinity of the integrated circuit chip 6, the return which is folded in the vicinity integrated circuit chip 6 External connection terminal part through the lead wiring 2 ₂ to be formed
It is a return wiring that returns to 2 ₄ . The folded wiring constitutes a feedthrough wiring for the input terminal of the chip 6. The external connection terminal parts 2 _4, to be connected to the signal input terminal IN of the board mounting the integrated circuit. And for example, an external connection terminal portion 2 ₅ of the folding line 2 ₂ is connected to the terminal potential V _TT via the termination resistor R. In this embodiment, the lead wirings 2 ₁ and 2 ₂ are attached to the portions shown in FIG.
As shown in FIG. 4, a composite structure of a microstrip transmission line structure and a coplanar transmission line structure, that is, a grounded coplanar transmission line structure (or a coplanar microstrip transmission line structure) is adopted. That is, lead wiring
2 ₁ and 2 ₂ have a constant line width d ₁ and ground conductors 4 are arranged on both sides of the space 3 ₁ and 3 ₂ with a constant spacing d ₂ to form a coplanar transmission line. A ground conductor 5 is also formed on the back surface of the resin film 1 to form a microstrip transmission line. As shown in FIG. 4, the ground conductor 5 on the back surface is provided on the entire surface of the TAB substrate inside the point E except for the external terminal area. Inside than this point E in this manner, the line width also draw concentric described bending portion d ₁ and line spacing d ₂ is kept constant, the characteristic impedance forms a constant gland coplanar transmission line . From the vicinity of the integrated circuit chip where the lead wires 2 ₂ and 2 ₂ draw an arc,
A tongue piece 2 ₃ made of the same Cu film as 2 ₁ and 2 ₂ projects inward, and this tongue piece 2 ₂ is directly connected to the bump electrode 8 of the input terminal pad 7 of the integrated circuit chip 6.

The bump electrode 8 is usually made of Ti-Ni-Pd, Ti-W-Au, Ti-Pt.
It is formed by Au plating through a barrier metal layer such as -Au or Cr-Cu-Au. If wiring tongue 2 ₃ contrast a Cu layer, preliminarily subjected to Sn plating or Au plating thereto.
To joining such tongue 2 ₃ and the bump electrodes 8, 350
A tool of ~ 500 ° C is pressed to the joint with 30 ~ 80g / lead, and eutectic bonding (in case of Au-Sn) or thermocompression bonding (Au-
In the case of Au). As a result, the integrated circuit chip can be easily fixed to the TAB substrate.

As is clear from FIG. 1, in this embodiment, the power supply potential is
V _DD and V _SS terminals, 6 input terminals IN _{1 to} IN ₆ , 4 output terminals OUT _{1 to} OUT ₄ , 3 potential monitoring terminals,
Corresponding to each of the input terminals IN _{1 to} IN ₆ , there is a terminal connected to the terminal potential V _TT via the terminal resistor R.

A specific numerical example of the lead wiring design will be described. For example, EC
In a GaAs logic integrated circuit having an interface compatible with the L circuit, the input signal wiring must have a characteristic impedance of 50%.
Ω and a terminating resistance of 50Ω. Now, assuming that the resin film 1 has a thickness of 75 μm and a relative dielectric constant of about 3.2,
A characteristic impedance of 50Ω can be obtained by setting the line width of the lead wires 2 ₁ and 2 ₂ to 50 μm and the distance between these wires and the ground conductor 4 to 30 μm.

According to this embodiment, by forming the feedthrough wiring on the TAB substrate, it is possible to easily form the signal input wiring having a constant characteristic impedance even in the case of an integrated circuit having a large number of signal input terminals. Unlike the ceramic package, the lead wiring is formed by photo-etching on the TAB substrate, so that a wiring having a small line width and a small line spacing can be obtained easily and with good controllability. Therefore, it is possible to easily cope with an increase in the number of input terminals and an increase in the density of the integrated circuit. Further, since wire bonding is not used, the open stub is reduced, distortion of the signal waveform is suppressed, and the uniformity of the open stub length is also improved. As a result, the high-speed performance of the GaAs logic integrated circuit chip is fully exhibited. . Not using wire bonding also means that the size and spacing of the terminal pads on the integrated circuit chip can be reduced, which results in a smaller integrated circuit chip and shorter internal wiring length. As a result, the integrated circuit can be further speeded up and highly integrated.

The manufacturing method of the embodiment described with reference to FIGS. 1 to 5 is as follows, for example. First, perforations are formed in a 35 mm wide resin film such as a hole for an integrated circuit chip mounting portion, and a Cu foil with a thickness of 18 μm is attached to the back surface with a polyimide adhesive. Next, the Cu foil on the back surface is processed into a predetermined pattern by photoetching. After this, a Cu foil with a thickness of 18 μm is also attached to the surface in the same manner. Then, the back surface is covered with a photoresist, a photoresist having a predetermined pattern is formed on the surface, and photoetching is performed to form a wiring pattern, and the photoresist on the front and back surfaces is removed.

The present invention is not limited to the above embodiment. For example, in the embodiment, the structure of the input wiring portion on the TAB substrate is a composite structure of a coplanar transmission line structure and a microstrip transmission line structure, but any one structure is also effective. FIGS. 6 (a) and 6 (b) show the structure of the embodiment in which only the coplanar transmission line structure is applied, corresponding to FIGS. 3 (a) and 3 (b). In FIGS. 6 (a) and 6 (b), the ground conductor 4 has no hollow portion in the ground conductor 4 unlike the embodiment shown in FIGS. 3 (a) and 3 (b). Such a structure is shown in FIGS.
It is also applicable to the embodiment shown in. FIGS. 7 (a) and 7 (b) show the structure of the embodiment when only the microstrip transmission line structure is applied, corresponding to FIGS. 3 (a) and 3 (b).

The terminating resistor is placed outside the TAB substrate on the integrated circuit mounting board, or in the form where the lead wiring forming the folded wiring on the TAB substrate is cut at an appropriate place after folding,
A thick film resistor, a chip resistor, or the like may be arranged with the tongue portion side end as one connection end and the ground conductor connected to the termination potential as the other connection end. In the embodiment, the terminating other potential V _TT is provided separately from one of the power source potentials V _SS , but it may be a common ground potential depending on the integrated circuit. In the embodiment, high-speed GaAs with integrated MESFET is also used.
Although the logic integrated circuit is taken as an example, the present invention can be similarly applied to other high speed integrated circuits.

[Effects of the Invention] As described above, according to the present invention, it is possible to easily cope with the increase in the number of input terminals and the increase in density by applying the TAB method and forming the feedthrough wiring on the TAB substrate. Thus, a semiconductor integrated circuit can be obtained in which the high speed performance of the chip can be sufficiently exhibited.

[Brief description of drawings]

FIG. 1 is a plan view showing the structure of a GaAs logic integrated circuit according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of its chip mounting area, and FIGS. 3 (a) and 3 (b) are further shown in FIG. FIG. 4 (a) and FIG. 4 (b), which is an enlarged plan view of a main part and a sectional view taken along the line AA ′.
1 is an enlarged plan view showing the external terminal area of FIG. 1 and its AA ′ sectional view, FIG. 5 is a plan view showing the structure of the TAB substrate, and FIGS. 6 (a) and 6 (b) are other views. The figure which shows the structure of an Example corresponding to FIG.3 (a) (b), FIG.7 (a) (b)
Shows the configuration of still another embodiment in correspondence with FIGS. 3 (a) and 3 (b), and FIGS. 8 and 9 are diagrams showing the conventional way of taking matching terminations in an equivalent circuit manner. 1 ... Resin film, 2 ₁ , 2 ₂ ...... Lead wiring (feed-through wiring), 2 ₃ ...... Tongue piece, 2 ₄ , 5, ₅ …… External connection terminal part, 3 ₁ , 3 ₂ …… Space, 4 , 5 ... Ground conductor, 6 ... GaAs integrated circuit chip, 7 ... Bonding pad, 8 ... Bump electrode, 9 ... Hole.

Claims (4)

[Claims] 1. A resin film in which a hole is provided in an integrated circuit chip mounting portion and a plurality of lead wirings radially arranged having a tongue protruding in the hole portion are formed, and the resin film. A semiconductor integrated circuit device mounted on the chip mounting part, the tongue piece being directly connected to a bonding pad, wherein the integrated circuit chip among the lead wirings on the resin film 2. The semiconductor integrated circuit device according to claim 1, wherein the lead wiring connected to the high-speed signal input terminal is a folded wiring that constitutes a feedthrough wiring adjusted to a predetermined characteristic impedance. 2. The semiconductor integrated circuit device according to claim 1, wherein the folded wiring portion forming the feed-through wiring forms a microstrip transmission line in which a ground conductor is formed on the back surface of the resin film. 3. A folded wiring portion constituting the feed-through wiring constitutes a coplanar transmission line in which a ground conductor is formed on the same surface as the folded wiring on the resin film at a predetermined distance from the folded wiring. The semiconductor integrated circuit device according to claim 1. 4. The folded wiring portion forming the feed-through wiring has a ground conductor formed on the same surface as the folded wiring on the resin film at a predetermined interval between the folded wiring and the ground on the back surface of the resin film. A first coplanar transmission line with a ground on which a conductor is formed.
The semiconductor integrated circuit device according to the paragraph.