JPH0544190B2 - - Google Patents

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Publication number
JPH0544190B2
JPH0544190B2 JP1242082A JP24208289A JPH0544190B2 JP H0544190 B2 JPH0544190 B2 JP H0544190B2 JP 1242082 A JP1242082 A JP 1242082A JP 24208289 A JP24208289 A JP 24208289A JP H0544190 B2 JPH0544190 B2 JP H0544190B2
Authority
JP
Japan
Prior art keywords
ceramic
multilayer circuit
circuit board
thermal expansion
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1242082A
Other languages
Japanese (ja)
Other versions
JPH02119164A (en
Inventor
Nobuyuki Ushifusa
Koichi Shinohara
Kosei Nagayama
Satoru Hagiwara
Tasao Soga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1242082A priority Critical patent/JPH02119164A/en
Publication of JPH02119164A publication Critical patent/JPH02119164A/en
Publication of JPH0544190B2 publication Critical patent/JPH0544190B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 本発明は、新規なセラミツクス多層回路基板に
係り、特にキヤリア基板上に搭載した半導体素子
を更にセラミツクス多層回路板に搭載した半導体
モジユールに関する。また特に、多層回路板に導
電性の良い銅または銀導体が使用でき、しかも半
導体素子のはんだ接続部の信頼性が良い半導体モ
ジユール構造に関する。 〔従来の技術〕 大型電子計算機の演算速度の高速化には、半導
体素子とそれを実装する系での信号伝播速度の高
速化が必要である。近年、半導体素子は、高集積
技術の発達により大幅な高速高集積化が実現し、
実装技術が演算速度の高速化に大きな影響を与え
るようになつてきている。実装技術としては、半
導体素子を高密度に実装し、電気信号の遅延を小
さくするために、セラミツクス多層回路基板が用
いられるようになつた。従来よりセラミツクス多
層回路基板の絶縁材料としては、一般にアルミナ
が使用されている。しかし、さらに高性能化する
ために、近年、特公昭59−22399号「多層セラミ
ツクス基板」に記載されているような低温焼結基
板材料や、特開昭59−11700号「セラミツクス多
層配線回路板」に記載されているようなSiO2
ガラスで結合した低誘電率・低温焼結材料が研究
開発されている。これらの回路板材料は、内部に
できるだけ気孔を含まないように緻密に焼結させ
たものであるが、演算速度の高速化に大きな影響
を及ぼす比誘電率は、4〜5程度が限界であつ
た。 また、従来より断熱・保温性、軽量化、防音な
どの目的で、例えば、特開昭57−89212号「複合
セラミツクス電子材料」や特開昭59−83985号
「発泡セラミツクス板の製造方法」に記載されて
いるようにセラミツクス内部に気孔を含んだ基板
が得られている。しかし、信号伝播速度の高速化
が要求される大型電子計算機の基板材料として
は、配慮がなされていなかつた。 一方、半導体素子は、高速化、高密度化に伴つ
て、放熱や素子の高速化を計るためにセラミツク
ス多層回路基板上に直接半導体素子を実装する方
式が用いられるようになつてきている。しかしな
がら、この実装方式においては、半導体素子のサ
イズが大きくなるにつれて、半導体素子材料とセ
ラミツクス多層配線回路基板材料との間で実装時
の温度変化によつて生ずる応力が大きくなるとい
う問題があつた。そのため、セラミツクス多層配
線回路基板材料の熱膨張係数を半導体素子のそれ
に近づけようとしていた。しかし、配線導体材料
として抵抗が小さい金、銅又は銀などを高密度配
線するためには、セラミツクス絶縁材料の熱膨張
係数をこれらの導体材料に近づけなければならな
い。このように、セラミツクス絶縁材料として
は、半導体素子材料及び導体材料の熱膨張係数に
近くすることが要求されている。しかし、これら
の相反する状態での実装技術については配慮され
ていなかつた。 〔発明が解決しようとする課題〕 セラミツクス多層回路基板において、絶縁材料
の誘電率は、信号伝播速度の高速化に対してでき
るだけ小さいものが要求されている。また、導体
材料には、電気抵抗の小さい材料を用いる必要が
ある。例えば、特開昭59−11700号「セラミツク
ス多層配線回路板」に記載されているように、低
誘電率であるシリカをガラスで結合した基板材料
で、比誘電率が4〜5のものが得られている。さ
らにこの材料は1000℃以下の温度で焼成可能なた
め、導体材料として電気抵抗の小さい金、銅又は
銀などが適用可能である。また、セラミツクス多
層回路基板材料の熱膨張係数は、半導体素子のそ
れにできるだけ近づいており、導体材料のそれと
の差が大きくなつている。そのため、内部回路を
高密度に配線し、しかも半導体素子を高密度に信
頼性良く搭載することに対し、あまり配慮がなさ
れていない。 本発明の目的は、より低誘電率のセラミツクス
絶縁材料に導体材料として金、銅又は銀のような
抵抗の低い材料を高密度に配線したセラミツクス
多層回路基板を用いた半導体モジユールにおい
て、半導体素子を高密度に信頼性良く搭載するこ
とができる実装技術を提供することにある。 〔課題を解決するための手段〕 本発明は、セラミツクス層と配線導体層とを交
互に積層したセラミツクス多層回路板を有する半
導体モジユールにおいて、前記セラミツクス層は
その熱膨張係数が前記配線導体の熱膨張係数より
小さく且つ前記配線導体層の熱膨張係数の2分の
1以上であり、前記配線導体層の融点以下で軟化
するガラスよりなることを特徴とするセラミツク
ス多層回路板を有することにある。 セラミツクス層の熱膨張係数は7.2×10-6/℃
以上及び1MHzにおける比誘電率が4.5以下であ
り、前記配線導体層は金、銀又は銅のいずれかで
ある。 更に、セラミツクス多層回路板はセラミツクス
層中に粒径100μm以下の中空シリカを分散させ
ることで、より低誘電率とすることができる。中
空シリカの含有量はセラミツクス層の35〜60体積
%が好ましい。 上記目的の1つであるセラミツクス絶縁材料の
比誘電率を下げるためには、低誘電率のフイラを
ガラスで結合したものが考えられるが、低誘電率
のフイラとしては、無機材料中最も誘電率が小さ
いのがシリカであり、シリカの比誘電率は約4で
あるので比誘電率が4以下のセラミツクス絶縁材
料を作ることは従来のセラミツクスを緻密に焼結
する方法では困難である。そこで、比誘電率を4
よりさらに下げるためには、空気の比誘電率が約
1であるため、セラミツクス絶縁材料中に気孔を
含ませればよいと考えた。従来から、断熱、防音
などの目的で構造材料に気孔をたくさん含ませた
ものは知られているが、一般にこのような材料に
含まれている気孔は、数mm程度と大きく、多層回
路板には適用し難い。そこで、多層回路板に使用
するためには、内部配線が非常に高集積化され、
短絡や断線の危険があるために少なくとも気孔の
径は100μm以下に微細化する必要がある。 セラミツクス内部に気孔を含んだ絶縁材料を作
製するには、例えばセラミツクス粉末と発泡剤を
いつしよに混合し、焼成中に発泡させて気孔を含
むセラミツクスを作る方法は、内部が中空になつ
ている中空微小球をセラミツクス粉末に混合して
焼結する方法等が考えられるが、発泡剤を利用す
る方法は、均一で微細な気孔をセラミツクス中に
多数分散させるのは困難であるため、中空微小球
とセラミツクスを複合する方法を採用した。この
中空微小球は、比誘電率をできるだけ小さくする
ために、無機材料中最も誘電率の小さいシリカを
主成分とした中空のシリカ微小球を採用し、粒径
は100μm以下のものを選んだ。また、中空のシ
リカ微小球を結合するセラミツクスとしては、
金、銅又は銀などの配線導体材料の融点以下で焼
結させる必要があるので、これらの融点以下の温
度で軟化するガラス又は結晶化ガラスで結合し
た。結晶化ガラスとは、加熱すると非晶質の状態
から結晶相が析出するものであり、低温焼結性と
強度を有している。 中空のシリカ微小球としては、100μm以下程
度の微細なものが必要であるため、以下のように
して作製したものを使用した。つまりNaを含有
したシリカをスプレードライ法で中空の造粒粉と
し、これを急速加熱して中空とし、冷却後酸処
理、水洗等を行つてNa含有量を2wt%以下とし
たものを使用した。Na含有量が2wt%以下であ
れば、1000℃以下の温度では軟化現象がなく、十
分な耐熱温度を有している。 他の目的である低抵抗の導体材料を高密度に配
線するためには、セラミツクス絶縁材料を導体材
料の熱膨張係数差を小さくする必要がある。ま
た、導体材料としても、電気抵抗をできるだけ小
さくするために、純金属に近い程望ましい。すな
わち、金、銅又は銀の熱膨張係数が、各々1.44〜
10-5/℃、1.68×10-5/℃又は1.92×10-5/℃と
大きいため、応力解析の結果よりセラミツクス絶
縁材料としてもこれらの熱膨張係数の2分の1以
上でなければならない。このことより、金を導体
材料に使用する場合には、セラミツクス絶縁材料
の熱膨張係数は、7.2×10-6/℃以上でなければ
ならない。また、銅を導体材料に使用する場合に
は、セラミツクス絶縁材料の熱膨張係数は、8.4
×10-6/℃以上でなければならない。このことか
ら、従来からセラミツクス絶縁材料の熱膨張係数
を半導体素子であるシリコンに近づけようとして
いたが、高密度配線とするためには、逆に導体材
料の熱膨張係数は近いように大きくする必要があ
る。そのため、セラミツクス多層回路板として
は、熱膨張係数が比較的大きくなるため、半導体
素子であるシリコンを直接搭載することは困難で
ある。半導体素子であるシリコンを高密度に実装
するためには、新しい実装方法を考えなければな
らない。そこで、セラミツクス多層回路基板と半
導体素子の間にキヤリア基板を設け、セラミツク
ス多層回路板と半導体素子との熱膨張係数差を緩
和することを考えた。まず、半導体素子をキヤリ
ア基板にはんだバンプで直接搭載した。次に、半
導体素子とキヤリア基板の間に、はんだと同等の
熱膨張係数をもつ有機材料を主成分とする材料を
挿入した。その後、セラミツクス多層回路基板上
にはんだバンプで接続し、モジユールとした。こ
の場合、キヤリア基板とセラミツクス多層回路基
板は、はんだのみで接続されているため、その接
続部の信頼性の面から、キヤリア基板とセラミツ
クス多層回路基板の熱膨張係数は、ほぼ同じでな
ければならない。応力解析及び熱サイクル試験の
結果から、キヤリア基板とセラミツクス多層回路
基板の熱膨張係数の差は、1×10-6/℃以下でな
ければいけない。一方、半導体素子とキヤリア基
板の熱膨張係数の差による熱応力は、その間に挿
入する有機材料を主成分とする材料により緩和さ
れ、その熱膨張係数差が1×10-5/℃まで、接続
部の信頼性が保持できることを、熱サイクル試験
及び応力解析により確認した。このことにより、
半導体素子より熱膨張係数が大きいセラミツクス
多層回路基板が使用できる実装方式とすることが
できた。また、これらの接続に使用するはんだ材
料は、プロセス上、異なる融点でなければならな
い。すなわち、半導体素子とキヤリア基板の接続
に用いるはんだ材料は、キヤリア基板とセラミツ
クス多層回路板の接続に用いるはんだ材料より高
融点でなければならない。 有機樹脂中には、ゴム粒子及びセラミツクス粉
を混入することが好ましく、前者は樹脂100重量
部に対し、5〜10重量部が混入され、後者は全体
として35〜60体積%混入するのが好ましい。 前記ゴム粒子はポリブタジエン及び/またはシ
リコンゴムの1種以上、及び前記セラミツクス粉
は石英、炭化シリコン、窒化シリコン、炭酸カル
シウム、ベリリウムを含有する炭化シリコンの1
種以上からなるのが好ましい。 キヤリア基板及び多層回路板としてセラミツク
ス層は次の組成(重量%)のガラスからなるもの
が好ましい。 重量でSiO220〜95%にAl2O325%以下、
MgO15〜25%、B2O350%以下、ZnO15〜25%、
CaO10〜25%及びLi2O4〜20%の少なくとも1種
を含むものが好ましい。より具体的には次の通り
である。 (1) SiO250〜70%、Al2O315〜25%及びMgO15
〜25%。 更に、これにB2O3,K2O,P2O5,ZrO2
CaF2,AlN,Cs2O,V2O5の1種以上を5%
以下含むことができる。 (2) SiO270〜95%、Li2O4〜15、Al2O31〜10%、
K2O,MgO及びB2O3の1種以上を5%以下。 更に、これにP2O5,ZrO2,CaF2,AlN,
Cs2O,V2O5の少なくとも1種を5%以下含む
ことができる。 (3) SiO230〜50%、B2O330〜50%、CaO10〜25
%及びLa2O10〜20%。 更に、これにK2O,MgO,CaF2,P2O5
ZrO2,AlN,Cs2O及びV2O5の1種以上を5
%以下含むことができる。 (4) SiO255〜82%、B2O315〜25%、Li2O2〜15%
及びAl2O31〜10%。 更に、CaF2,P2O5,ZrO2,AlN,Cs2O,
V2O5,MgO,K2Oの1種以上を5%以下含む
ことができる。 (5) SiO255〜65%、ZnO15〜25%、Al2O3,Li2
O及びK2Oの少なくとも2種を10%以下。 更に、B2O3,CaF2,MgO,K2O,P2O5
ZrO2,AlN,Cs2O,V2O5の少なくとも1種
を5%以下含むことができる。 (6) SiO220〜30%、Li2O10〜15%、B2O340〜50
%及びCaO15〜25%。 更に、CaF2,Al2O3,K2O,P2O5,ZrO2
AlN,Cs2O,V2O5の少なくとも1種を5%以
下含むことができる。 〔作用〕 比誘電率が3.0〜4.5のセラミツクス絶縁材料
と、抵抗が小さい金、銅又は銀を主成分とする配
線導体材料を高密度配線したセラミツクス多層回
路基板は熱膨張係数が、半導体素子の熱膨張係数
より、大きいために、半導体素子とセラミツクス
多層回路基板の間にセラミツクス多層回路基板と
同等の熱膨張係数をもつキヤリア基板を設けはん
だにより接続し、かつ、半導体素子とキヤリア基
板の間に、はんだと同等の熱膨張係数をもつ有機
材料を主成分とする材料を挿入することにより、
はんだ接続部の信頼性が向上した。このように、
熱膨張係数が比較的大きいセラミツクス多層回路
基板を用いた場合でも、半導体素子を高密度でし
かも接続部の信頼性が高い実装方式が得られた。
また、半導体素子を搭載したキヤリア基板とセラ
ミツクス多層回路基板を接続しているはんだ部
で、離着が可能であり、半導体素子表面を保護す
ることができた。 〔実施例〕 以下、本発明の一実施例を説明する。なお、以
下の記載中、特に断らない限り、部とあるのは重
量部を、%とあるのは重量%を意味する。 実施例 1 平均粒径28μmの中空シリカ微小球40部に第1
表に示すガラス組成粉末(平均粒径1μm)60部
を配合し、平均重合度1000のポリビニルブチラー
ル樹脂12.5部、ブチルフタリルグリコール酸ブチ
ル4.0部、トリクロロエチレン62.0部、テトラク
ロロエチレン16.0部、n−ブチルアルコール22.0
部を加え、湿式ボールミルで8時間混合し、スラ
リを作製した。次に、攪拌真空脱気装置により、
ボールミル時に混入した気孔を除去するととも
に、適当な粘度に調節した。次に、スラリをドク
ターブレード法を用いて、シリコーン処理したポ
リエステルフイルム支持体上に0.2mmの厚さに塗
布し、乾燥炉内で溶媒を除去し、グリーンシート
を作製した。
[Industrial Application Field] The present invention relates to a novel ceramic multilayer circuit board, and more particularly to a semiconductor module in which a semiconductor element mounted on a carrier substrate is further mounted on a ceramic multilayer circuit board. In particular, the present invention relates to a semiconductor module structure in which highly conductive copper or silver conductors can be used in a multilayer circuit board, and in which the solder connections of semiconductor elements have high reliability. [Prior Art] In order to increase the calculation speed of large electronic computers, it is necessary to increase the signal propagation speed in semiconductor elements and the system in which they are mounted. In recent years, semiconductor devices have become much faster and more integrated due to the development of high-integration technology.
Implementation technology is beginning to have a significant impact on increasing the calculation speed. As for mounting technology, ceramic multilayer circuit boards have come to be used in order to mount semiconductor elements at high density and reduce delays in electrical signals. Alumina has conventionally been generally used as an insulating material for ceramic multilayer circuit boards. However, in order to further improve performance, in recent years, low-temperature sintered substrate materials such as those described in Japanese Patent Publication No. 59-22399 ``Multilayer Ceramic Substrates'' and ``Ceramics Multilayer Wiring Circuit Boards'' in JP Patent Publication No. 59-11700 have been developed. A low dielectric constant, low temperature sintered material in which SiO 2 is bonded with glass is being researched and developed. These circuit board materials are densely sintered so that they do not contain pores as much as possible, but the relative dielectric constant, which has a large effect on increasing the calculation speed, is limited to about 4 to 5. Ta. In addition, for the purpose of heat insulation, heat retention, weight reduction, soundproofing, etc., for example, JP-A No. 57-89212 "Composite Ceramic Electronic Materials" and JP-A No. 59-83985 "Method for Manufacturing Foamed Ceramic Boards" As described, a substrate containing pores inside the ceramic is obtained. However, no consideration has been given to this material as a substrate material for large electronic computers, which require high signal propagation speeds. On the other hand, as semiconductor devices become faster and more densely packed, a method of mounting semiconductor devices directly on a ceramic multilayer circuit board has come to be used in order to dissipate heat and increase the speed of devices. However, this mounting method has a problem in that as the size of the semiconductor element increases, the stress generated between the semiconductor element material and the ceramic multilayer wiring circuit board material due to temperature changes during mounting increases. Therefore, attempts have been made to bring the coefficient of thermal expansion of ceramic multilayer wiring circuit board materials closer to that of semiconductor elements. However, in order to conduct high-density wiring using gold, copper, silver, or the like having low resistance as a wiring conductor material, the coefficient of thermal expansion of the ceramic insulating material must be close to that of these conductor materials. Thus, ceramic insulating materials are required to have thermal expansion coefficients close to those of semiconductor element materials and conductor materials. However, no consideration was given to mounting techniques for these contradictory conditions. [Problems to be Solved by the Invention] In ceramic multilayer circuit boards, the dielectric constant of the insulating material is required to be as small as possible in order to increase the signal propagation speed. Furthermore, it is necessary to use a material with low electrical resistance as the conductor material. For example, as described in JP-A No. 59-11700 "Ceramics Multilayer Wiring Circuit Board", a substrate material with a dielectric constant of 4 to 5 can be obtained by bonding silica, which has a low dielectric constant, with glass. It is being Furthermore, since this material can be fired at a temperature of 1000° C. or lower, gold, copper, silver, or the like with low electrical resistance can be used as the conductive material. Furthermore, the coefficient of thermal expansion of ceramic multilayer circuit board materials is approaching that of semiconductor elements as much as possible, and the difference from that of conductor materials is increasing. Therefore, little consideration has been given to wiring internal circuits at high density and mounting semiconductor elements at high density and with high reliability. An object of the present invention is to manufacture semiconductor elements in a semiconductor module using a ceramic multilayer circuit board in which a low resistance material such as gold, copper or silver is interconnected as a conductive material in a ceramic insulating material with a lower dielectric constant in high density. The objective is to provide a mounting technology that allows high-density and reliable mounting. [Means for Solving the Problems] The present invention provides a semiconductor module having a ceramic multilayer circuit board in which ceramic layers and wiring conductor layers are alternately laminated, wherein the ceramic layer has a coefficient of thermal expansion equal to that of the wiring conductor. The present invention provides a ceramic multilayer circuit board characterized in that it is made of glass which has a coefficient of thermal expansion smaller than the coefficient of thermal expansion of the wiring conductor layer and one-half or more of the coefficient of thermal expansion of the wiring conductor layer, and which softens below the melting point of the wiring conductor layer. The thermal expansion coefficient of the ceramic layer is 7.2×10 -6 /℃
and a relative dielectric constant of 4.5 or less at 1 MHz, and the wiring conductor layer is made of gold, silver, or copper. Furthermore, the ceramic multilayer circuit board can be made to have a lower dielectric constant by dispersing hollow silica with a particle size of 100 μm or less in the ceramic layer. The content of hollow silica is preferably 35 to 60% by volume of the ceramic layer. In order to lower the dielectric constant of ceramic insulating materials, which is one of the above objectives, it is possible to combine fillers with a low dielectric constant with glass. Silica has a small dielectric constant, and the dielectric constant of silica is about 4. Therefore, it is difficult to produce a ceramic insulating material with a dielectric constant of 4 or less using the conventional method of densely sintering ceramics. Therefore, we set the relative permittivity to 4
Since the dielectric constant of air is approximately 1, it was thought that in order to further reduce the dielectric constant, it would be sufficient to include pores in the ceramic insulating material. Structural materials containing many pores have been known for the purpose of heat insulation, soundproofing, etc., but the pores contained in such materials are generally large, on the order of several millimeters, and are not suitable for multilayer circuit boards. is difficult to apply. Therefore, in order to be used in multilayer circuit boards, internal wiring must be highly integrated.
Since there is a risk of short circuits and disconnections, the diameter of the pores must be reduced to at least 100 μm or less. To create an insulating material that contains pores inside ceramics, for example, ceramic powder and a foaming agent are mixed together and foamed during firing to create ceramics that contain pores. One possible method is to mix hollow microspheres with ceramic powder and sinter it, but the method using a foaming agent is difficult to disperse a large number of uniform, fine pores in ceramics. A method of combining spheres and ceramics was adopted. In order to minimize the relative permittivity of these hollow microspheres, we selected hollow silica microspheres whose main component is silica, which has the lowest permittivity among inorganic materials, and whose particle size is 100 μm or less. In addition, as a ceramic that binds hollow silica microspheres,
Since it is necessary to sinter at a temperature below the melting point of the wiring conductor material such as gold, copper, or silver, the bonding was performed using glass or crystallized glass that softens at a temperature below the melting point of these materials. Crystallized glass is a material that precipitates a crystalline phase from an amorphous state when heated, and has low-temperature sinterability and strength. Since hollow silica microspheres need to be microscopic, about 100 μm or less, those produced in the following manner were used. In other words, silica containing Na was made into a hollow granulated powder using a spray drying method, this was rapidly heated to make it hollow, and after cooling, acid treatment, water washing, etc. were performed to reduce the Na content to 2 wt% or less. . When the Na content is 2wt% or less, there is no softening phenomenon at temperatures below 1000°C, and the material has sufficient heat resistance. In order to wire low-resistance conductor materials at high density, which is another purpose, it is necessary to reduce the difference in thermal expansion coefficient between the ceramic insulating materials and the conductor materials. Furthermore, as a conductive material, it is desirable that it be as close to pure metal as possible in order to minimize electrical resistance. That is, the coefficient of thermal expansion of gold, copper or silver is 1.44 to 1.44 respectively.
10 -5 /℃, 1.68 x 10 -5 /℃ or 1.92 x 10 -5 /℃, so the stress analysis results indicate that the thermal expansion coefficient of ceramic insulation materials must be at least half of these values. . From this, when gold is used as a conductive material, the thermal expansion coefficient of the ceramic insulating material must be 7.2×10 -6 /°C or higher. In addition, when copper is used as a conductor material, the coefficient of thermal expansion of ceramic insulation material is 8.4.
Must be at least ×10 -6 /°C. For this reason, attempts have been made to make the coefficient of thermal expansion of ceramic insulating materials close to that of silicon, which is a semiconductor element, but in order to achieve high-density wiring, it is necessary to increase the coefficient of thermal expansion of conductive materials to be close to that of silicon. There is. Therefore, since the thermal expansion coefficient of a ceramic multilayer circuit board is relatively large, it is difficult to directly mount silicon, which is a semiconductor element. In order to package silicon, which is a semiconductor element, with high density, new packaging methods must be considered. Therefore, we considered providing a carrier substrate between the ceramic multilayer circuit board and the semiconductor element to alleviate the difference in thermal expansion coefficient between the ceramic multilayer circuit board and the semiconductor element. First, semiconductor elements were directly mounted on a carrier substrate using solder bumps. Next, a material mainly composed of an organic material with a coefficient of thermal expansion equivalent to that of solder was inserted between the semiconductor element and the carrier substrate. Afterwards, it was connected to a ceramic multilayer circuit board using solder bumps to form a module. In this case, the carrier board and the ceramic multilayer circuit board are connected only by solder, so the coefficients of thermal expansion of the carrier board and the ceramic multilayer circuit board must be approximately the same in order to ensure the reliability of the connection. . From the results of stress analysis and thermal cycle tests, the difference in thermal expansion coefficient between the carrier substrate and the ceramic multilayer circuit board must be 1×10 -6 /°C or less. On the other hand, the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor element and the carrier substrate is alleviated by the material whose main component is an organic material inserted between the semiconductor element and the carrier substrate. It was confirmed through thermal cycle tests and stress analysis that the reliability of the parts could be maintained. Due to this,
We were able to create a mounting method that allows the use of a ceramic multilayer circuit board, which has a larger coefficient of thermal expansion than semiconductor elements. Additionally, the solder materials used for these connections must have different melting points due to the process. That is, the solder material used to connect the semiconductor element and the carrier substrate must have a higher melting point than the solder material used to connect the carrier substrate and the ceramic multilayer circuit board. It is preferable to mix rubber particles and ceramic powder into the organic resin, and the former is preferably mixed in an amount of 5 to 10 parts by weight per 100 parts by weight of the resin, and the latter is preferably mixed in a total amount of 35 to 60% by volume. . The rubber particles are one or more of polybutadiene and/or silicone rubber, and the ceramic powder is one or more of silicon carbide containing quartz, silicon carbide, silicon nitride, calcium carbonate, and beryllium.
Preferably, it consists of more than one species. The ceramic layer for the carrier substrate and multilayer circuit board is preferably made of glass having the following composition (% by weight). SiO2 20-95% and Al2O3 not more than 25% by weight,
MgO15~25%, B2O3 less than 50%, ZnO15~ 25 %,
Preferably, it contains at least one of 10 to 25% CaO and 4 to 20% Li2O . More specifically, it is as follows. (1) SiO 2 50-70%, Al 2 O 3 15-25% and MgO15
~twenty five%. Furthermore, B 2 O 3 , K 2 O, P 2 O 5 , ZrO 2 ,
5% of one or more of CaF 2 , AlN, Cs 2 O, V 2 O 5
May include: (2) SiO2 70-95%, Li2O4-15 , Al2O3 1-10 %,
5% or less of one or more of K 2 O, MgO and B 2 O 3 . Furthermore, P 2 O 5 , ZrO 2 , CaF 2 , AlN,
It can contain at least 5% of at least one of Cs 2 O and V 2 O 5 . (3) SiO2 30-50%, B2O3 30-50 %, CaO10-25
% and La2O10-20 %. Furthermore, K 2 O, MgO, CaF 2 , P 2 O 5 ,
One or more of ZrO 2 , AlN, Cs 2 O and V 2 O 5
% or less. (4) SiO2 55-82%, B2O3 15-25 %, Li2O2-15 %
and Al2O3 1-10 %. Furthermore, CaF 2 , P 2 O 5 , ZrO 2 , AlN, Cs 2 O,
It can contain 5% or less of one or more of V 2 O 5 , MgO, and K 2 O. (5) SiO2 55-65%, ZnO15-25%, Al2O3 , Li2
10% or less of at least two of O and K 2 O. Furthermore, B 2 O 3 , CaF 2 , MgO, K 2 O, P 2 O 5 ,
It can contain at least 5% of at least one of ZrO 2 , AlN, Cs 2 O, and V 2 O 5 . (6) SiO2 20-30%, Li2O10-15 %, B2O3 40-50
% and CaO15-25%. Furthermore, CaF 2 , Al 2 O 3 , K 2 O, P 2 O 5 , ZrO 2 ,
It can contain at least 5% of at least one of AlN, Cs 2 O, and V 2 O 5 . [Function] Ceramic multilayer circuit boards with high-density wiring of ceramic insulating materials with a dielectric constant of 3.0 to 4.5 and wiring conductor materials whose main components are gold, copper, or silver with low resistance have thermal expansion coefficients that are similar to those of semiconductor elements. Since the coefficient of thermal expansion is larger than that of the ceramic multilayer circuit board, a carrier substrate with a coefficient of thermal expansion equivalent to that of the ceramic multilayer circuit board is provided between the semiconductor element and the ceramic multilayer circuit board, and is connected by solder. By inserting a material whose main component is an organic material with a coefficient of thermal expansion equivalent to that of solder,
Improved reliability of solder joints. in this way,
Even when a ceramic multilayer circuit board with a relatively large coefficient of thermal expansion is used, a mounting method with high density of semiconductor elements and high reliability of connection parts has been obtained.
In addition, the solder portion connecting the carrier substrate on which the semiconductor element is mounted and the ceramic multilayer circuit board can be detached and detached, and the surface of the semiconductor element can be protected. [Example] An example of the present invention will be described below. In the following description, unless otherwise specified, "part" means part by weight, and "%" means weight %. Example 1 40 parts of hollow silica microspheres with an average particle size of 28 μm were
Blend 60 parts of the glass composition powder shown in the table (average particle size 1 μm), 12.5 parts of polyvinyl butyral resin with an average degree of polymerization of 1000, 4.0 parts of butyl phthalyl glycolate, 62.0 parts of trichlorethylene, 16.0 parts of tetrachloroethylene, and n-butyl alcohol. 22.0
and mixed in a wet ball mill for 8 hours to prepare a slurry. Next, using a stirring vacuum deaerator,
Pores introduced during ball milling were removed and the viscosity was adjusted to an appropriate level. Next, the slurry was applied to a thickness of 0.2 mm on a silicone-treated polyester film support using a doctor blade method, and the solvent was removed in a drying oven to produce a green sheet.

【表】 グリーンシートを210mm角に札弾し、100℃で5
Kgf/cm2の圧力でプレス処理を行い、グリーンシ
ート上の凹凸を除去した。次に、パンチ器を用い
て、200mm角に切断し、ガイド用の穴を施こした。
その後、このガイド用の穴を利用してグリーンシ
ートを固定し、電子ビーム法により所定位置に径
0.1mmのスルーホールをあけた。さらに、金粉
末:ニトロセルロース:エチルセルロース:ポリ
ビニルブチラール:トリクロロエチレン=100:
3:1:2:23(重量比)の導体ペーストをグリ
ーンシートにあけたスルーホールを充填し、次
に、スクリーン印刷法により所定回路パターンに
したがつて上記導体ペーストを印刷する。これら
のグリーンシートをガイド用の穴の位置を合わせ
て50枚積層し、120℃で25Kgf/cm2の圧力で積層
した。次に、外形切断し、150mm角のグリーンシ
ート積層板とし、大気雰囲気焼成炉内にセツトし
た。最高温度850〜960℃で、1時間保持し焼成し
た。このようにして、120mm角、厚さ7mmのセラ
ミツクス多層回路基板を作製した。 キヤリア基板は、セラミツクス多層回路基板と
同様の方法で作製した。異なる点は、スルーホー
ル位置、配線パターン、積層枚数7枚で、焼成後
のキヤリア基板の寸法が11mm角、厚さが1mmであ
ることである。 キヤリア基板に10mm角の半導体素子(シリコ
ン)を95%鉛−5%スズはんだで接続した。次
に、キヤリア基板と半導体素子の間に、エポキシ
樹脂(EP−828)100部とポリブタジエン
(CTBN1300×9)5〜10部の混合有機物に、平
均粒径1μmの石英粉末を35〜60体積%混合した
はんだ材料と同等の熱膨張係数である材料を挿入
した。次に、コバールピンを金−ゲルマニウムろ
うで接続したセラミツクス多層回路基板上に、9
×9=81個のキヤリア基板(半導体素子を接続
し、有機材料を主成分とした材料を挿入したも
の)を60%鉛−40%スズはんだで接続し、半導体
モジユールを作製した。 作製したセラミツクス多層回路基板の特性とモ
ジユール基板におけるはんだ接続部の信頼性につ
いて第2表に示す。セラミツクス多層回路基板に
使用したセラミツクス絶縁材料は、比誘電率3.0
〜4.5(1MHz)であり、電気信号の遅延時間は5.7
〜7.0nsであつた。これは、アルミナを主成分と
したセラミツクス多層回路基板においては、比誘
電率が9.5と大きく、電気信号の遅延時間が
10.2nsであつたため、これに比べて、31〜44%高
速化ができた。また、No.20のセラミツクス多層回
路基板は、熱膨張係数が7.0〜9.0×10-6℃であつ
たため、一部の材料系で、内部配線導体材料の金
とセラミツクス絶縁材料との熱膨張係数差によ
り、内部にクラツクが発生したものがあつた。し
かし、No.21〜38のセラミツクス多層回路基板は、
熱膨張係数が8.0〜13.0×10-6/℃であるため、内
部配線導体材料である金とのマツチングが良く基
板内部にクラツクの発生は無かつた。一方、半導
体モジユールにおいては、−55℃〜150℃の熱サイ
クルを3000回繰り返しても全くはんだ接
[Table] 210mm square green sheet, heated to 100℃
Pressing was performed at a pressure of Kgf/cm 2 to remove irregularities on the green sheet. Next, using a puncher, it was cut into 200 mm square pieces and holes were made for guides.
Then, use the guide holes to fix the green sheet, and use the electron beam method to calibrate it in place.
I drilled a 0.1mm through hole. Furthermore, gold powder: nitrocellulose: ethyl cellulose: polyvinyl butyral: trichlorethylene = 100:
The through holes made in the green sheet are filled with conductor paste in a ratio of 3:1:2:23 (weight ratio), and then the conductor paste is printed according to a predetermined circuit pattern by screen printing. Fifty of these green sheets were laminated with the guide holes aligned, and laminated at 120° C. and a pressure of 25 kgf/cm 2 . Next, the outer shape was cut into a 150 mm square green sheet laminate, which was set in an atmospheric firing furnace. Firing was carried out at a maximum temperature of 850 to 960°C for 1 hour. In this way, a ceramic multilayer circuit board measuring 120 mm square and 7 mm thick was produced. The carrier substrate was manufactured in the same manner as the ceramic multilayer circuit board. The differences are the through hole position, wiring pattern, number of laminated sheets of 7, and the dimensions of the carrier board after firing are 11 mm square and 1 mm thick. A 10 mm square semiconductor element (silicon) was connected to a carrier substrate using 95% lead-5% tin solder. Next, between the carrier substrate and the semiconductor element, 35 to 60 volume percent of quartz powder with an average particle size of 1 μm was added to a mixed organic material of 100 parts of epoxy resin (EP-828) and 5 to 10 parts of polybutadiene (CTBN1300×9). A material with the same coefficient of thermal expansion as the mixed solder material was inserted. Next, 9 pins were placed on a ceramic multilayer circuit board with Kovar pins connected with gold-germanium solder.
×9=81 carrier substrates (to which semiconductor elements are connected and a material mainly composed of an organic material is inserted) were connected with 60% lead-40% tin solder to fabricate a semiconductor module. Table 2 shows the characteristics of the manufactured ceramic multilayer circuit board and the reliability of the solder joints on the module board. The ceramic insulating material used in the ceramic multilayer circuit board has a dielectric constant of 3.0.
~4.5 (1MHz), and the electrical signal delay time is 5.7
It was ~7.0ns. This is due to the large dielectric constant of 9.5 in ceramic multilayer circuit boards whose main component is alumina, and the delay time of electrical signals.
Since it was 10.2ns, the speed was increased by 31-44% compared to this. In addition, the ceramic multilayer circuit board No. 20 had a thermal expansion coefficient of 7.0 to 9.0 × 10 -6 °C, so in some material systems, the thermal expansion coefficient between gold, the internal wiring conductor material, and the ceramic insulating material Due to the difference, some cracks occurred internally. However, the ceramic multilayer circuit boards No. 21 to 38 are
Since the thermal expansion coefficient was 8.0 to 13.0×10 -6 /°C, it matched well with gold, which is the internal wiring conductor material, and no cracks were generated inside the board. On the other hand, in semiconductor modules, even after 3,000 thermal cycles from -55℃ to 150℃, no solder connection occurs.

【表】【table】

【表】 続部に断線を生じなかつた。これは、大形電子計
算機に要求されている寿命を十分に満足するもの
であつた。 実施例 2 下記の点を変更した以外は上記実施例1と同等
にして半導体モジユールを作製した。 ・ 平均重合度1000のポリビニルブチラール樹脂
の代りにポリメタクリレート樹脂を使用。 ・ ブチルフタリルグリコール酸ブチルの代りに
フタル酸ジエチルを使用。 ・ 金粉末の代りに銅粉末を使用。 ・ ポリビニルブチラールの代りにポリメタクリ
レートを使用。 ・ 大気雰囲気焼成炉の代りに窒素雰囲気焼成炉
を使用。 作製したセラミツクス多層回路基板の特性とモ
ジユール基板におけるはんだ接続部の信頼性につ
いて第3表に示す。セラミツクス多層回路基板に
使用したセラミツクス絶縁材料は、比誘電率3.0
〜4.5(1MHz)であり、電気信号の遅延時間
[Table] No breakage occurred in the continuation section. This sufficiently satisfied the life span required for large-scale electronic computers. Example 2 A semiconductor module was manufactured in the same manner as in Example 1 except for the following changes.・ Polymethacrylate resin is used instead of polyvinyl butyral resin with an average degree of polymerization of 1000. - Use diethyl phthalate instead of butyl phthalyl glycolate.・Using copper powder instead of gold powder. - Polymethacrylate is used instead of polyvinyl butyral. - A nitrogen atmosphere firing furnace is used instead of an atmospheric firing furnace. Table 3 shows the characteristics of the manufactured ceramic multilayer circuit board and the reliability of the solder joints on the module board. The ceramic insulating material used in the ceramic multilayer circuit board has a dielectric constant of 3.0.
~4.5 (1MHz), the delay time of the electrical signal

【表】【table】

【表】 は5.7〜7.0nsであつた。これは、アルミナ系セラ
ミツクス多層回路基板に比べて、31〜44%高速化
ができた。また、No.39,48,54及び55のセラミツ
クス多層回路基板は、熱膨張係数が内部配線導体
材料である銅の熱膨張係数の0.5倍以下のものが
一部の材料系で存在し、とセラミツクス絶縁材料
とのマツチングがとれず、クラツクの発生したも
のがあつた。しかし、これら以外のセラミツクス
多層回路基板においては、クラツクの発生がなく
銅とセラミツクス絶縁材料のマツチングが良かつ
た。一方、モジユールにおいては、−55〜150℃の
熱サイクルを3000回繰り返した結果、No.44,49及
び52ではんだ接続部にクラツクが発生したものが
あり、熱サイクルを繰り返すと、断線を生じる可
能性ができた。これら以外は、はんだ接続部に変
化がなく、十分実使用に耐えうるものであること
が確認できた。 実施例 3 下記の点を変更した以外は上記実施例1及び2
と同様にしてモジユールを作製した。 ・ キヤリア基板は、グリーンシートを7枚積層
し焼成した白基板(スルーホール、配線パター
ン等がない)を11mm角に切断した。その後、レ
ーザによりφ0.1mmの穴を形成し、めつきにより
銅を穴に充填してキヤリア基板を作製した。 作製したモジユールは、実施例1及び2と同様
の結果が得られた。 実施例 4 実施例1及び2で作製したセラミツクス多層回
路基板上に、銅とポリイミドによる多層配線回路
を形成した。尚、セラミツクス多層回路基板は26
層とした。 セラミツクス多層回路基板上に、真空蒸着法に
より、厚さ0.03μmのクロム膜及び厚さ0.1μmの
銅膜を形成しあ。次に、ポジタイプフオトレジス
トを厚さ22μmまで塗布し、配線パターンを形成
した後、電解めつきによつて厚さ20μmの銅配線
層を形成した。引き続いて、ポジタイプフオトレ
ジストを厚さ22μm塗布し、層間接続パターンを
形成した後、電解めつきによつて厚さ20μmの銅
による層間接続用突起を形成した。ポジタイプフ
オトレジストを除去した後、アルゴンを用いたイ
オンミリンダにより、不要部分の銅膜及びクロム
膜をエツチング除去した。引き続いて、低熱膨張
ポリイミド系樹脂を厚さ50μmまで塗布して硬化
させ、絶縁層とした後、平面研磨によつて低熱膨
張ポリイミド系樹脂層を平坦化し、さらに泡水ヒ
ドラジン−エチレンジアミン混合液を用いたウエ
ツトエツチングにより、層間接続用突起を露出さ
せた。続いて、第一層配線と同様の方法により、
厚さ20μmの銅配線層を形成した。このようにし
て、セラミツクス多層回路基板上に銅配線層を3
層形成した。 半導体素子及びキヤリア基板は、実施例1〜3
と同様の方法により搭載し、モジユール基板を作
製した。 本実施例により製作したモジユール基板は、実
施例1〜3により作製したモジユール基板より、
信号の伝播遅延時間が約5%低減することができ
た。これは、低熱膨張ポリイミド絶縁材料の比誘
電率が3.5であることによるものである。また、
はんだ接続部の信頼性は、実施例1〜3と同等で
あつた。これは、セラミツクス多層回路基板上に
形成した銅とポリイミドの多層配線回路の厚さが
薄いため、熱膨張係数の変化が少なかつたためで
ある。 〔発明の効果」 本発明によれば、セラミツクス絶縁材料の熱膨
張係数が比較的大きいために、抵抗の小さい金、
銅又は銀を主成分とする配線導体材料が高密度に
配線することができる。また、半導体素子とセラ
ミツクス多層回路基板の間にキヤリア基板を設
け、はんだで接続し、かつ、半導体素子とキヤリ
ア基板の間にはんだと同等の熱膨張係数をもつ有
機材料を主成分とする材料を挿入することによ
り、熱膨張係数が比較的大きいセラミツクス多層
回路基板を用いた場合でも、半導体素子を高密度
でしかも接続部の信頼性がよい実装方式とするこ
とができた。
[Table] was 5.7 to 7.0 ns. This is 31 to 44% faster than an alumina ceramic multilayer circuit board. In addition, some of the ceramic multilayer circuit boards No. 39, 48, 54, and 55 have thermal expansion coefficients that are 0.5 times or less than the thermal expansion coefficient of copper, which is the internal wiring conductor material. There were some cases where cracks occurred due to poor matching with the ceramic insulating material. However, in ceramic multilayer circuit boards other than these, no cracks occurred and the matching between copper and ceramic insulating material was good. On the other hand, as a result of 3000 repetitions of heat cycles between -55 and 150°C in modules, cracks occurred in the solder connections in Nos. 44, 49, and 52, and repeated heat cycles caused wire breakage. It became possible. Other than these, there was no change in the soldered joints, and it was confirmed that the product was sufficiently durable for actual use. Example 3 Example 1 and 2 above except for the following changes.
A module was produced in the same manner as above. - The carrier board was a white board (no through holes, wiring patterns, etc.) made by laminating and firing seven green sheets and cutting it into 11 mm square pieces. Thereafter, a hole with a diameter of 0.1 mm was formed using a laser, and the hole was filled with copper by plating to produce a carrier substrate. The produced module gave similar results to Examples 1 and 2. Example 4 A multilayer wiring circuit made of copper and polyimide was formed on the ceramic multilayer circuit board produced in Examples 1 and 2. Furthermore, the ceramic multilayer circuit board is 26
layered. A chromium film with a thickness of 0.03 μm and a copper film with a thickness of 0.1 μm were formed on a ceramic multilayer circuit board by vacuum evaporation. Next, a positive type photoresist was applied to a thickness of 22 .mu.m to form a wiring pattern, and then a 20 .mu.m thick copper wiring layer was formed by electrolytic plating. Subsequently, a positive type photoresist was applied to a thickness of 22 μm to form an interlayer connection pattern, and then copper interlayer connection protrusions with a thickness of 20 μm were formed by electrolytic plating. After removing the positive type photoresist, unnecessary portions of the copper film and chromium film were etched away using an ion miller using argon. Subsequently, a low thermal expansion polyimide resin was applied to a thickness of 50 μm and cured to form an insulating layer, and then the low thermal expansion polyimide resin layer was flattened by surface polishing, and then a foamy hydrazine-ethylenediamine mixture was used. The interlayer connection protrusions were exposed by wet etching. Next, using the same method as the first layer wiring,
A copper wiring layer with a thickness of 20 μm was formed. In this way, three copper wiring layers are formed on the ceramic multilayer circuit board.
Layered. Semiconductor elements and carrier substrates are Examples 1 to 3
A module board was fabricated using the same method as above. The module substrate manufactured according to this example is different from the module substrate manufactured according to Examples 1 to 3.
The signal propagation delay time could be reduced by about 5%. This is due to the relative dielectric constant of the low thermal expansion polyimide insulating material being 3.5. Also,
The reliability of the soldered joints was equivalent to Examples 1-3. This is because the multilayer wiring circuit of copper and polyimide formed on the ceramic multilayer circuit board is thin, so there is little change in the coefficient of thermal expansion. [Effects of the Invention] According to the present invention, since the coefficient of thermal expansion of the ceramic insulating material is relatively large, gold, which has a low resistance,
A wiring conductor material containing copper or silver as a main component can be wired with high density. In addition, a carrier substrate is provided between the semiconductor element and the ceramic multilayer circuit board, which are connected by solder, and a material mainly composed of an organic material having a coefficient of thermal expansion equivalent to that of the solder is placed between the semiconductor element and the carrier substrate. By inserting it, even when using a ceramic multilayer circuit board with a relatively large coefficient of thermal expansion, it was possible to implement a mounting method that allows semiconductor elements to be mounted in high density and has good connection reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明の一実施例を示す半
導体モジユールの縦断面図である。 1,10……半導体素子、2,11……有機材
料を主成分とした材料、3,12……キヤリア基
板、4,13……はんだ、5,16……スルーホ
ール導体材料、6,17……配線導体材料、7,
18……セラミツクス絶縁材料、8,19……金
−ゲルマニウムろう、9,20……コバールピ
ン、14……ポリイミド樹脂、15……銅導体配
線材料。
1 and 2 are longitudinal sectional views of a semiconductor module showing an embodiment of the present invention. 1, 10... Semiconductor element, 2, 11... Material mainly composed of organic material, 3, 12... Carrier substrate, 4, 13... Solder, 5, 16... Through-hole conductor material, 6, 17 ...Wiring conductor material, 7,
18... Ceramics insulating material, 8, 19... Gold-germanium solder, 9, 20... Kovar pin, 14... Polyimide resin, 15... Copper conductor wiring material.

Claims (1)

【特許請求の範囲】 1 セラミツクスキヤリア基板に半導体素子を搭
載し、該基板をセラミツクス多層回路板に搭載し
てなる半導体モジユールにおいて、前記キヤリア
基板及び前記多層回路板はセラミツクス層と配線
導体層とを交互に積層させており、前記セラミツ
クス層がガラスよりなり、更に、前記セラミツク
スキヤリア基板と前記半導体素子とは、はんだバ
ンプによつて接合され、該はんだバンプが有機樹
脂によつて被われていることを特徴とする半導体
モジユール。 2 前記有機樹脂が、該樹脂100重量部に対して
5〜10重量部のゴム粒子と、全体として35〜60体
積%のセラミツクス粉とを含むことを特徴とする
特許請求の範囲第1項記載の半導体モジユール。 3 前記ゴム粒子がポリブタジエン及び/または
シリコンゴム、及び前記セラミツクス粉が石英、
炭化シリコン、窒化シリコン、炭酸カルシウム、
ベリリウムを含有する炭化シリコンの1種以上か
らなることを特徴とする特許請求の範囲第2項記
載の半導体モジユール。
[Scope of Claims] 1. A semiconductor module in which a semiconductor element is mounted on a ceramic carrier substrate, and the substrate is mounted on a ceramic multilayer circuit board, wherein the carrier substrate and the multilayer circuit board include a ceramic layer and a wiring conductor layer. The ceramic layers are alternately laminated, the ceramic layers are made of glass, and the ceramic carrier substrate and the semiconductor element are joined by solder bumps, and the solder bumps are covered with an organic resin. A semiconductor module featuring: 2. Claim 1, wherein the organic resin contains 5 to 10 parts by weight of rubber particles and 35 to 60% by volume of ceramic powder as a whole based on 100 parts by weight of the resin. semiconductor module. 3 The rubber particles are polybutadiene and/or silicone rubber, and the ceramic powder is quartz,
silicon carbide, silicon nitride, calcium carbonate,
The semiconductor module according to claim 2, characterized in that it is made of one or more types of silicon carbide containing beryllium.
JP1242082A 1989-09-20 1989-09-20 Semiconductor module Granted JPH02119164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1242082A JPH02119164A (en) 1989-09-20 1989-09-20 Semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1242082A JPH02119164A (en) 1989-09-20 1989-09-20 Semiconductor module

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP61130136A Division JPS62287658A (en) 1986-06-06 1986-06-06 Ceramic multilayered circuit board and semiconductor module

Publications (2)

Publication Number Publication Date
JPH02119164A JPH02119164A (en) 1990-05-07
JPH0544190B2 true JPH0544190B2 (en) 1993-07-05

Family

ID=17084023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1242082A Granted JPH02119164A (en) 1989-09-20 1989-09-20 Semiconductor module

Country Status (1)

Country Link
JP (1) JPH02119164A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214006A (en) * 1991-02-05 1993-05-25 Indresco Inc. Cement-free silicon carbide monoliths
TW201842008A (en) * 2017-03-15 2018-12-01 日商住友電木股份有限公司 Resin sheet, laminate resin sheet, and resin composition

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128899A (en) * 1979-03-23 1980-10-06 Ibm Method of fabricating glass ceramic structure
JPS5815264A (en) * 1981-07-21 1983-01-28 Nec Corp Multichip package
JPS5843553A (en) * 1981-09-08 1983-03-14 Nec Corp Multi-chip lsi package
JPS58137294A (en) * 1982-02-09 1983-08-15 株式会社日立製作所 Method of producing electrically mutually connecting package
JPS59107596A (en) * 1982-12-13 1984-06-21 株式会社日立製作所 Ceramic multilayer wiring circuit board
JPS6010698A (en) * 1983-06-29 1985-01-19 日本電気株式会社 Multilayer circuit board and method of producing same
JPS6027191A (en) * 1983-07-25 1985-02-12 株式会社日立製作所 Method of laminating glass ceramic multilayer circuit board

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128899A (en) * 1979-03-23 1980-10-06 Ibm Method of fabricating glass ceramic structure
JPS5815264A (en) * 1981-07-21 1983-01-28 Nec Corp Multichip package
JPS5843553A (en) * 1981-09-08 1983-03-14 Nec Corp Multi-chip lsi package
JPS58137294A (en) * 1982-02-09 1983-08-15 株式会社日立製作所 Method of producing electrically mutually connecting package
JPS59107596A (en) * 1982-12-13 1984-06-21 株式会社日立製作所 Ceramic multilayer wiring circuit board
JPS6010698A (en) * 1983-06-29 1985-01-19 日本電気株式会社 Multilayer circuit board and method of producing same
JPS6027191A (en) * 1983-07-25 1985-02-12 株式会社日立製作所 Method of laminating glass ceramic multilayer circuit board

Also Published As

Publication number Publication date
JPH02119164A (en) 1990-05-07

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