JPS61131556A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61131556A
JPS61131556A JP59253501A JP25350184A JPS61131556A JP S61131556 A JPS61131556 A JP S61131556A JP 59253501 A JP59253501 A JP 59253501A JP 25350184 A JP25350184 A JP 25350184A JP S61131556 A JPS61131556 A JP S61131556A
Authority
JP
Japan
Prior art keywords
layer
power supply
semiconductor device
electrode
condenser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59253501A
Other languages
Japanese (ja)
Inventor
Junichi Goto
順一 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59253501A priority Critical patent/JPS61131556A/en
Publication of JPS61131556A publication Critical patent/JPS61131556A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

Abstract

PURPOSE:To improve the mounting efficiency and reliability of overall system by a method wherein a condenser is formed on an electrode part of semiconductor as a pass condenser for power supply. CONSTITUTION:An earth potential layer 1 is a conventionally applicable first layer wiring while an insulating layer 2 is a polyimide resin layer to be mounted on a position of electrode whereon a power supply layer 3 is mounted. The power supply layer 3 is bonded with a bonding wire 4. a semiconductor substrate 5 is a conventionally applicable Si, GaAs substrate. In such a constitution, a condenser may be formed between the power supply layer 3 and the earth potential layer 1 to be utilized as a pass condenser for power supply. Besides, a TAB pump composing electrode may be also applicable.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に１１／Ｌ源用電極の
構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an 11/L source electrode.

〔従来の技術〕[Conventional technology]

半導体装置が高速動作をするようＫなると、それに供給
される電源のノイズ、リップルが動作に悪影響を与え、
また動作状態の急減な切替わりに対する供給電源の遅れ
による動作不良等が発生する。このため、半導体装置へ
の電源ラインにパスコンを、入れることはよく行なわれ
る手段である。As semiconductor devices operate at high speeds, noise and ripples in the power supplied to them adversely affect operation.
Furthermore, malfunctions may occur due to a delay in the power supply due to a sudden change in the operating state. For this reason, it is a common practice to insert a bypass capacitor into the power supply line to the semiconductor device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の方式は、半導体装置とパスコンとは別個のものと
いう考えにたりており、半導体装置をプリント板あるい
はハイブリッドＩＣ上に実装するときに寸法的な制約、
あるいは配線引き間しによる損失等の制約がありた。The conventional method is based on the idea that the semiconductor device and the bypass capacitor are separate entities, and there are dimensional restrictions and restrictions when mounting the semiconductor device on a printed board or hybrid IC.
Alternatively, there were limitations such as loss due to wiring thinning.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の電極は、従来、半導体装置の外側
に別部品で付けていたパスコンを半導体装置内に取り込
むもので、その電源用電極はアースポテンシャル層と弾
力性を持った絶縁層と電源層を積層した構造をもってい
る。The electrode of the semiconductor device of the present invention incorporates a bypass capacitor, which was conventionally attached as a separate component on the outside of the semiconductor device, into the semiconductor device. It has a layered structure.

この絶縁層はポンディング及びＴＡＢ接続の時の衝撃に
耐えるため、ある程度のクッシＩン性を持つポリイミド
樹脂、シリコン樹脂等から成り立っている。This insulating layer is made of polyimide resin, silicone resin, or the like having a certain degree of cushioning properties in order to withstand shocks during bonding and TAB connection.

また、容量を可変させるために、樹脂基材の酸化タンタ
ル（透電率２２）含有率を可変させることも出来る。Furthermore, in order to vary the capacity, the content of tantalum oxide (electrical conductivity 22) in the resin base material can also be varied.

また、　Ｓｉ３Ｎ４　ｏｒ８ｉ０１　　を絶縁層とする
ことも出来る。Moreover, Si3N4 or8i01 can also be used as an insulating layer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体装置の電極部にコ
ンデンサを形成することにより、従来、個別部品で取り
扱っていた電源用パスコンを半導体装置内にとり組むこ
とが出来、システム全体の実装効率、経済性の向上が計
れ、かつ部品点数減少になる信頼性向上に効果がある。As explained above, by forming a capacitor in the electrode part of a semiconductor device, the present invention enables a power supply bypass capacitor, which has conventionally been handled as an individual component, to be incorporated into the semiconductor device, improving the mounting efficiency of the entire system and making it economical. This has the effect of improving reliability by improving performance and reducing the number of parts.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の外観図である。アースポテ
ンシャル層１は従来から使用されている一層目配線であ
り、絶縁層２が電極の位置にマウントされるポリイミド
樹脂層で、その上に電源層３がマウントされる。電源層
３はボンディングワ１、　　　　　　　′ｆ″４が“′
ディ″′さ′６・半導体基板５は従来から使用されてい
るＳｉ、ＧａＡｓ基板である。FIG. 1 is an external view of one embodiment of the present invention. The earth potential layer 1 is a conventionally used first layer wiring, and is a polyimide resin layer on which an insulating layer 2 is mounted at the electrode position, and a power supply layer 3 is mounted thereon. Power supply layer 3 has bonding wire 1, 'f'4 is ''
The semiconductor substrate 5 is a conventionally used Si or GaAs substrate.

この構成をとると、電源層３とアースポテンシャル層１
０間にコンデンサが形成され、電源用パスコンとして利
用出来る。また、ＴＡＢ用バンプ構成電極でも可能であ
る。With this configuration, the power layer 3 and the earth potential layer 1
A capacitor is formed between 0 and 0, and can be used as a power supply bypass capacitor. It is also possible to use bump-forming electrodes for TAB.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例の半導体装置の電極の外観図で
ある。 １°°−−−−アースポテンシャル層、２°°°°°°
絶縁濁、３・・・・・・電源層、４・・・・・・ボンデ
ィングワイヤ、５・・・・・・半導体基板。FIG. 1 is an external view of an electrode of a semiconductor device according to an embodiment of the present invention. 1°°---Earth potential layer, 2°°°°°°
Insulating layer, 3...Power layer, 4...Bonding wire, 5...Semiconductor substrate.

Claims (1)

【特許請求の範囲】[Claims] 　半導体装置の表面において、アースポテシャル電位配
線層の上に絶縁層をおき、さらに電源層を重ねた電極を
有することを特徴とする半導体装置。1. A semiconductor device comprising an electrode in which an insulating layer is placed on a ground potential wiring layer on a surface of the semiconductor device, and a power supply layer is further stacked thereon.
JP59253501A 1984-11-30 1984-11-30 Semiconductor device Pending JPS61131556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59253501A JPS61131556A (en) 1984-11-30 1984-11-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59253501A JPS61131556A (en) 1984-11-30 1984-11-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61131556A true JPS61131556A (en) 1986-06-19

Family

ID=17252256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59253501A Pending JPS61131556A (en) 1984-11-30 1984-11-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61131556A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283459A (en) * 1990-03-30 1991-12-13 Hitachi Ltd Semiconductor integrated circuit device
EP0536972A2 (en) * 1991-10-07 1993-04-14 Maxim Integrated Products, Inc. An integrated circuit device having improved substrate capacitance isolation
JP2015130537A (en) * 2009-06-29 2015-07-16 株式会社半導体エネルギー研究所 semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283459A (en) * 1990-03-30 1991-12-13 Hitachi Ltd Semiconductor integrated circuit device
EP0536972A2 (en) * 1991-10-07 1993-04-14 Maxim Integrated Products, Inc. An integrated circuit device having improved substrate capacitance isolation
JP2015130537A (en) * 2009-06-29 2015-07-16 株式会社半導体エネルギー研究所 semiconductor device

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