TWI244715B - Semiconductor package - Google Patents

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Publication number
TWI244715B
TWI244715B TW093140361A TW93140361A TWI244715B TW I244715 B TWI244715 B TW I244715B TW 093140361 A TW093140361 A TW 093140361A TW 93140361 A TW93140361 A TW 93140361A TW I244715 B TWI244715 B TW I244715B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor
package structure
semiconductor element
semiconductor package
Prior art date
Application number
TW093140361A
Other languages
Chinese (zh)
Other versions
TW200623290A (en
Inventor
Jun-Young Yang
You-Ock Joo
Dong-Pil Jung
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093140361A priority Critical patent/TWI244715B/en
Application granted granted Critical
Publication of TWI244715B publication Critical patent/TWI244715B/en
Publication of TW200623290A publication Critical patent/TW200623290A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive

Abstract

A semiconductor package includes a semiconductor device and a passive component mounted and electrically coupled to a substrate. The passive component is disposed within a cavity portion formed on an upper surface of the substrate and the semiconductor device is disposed across the cavity portion of the substrate above the passive component.

Description

1244715 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體封裝構造，其特別有關於具有被 動元件的半導體封裝構造。 ^ 【先前技術】 半導體封裝構造一般包含具有一或多個主動元件的電 路板；僅包含單一元件之封裝構造係為眾所皆知之單一曰曰 片封裝（Single Chip Modules，SCM)，當封裝構造包含2 數個元件時稱之為多晶片封裝（Multi Chip M〇dulSes MCM)。該主動元件一般為一自砷化鍺或砷化鎵所製成之矽 晶圓，所切割出一小塊之晶片。 $ 當電子封裝構造的運作速度增加，在直流電源及接地 内的雜訊問題逐漸顯現。為了減少雜訊，被動元件如去叙 合電容器’常被用來減少電源供應之雜訊，該雜訊係因接 地電壓與供應至主動元件之電源供應電壓之間的電位差變 化而產生。該去耦合電容器在實務使用上常被置於靠近= 主動元件以加強其功效。一般而言該去耦合電容器連接^ 電源及接地係儘可能的靠近該主動元件。 一般而言，該被動元件為使用在所謂的表面接著技術之 表面接著元件（surface-mountable devices, SMD)，其中 該被動元件經由二末端接點直接連接在一基板上。然而， 在許多習用的封裝構造中，將被動元件直接安裝在基板會 造成幾個問題。首先，將被動元件設置在基板上預設位^ 將會限制基板佈線之彈性。再者，該基板面積必須隨連接 5 1244715 二其上：被動兀件的數量增加而增加’進而造成無法接受 的低封裝效率。 、根據本务明之半導體元件封裝構造可包含一個以上之 元：：該被動元件可包含有電容、電阻及電感組成之 一渡波恭以抑制雜訊並加速該晶片之運作。 【發明内容】 因此|發明之主要目的在於提供—半導體封裝構造， 八可克服或減少上述習用技術所產生的問題。 為達上述以及其他目的，具有本發明特徵的半導體元件 構k大致上包含—半導體元件及—電性連接及固定於 被動it件。該被動元件係置於該基板上表面之一凹 且該半導體元件係跨置於該基板凹槽部上並位於 ::件上方’藉此可大幅減少整體之封装厚度以增加 動亓杜#牛導體70件、该些連接線及該被 、 ；5亥基板之上表面。此外，該半導髀亓杜貪开兹由 複數個金屬凸塊連接於該基板上。 —，、σ θ 著芦藉由—絕職著層固定於該基板，該黏 半之凹槽部並且包覆該被動元件，使得該 牛導體7L件並未與該被動元件接觸。 根據本發明之另一面向，JL另姆yfit ^ it，/、另棱供一種半導體封裝構 封义構k並未有凹槽部形成於基板，且該被動元件 1244715 被=置於該半導體元件與基板上表面之間的空間内 。值得 庄思的疋，该半導體元件與基板相互間隔一預設之距離， 該距離係足以使該半導體元件避免與該被動元件相互接 觸。 【實施方式】 為了對於本發明之上述及其他特徵、優點及其他方面， 有更完整的了解’以下舉本發明—些較佳的實施例，配合 相關的圖示，作詳細說明如後。 第1圖所不為根據本發明一實施例之半導體封裝構造 100。該半導體封裝構造100包含二半導體元件11〇、12〇 及複數個電性連接及固定於一基板14〇上之被動元件 130。值得注意的是，所有的被動元件13〇皆設於該基板 140上表面之凹槽部i4〇a内，且該半導體元件11〇係跨置 於該基板140之凹槽部140a並位於該些被動元件13〇上 方，如此，可大幅減少該封裝構造1〇〇之整體厚度而增加 封裝效率。 胃 該半導體元件110藉由一黏著層或一雙面膠帶固定於該 基板140上。該黏著層可為導電體，例如，含銀之環氧樹 脂，或非導電體。該半導體元件110藉由複數條連接線ii2 連接至該基板140，該些連接線U2係作為電輸入輪出連 結至基板140上表面之第一組接點（未示於圖中），例如 位於該基板140上表面之導電線路或接墊。該半導體一 120係藉由複數個金屬凸塊（Bumps) 122機械及電性連接至 7 1244715 該基板140，該些凸塊122係作為電輸入輸出連結至基板 140上表面之第一組接點（未示於圖中）。該凸塊ι22可為 以任何習知植球方式形成於該半導體元件丨正面 (active surface)的金凸塊、錫球（s〇lder Ban)或枉狀 凸塊。 該基板140之上表面並提供有第三組接點（未示於圖中） 用以電性連結至該被動元件13〇。該第三組接點可經由數 條導電線路（未示於圖中）連接至該第一組接點，該些導 電線路可直接經由該凹槽部14〇a之側表面，自該凹槽部 140a之底部表面延伸至位於該基板14〇上表面之第一組接 點，該些導電線路亦可自該凹槽部14〇a之底部表面延伸至 該第一組接點下方的位置，並藉由基板14〇所設之專用垂 直端子，例如導孔（via)與該第一組接點連接。 *為了電性連接至一外部印刷電路板，該基板下表面設有 複數個接腳或第四組接點（未示於圖中），例如，導電線路 或接墊（pads)，並且一般設有複數個錫球（s〇lderBaU) (未示於圖中）設於該基板之該第四組接點。 請參照第1圖所示，該半導體元件110、12〇、該些連接 線112、金屬凸塊及被動元件13〇係被包覆在一封裝體15〇 内。一般而言，該封裝體15〇係藉由習知塑膠模塑方法所 开成’例如’轉移模塑（transfer molding)法。 第2圖所示為根據本發明另一實施例半導 ⑽。該半導體封輸細㈣4== 封裝構造1GG之改良，因此，第2圖之元件符號係被賦予 1244715 與第1圖相同之符號。該半導體封裝構造200之唯一差異， 在於其設有另一被動元件132於該基板140之一凹槽部 140b’且该半導體元件12〇係跨置於該基板14〇凹槽部i4〇b 且位於該被動元件132上方。 第3圖所示為根據本發明另一實施例之半導體封裝構造 300。除了該半導體元件11()係以覆晶（flip_chip)接合 而非打線（wire-bonding)接合方式連接於該基板140， 且該半導體元件120係藉由打線接合而非覆晶接合的方式 連接於該基板140之外，該半導體封裝構造3〇〇大致與第 1圖所示之半導體封裝構造1〇〇相同。 第4圖所示為根據本發明另一實施例之半導體封裝構造 400。除了另設有一被動元件132於該基板140之一凹槽部 140b，且該半導體元件120係跨置於該基板140凹槽部140b 且位於該被動元件132上方之外，該半導體封裝構造400 大致與第3圖所示之半導體封裝構造300相同。 第5圖所示為根據本發明另一實施例之半導體封裝構造 500。除了該基板140並未設有凹槽部且該被動元件130係 被設置於該半導體元件110與基板140上表面之間的空間 内之外，該半導體封裝構造500大致與第3圖所示之半導 體封裝構造300相同。值得注意的是，該半導體元件11〇 與基板140相互間隔一預設之距離，該距離係足以使該半 導體元件11〇避免與該被動元件130相互接觸。 第6圖所示為根據本發明另一實施例之半導體封裝構造 600。除了另設有一被動元件132置於該基板140之一凹槽 9 1244715 部140b且該半導體元件12()係跨置於該基板14()凹槽部 140b之被動元件丨32上方之外，該半導體封裝構造6〇〇大 致與第5圖所示之半導體封裝構造5〇〇相同。 第7圖所示為根據本發明另一實施例之半導體封裝構造 700。除了該半導體元件係藉由打線接合而非覆晶接合的方 式連接於該基板140以及該半導體元件丨1〇係藉由一絕緣 黏著層160固定於該基板14〇之外（該黏著層16〇亦填滿 該基板140之凹槽部i4〇a並且包覆該被動元件13〇，使該 半導體元件110並未與該被動元件13〇接觸），該半導體封 裝構造700大致與第2圖所示之半導體封裝構造200相同。 第8圖所示為根據本發明另一實施例之半導體封裝構造 800。在此半導體封裝構造8〇〇中，該半導體元件u〇係藉 由連接線112連接至該基板140，且該半導體元件120係 堆豐於该半導體元件11〇上。該些連接線112係分別連接 該半導體元件110之晶片銲墊（未示於圖中）與該基板140 之第一組接點（未示於圖中）。一般而言，該半導體元件 110設有一護層（passivation layer)(未示於圖中）覆 蓋於每一晶片銲墊之上緣部份，而裸露出每一晶片銲墊之 中央部分。該純化層可為一聚亞醯胺（polyimide)層、一 二氧化石夕（silicon dioxide)層、一氮化石夕（silicon nitride)層或其它習知之護層材料。在此實施例中，該半 導體元件110之正面（active surface)上設有複數條線路 (未示於圖中）用以連接至該半導體元件120。每一線路 具有一第一端部連接至該半導體元件110上之複數個晶片 1244715 銲墊之一 ’以及一第二端部藉由一金屬凸塊122連接至該 半導體元件120上之複數個晶片銲墊之一。值得注意的 是’該些被動元件13〇係皆設於該基板14〇上表面之一凹 槽部140a内且該半導體元件110係跨置於該基板140凹槽 部140a且位於被動元件13〇上方，如此，可大幅減少該封 裝體100之整體厚度而增加封裝效率。該第二半導體元件 120可包含整合被動電路元件。 第9圖所示為根據本發明另一實施例之半導體封裝構造 900。在此半導體封裝構造900中，該半導體元件110係藉 由複數個金屬凸塊122機械及電性連接至該基板14〇，且 該半導體元件120係堆疊於該半導體元件11〇上並藉由複 數條連接線112連接至該基板14 〇。在此實施例中，並未 有凹槽部形成於該基板140，且該被動元件係被設置 於該半導體元件110與基板140上表面之間的空間内。此 外，該半導體元件110與基板14〇相互間隔一預設之距離， 該距離係足以使該半導體元件11〇避免與該被動元件13〇 相互接觸。該第二半導體元件12()可包含整合被動電路元 件0 根據本發明，所有的被動元件被置於至少—半導體元件 的正下方’藉此該表面接著元件能夠盡可能被置於靠近該 主動兀件的地方。如此可大幅減少用以連接於該被動元件 與該半導體70件之間的基板導電線路，藉此增進電性效能 (由於该導電線路的阻抗、電歧雜訊係無導電線路之 長度成正tb #者，由於所有的該被動元件被置於至少一 1244715 半導體元件的正下方，本發明相較於習用將被動元件置於 半導體元件周圍的先前技術的優點在於可大幅減少所需的 面板空間而增加封裝效率。 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 12 1244715 【圖式簡單說明】 第1圖：根據本發明一實施例之半導體封裝構造之剖視圖。 第2圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 第3圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 第4圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 第5圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 第6圖··根據本發明另一實施例之半導體封裝構造之剖視 圖。 第7圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 第8圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 第9圖：根據本發明另一實施例之半導體封裝構造之剖視 圖。 主要元件符號說明 100 半導體封裝構造 110半導體元件 112連接線 122凸塊（Bumps) 120半導體元件 130被動元件 132被動元件 140基板 140a凹槽部 140b凹槽部 13 1244715 150封裝體 160黏著層 200半導體封裝構造 300半導體封裝構造 400半導體封裝構造 500半導體封裝構造 600半導體封裝構造 700半導體封裝構造 800半導體封裝構造 900半導體封裝構造 141244715 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure having a passive element. ^ [Prior art] A semiconductor package structure generally includes a circuit board with one or more active components; a package structure containing only a single component is a well-known single chip module (SCM). When the structure includes two or more components, it is called a multi-chip package (Multi Chip Module). The active device is generally a silicon wafer made from germanium arsenide or gallium arsenide, and a small piece of wafer is cut out. As the operating speed of the electronic package structure increases, noise problems in the DC power supply and ground gradually appear. In order to reduce noise, passive components such as de-synchronizing capacitors are often used to reduce the noise of the power supply, which is caused by the change in potential difference between the ground voltage and the power supply voltage supplied to the active component. This decoupling capacitor is often placed close to the active component in practical use to enhance its effectiveness. Generally speaking, the decoupling capacitor is connected as close as possible to the active component. Generally speaking, the passive device is a surface-mountable device (SMD) used in a so-called surface bonding technology, wherein the passive device is directly connected to a substrate via two terminal contacts. However, in many conventional package constructions, mounting passive components directly on a substrate causes several problems. First, setting the passive element on the substrate at a predetermined position ^ will limit the flexibility of the substrate wiring. Furthermore, the area of the substrate must be increased with the number of connections 5 1244715: the number of passive elements increases and this leads to unacceptably low packaging efficiency. 2. According to the present invention, the package structure of a semiconductor element may include more than one element: the passive element may include a wave of capacitance, resistance, and inductance to suppress noise and accelerate the operation of the chip. [Summary] Therefore, the main purpose of the invention is to provide a semiconductor package structure, which can overcome or reduce the problems caused by the conventional technology. To achieve the above and other objects, the semiconductor element structure k having the features of the present invention generally includes-a semiconductor element and-electrically connected and fixed to a passive it. The passive element is placed in a recess on the upper surface of the substrate and the semiconductor element is placed across the recessed portion of the substrate and is located above the: component, thereby greatly reducing the overall package thickness and increasing the dynamic load. 70 conductors, the connecting wires and the quilt; the upper surface of the substrate. In addition, the semiconductor device is connected to the substrate by a plurality of metal bumps. — ,, σ θ and 芦 are used to fix the substrate on the substrate, and the adhesive half groove portion covers the passive component, so that the 7L piece of bull conductor is not in contact with the passive component. According to another aspect of the present invention, JL yfit ^ it, / and another edge for a semiconductor package structure. There is no groove formed in the substrate, and the passive element 1244715 is placed in the semiconductor element. And the upper surface of the substrate. It is worth thinking about, the semiconductor element and the substrate are spaced from each other by a preset distance, which is sufficient to prevent the semiconductor element from contacting the passive element. [Embodiment] In order to have a more complete understanding of the above and other features, advantages, and other aspects of the present invention, 'the following presents some preferred embodiments of the present invention, which are described in detail with reference to related drawings. FIG. 1 is not a semiconductor package structure 100 according to an embodiment of the present invention. The semiconductor package structure 100 includes two semiconductor elements 11 and 12 and a plurality of electrical connections and a passive element 130 fixed on a substrate 14. It is worth noting that all the passive components 13 are disposed in the groove portions i4a on the upper surface of the substrate 140, and the semiconductor device 110 is straddled and located in the groove portions 140a of the substrate 140. Above the passive element 130, in this way, the overall thickness of the package structure 100 can be greatly reduced and the packaging efficiency can be increased. The stomach The semiconductor element 110 is fixed on the substrate 140 by an adhesive layer or a double-sided tape. The adhesive layer may be a conductive body, such as a silver-containing epoxy resin, or a non-conductive body. The semiconductor element 110 is connected to the substrate 140 by a plurality of connection lines ii2. The connection lines U2 are used as electrical input wheels to connect to the first set of contacts (not shown in the figure) on the upper surface of the substrate 140, such as Conductive circuits or pads on the upper surface of the substrate 140. The semiconductor 120 is mechanically and electrically connected to 7 1244715 substrate 140 through a plurality of metal bumps 122. The bumps 122 are a first set of contacts connected to the upper surface of the substrate 140 as electrical input and output. (Not shown). The bump 22 may be a gold bump, a solder ban, or a 枉 -shaped bump formed on the active surface of the semiconductor device in any conventional manner. A third group of contacts (not shown) is provided on the upper surface of the substrate 140 for electrically connecting to the passive component 13. The third group of contacts can be connected to the first group of contacts through a plurality of conductive lines (not shown in the figure), and the conductive lines can directly pass through the side surface of the groove portion 14a from the groove. The bottom surface of the portion 140a extends to a first group of contacts located on the upper surface of the substrate 140, and the conductive lines can also extend from the bottom surface of the groove portion 14a to a position below the first group of contacts. It is connected to the first group of contacts through a dedicated vertical terminal, such as a via, provided on the substrate 14. * In order to be electrically connected to an external printed circuit board, a plurality of pins or a fourth group of contacts (not shown in the figure) are provided on the lower surface of the substrate, such as conductive lines or pads, and are generally provided. There are a plurality of solder balls (not shown) (not shown) provided on the fourth set of contacts on the substrate. Referring to FIG. 1, the semiconductor devices 110, 120, the connecting wires 112, the metal bumps, and the passive device 13 are all enclosed in a package body 150. In general, the package body 15 is formed by a conventional plastic molding method, such as a transfer molding method. Fig. 2 shows a semiconductor device according to another embodiment of the present invention. The semiconductor package 4 == improvement of the package structure 1GG. Therefore, the component symbol in FIG. 2 is given the same symbol as 1244715. The only difference of the semiconductor package structure 200 is that it is provided with another passive element 132 in a groove portion 140b 'of the substrate 140, and the semiconductor element 120 is placed across the groove 14i4 of the substrate 14 and Located above the passive element 132. FIG. 3 shows a semiconductor package structure 300 according to another embodiment of the present invention. Except that the semiconductor element 11 () is connected to the substrate 140 by flip-chip bonding instead of wire-bonding, and the semiconductor element 120 is connected to the substrate 140 by wire bonding instead of flip-chip bonding. Except for the substrate 140, the semiconductor package structure 300 is substantially the same as the semiconductor package structure 100 shown in FIG. FIG. 4 shows a semiconductor package structure 400 according to another embodiment of the present invention. Except that a passive component 132 is further provided in a recessed portion 140b of the substrate 140, and the semiconductor element 120 is placed across the recessed portion 140b of the substrate 140 and above the passive element 132, the semiconductor package structure 400 is roughly This is the same as the semiconductor package structure 300 shown in FIG. 3. FIG. 5 shows a semiconductor package structure 500 according to another embodiment of the present invention. Except that the substrate 140 is not provided with a groove portion and the passive element 130 is disposed in a space between the semiconductor element 110 and the upper surface of the substrate 140, the semiconductor package structure 500 is substantially the same as that shown in FIG. The semiconductor package structure 300 is the same. It is worth noting that the semiconductor element 110 and the substrate 140 are separated from each other by a preset distance, which is sufficient to prevent the semiconductor element 110 from contacting the passive element 130 with each other. FIG. 6 shows a semiconductor package structure 600 according to another embodiment of the present invention. Except that there is another passive element 132 placed in a groove 9 1244715 portion 140b of the substrate 140 and the semiconductor element 12 () is placed over the passive element 32 of the groove portion 140b of the substrate 14 (), the The semiconductor package structure 600 is substantially the same as the semiconductor package structure 500 shown in FIG. 5. FIG. 7 shows a semiconductor package structure 700 according to another embodiment of the present invention. Except that the semiconductor element is connected to the substrate 140 by wire bonding rather than flip-chip bonding, and the semiconductor element is fixed to the substrate 14 by an insulating adhesive layer 160 (the adhesive layer 16). The groove i4a of the substrate 140 is also filled and the passive element 13 is covered so that the semiconductor element 110 is not in contact with the passive element 13). The semiconductor package structure 700 is substantially as shown in FIG. 2 The semiconductor package structure 200 is the same. FIG. 8 shows a semiconductor package structure 800 according to another embodiment of the present invention. In this semiconductor package structure 800, the semiconductor element u0 is connected to the substrate 140 through a connection line 112, and the semiconductor element 120 is stacked on the semiconductor element 110. The connecting wires 112 are respectively connected to a first set of contacts (not shown in the figure) of the wafer pad (not shown in the figure) of the semiconductor element 110 and the substrate 140. Generally, the semiconductor device 110 is provided with a passivation layer (not shown) covering the upper edge portion of each wafer pad, and the central portion of each wafer pad is exposed. The purification layer may be a polyimide layer, a silicon dioxide layer, a silicon nitride layer, or other conventional coating materials. In this embodiment, a plurality of lines (not shown) are provided on the active surface of the semiconductor element 110 for connecting to the semiconductor element 120. Each line has a first end connected to one of the plurality of wafers 1244715 on the semiconductor element 110 and a second end connected to the plurality of wafers on the semiconductor element 120 through a metal bump 122. One of the pads. It is worth noting that the passive components 13 are all disposed in a groove 140a on the upper surface of the substrate 14 and the semiconductor element 110 is placed across the groove 140a of the substrate 140 and is located in the passive component 13. Above, in this way, the overall thickness of the package body 100 can be greatly reduced and the packaging efficiency can be increased. The second semiconductor device 120 may include an integrated passive circuit device. FIG. 9 shows a semiconductor package structure 900 according to another embodiment of the present invention. In this semiconductor package structure 900, the semiconductor element 110 is mechanically and electrically connected to the substrate 14 by a plurality of metal bumps 122, and the semiconductor element 120 is stacked on the semiconductor element 11 and is formed by a plurality of The connecting lines 112 are connected to the substrate 14. In this embodiment, no recessed portion is formed in the substrate 140, and the passive element is disposed in a space between the semiconductor element 110 and the upper surface of the substrate 140. In addition, the semiconductor element 110 and the substrate 14 are separated from each other by a preset distance, which is sufficient to prevent the semiconductor element 110 from contacting the passive element 13o. The second semiconductor element 12 () may include integrated passive circuit elements. According to the present invention, all passive elements are placed at least-directly below the semiconductor element, whereby the surface-bonding element can be placed as close as possible to the active element. Place of pieces. This can greatly reduce the conductive line of the substrate used to connect between the passive component and the 70 semiconductors, thereby improving electrical performance (due to the impedance of the conductive line, the length of the non-conductive line of the electrical noise is positive tb # In addition, since all the passive elements are placed directly under at least one 1244715 semiconductor element, the present invention has the advantage over the prior art of conventionally placing the passive element around the semiconductor element in that the required panel space can be greatly reduced and increased. Packaging efficiency. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. 12 1244715 [Simplified illustration of the drawing] Figure 1: A cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. Figure 2: According to A cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. Figure 3: A semiconductor package according to another embodiment of the present invention Figure 4: A cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. Figure 5: A cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. A cross-sectional view of a semiconductor package structure according to an embodiment. FIG. 7: A cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. FIG. 8: A cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. A cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. Explanation of main component symbols 100 Semiconductor package structure 110 Semiconductor component 112 Connecting line 122 Bumps 120 Semiconductor component 130 Passive component 132 Passive component 140 Substrate 140a Groove portion 140b is recessed Slot part 13 1244715 150 package body 160 adhesive layer 200 semiconductor package structure 300 semiconductor package structure 400 semiconductor package structure 500 semiconductor package structure 600 semiconductor package structure 700 semiconductor package structure 800 semiconductor package structure 900 semiconductor package structure 14

Claims (1)

1244715 十、申請專利範圍： 1. 一種半導體封裝構造，其係包含： 一基板，其上表面設有一第一凹槽部； 至少一第一被動元件電性連接及固定於該基板上，該至 少一第一被動元件被置於該基板之第一凹槽部内；及 一第一半導體元件電性連接及固定於該基板上，該第一 半導體元件跨置於該基板之第一凹槽部並位於該至少一第 一被動元件上方。 2. 如申請專利範圍第1項所述之半導體封裝構造，另包 含複數條連接線用以電性連接該第一半導體元件至該基 板，以及一封裝體包覆該第一半導體元件、該些連接線及該 至少一第一被動元件於該基板之上表面。 3. 如申請專利範圍第1項所述之半導體封裝構造，其中 該第一半導體元件並未與該至少一第一被動元件接觸。 4. 如申請專利範圍第1項所述之半導體封裝構造，另包 含複數個金屬凸塊用以機械及電性連接該第一半導體元件 至該基板。 5. 如申請專利範圍第1項所述之半導體封裝構造，另包 含一絕緣黏著層位於該第一半導體元件及該基板之間，以將 該第一半導體元件固定於該基板並且包覆該至少一第一被 15 1244715 動元件。 t如申請專利範圍帛1項所述之半導體封裝構造，另包 3第-半導體元件:t隹疊於該第一半導體元件丨以及複數 個金屬凸塊用以機械及電性連接該第二半導體元件至該 一半導體元件。 二々7·如申請專利範圍第6項所述之半導體封裝構造，其中 該第二半導體元件包含複數個整合被動電路元件。 • ^如申請專利範圍第1項所述之半導體封裝構造，另包 含一第二半導體元件堆疊於該第一半導體元件並打線連接 至该基板。 9·如申請專利範圍第8項所述之半導體封裝構造，其中 該第二半導體元件包含複數個整合被動電路元件。 /、 10·如申請專利範圍第1項所述之半導體封裝構造，其中 該基板之上表面設有一第二凹槽部，且該半導體封裝構造另 包含至少一第二被動元件置於該基板之第二凹槽部内，以及 一第二半導體元件跨置於該基板之第二凹槽部並位於該至 少一弟二被動元件上方。 11·如申請專利範圍第1項所述之半導體封裝構造，另包 16 1244715 含複數條導電線路設於該基板，用以電性連接該至少一第一 被動元件及該第一半導體元件。 12. 如申請專利範圍第11項所述之半導體封裝構造，其 中該第一半導體元件係電性連接至該基板上表面之一組接 點，且該些導電線路係由該第一凹槽部之底部表面，經由該 凹槽部之側表面延伸至該組接點。 13. 如申請專利範圍第11項所述之半導體封裝構造，其 中該第一半導體元件係電性連接至該基板上表面之一組接 點，且該些導電線路係由該第一凹槽部之底部表面延伸至該 _ 些接點下方的位置，並藉由設在基板内的專用垂直端子與該 - 組接點連接。 14.一種半導體封裝構造，其係包含： 一基板； 一第一半導體元件； 複數個金屬凸塊用以機械及電性連接該第一半導體元 件至該基板；及 至少一第一被動元件電性連接及固定於該基板上，該至 少一第一被動元件被置於該第一半導體元件及該基板之間， 其中該第一半導體元件與基板相互間隔一充分預設之 距離，使該第一半導體元件並未與該至少一第一被動元件接 觸0 17 1244715 15.如申請專利範圍第14項所述之半導體封裝構造，立 ^亥基板之上表面設有1槽部，且該半導體構造另包 3至少-第二被動元件被置於該基板之凹槽部内，以及一第 二半導體元件跨置於該基板之凹槽部並位於該至 被動元件上方。 乐一 16·如申請專利範圍帛14_述之半導體封裝構造，另 包含-第二半導體元件堆疊於該第一半導體 連接至該基板。 、银 I7·如申請專利範圍帛10項所述之半導體封裝構造，其 中該第二半導體元件包含複數個整合被動電路元件。/、 18·如申清專利|a hi第14項所述之半導體封裝構造，另 包含-第二半導體元件堆疊於該第一半導體元件上以及複 數個金屬凸塊用以機械及電性連接該第二半導體元件至該 I9·如申請專利範圍$ IS項所述之半導體封裝構造，其 中該第二半導體元件包含複數個整合被動電路元件。 20·如申請專利範圍第14項所述之半導體封裝構造，另 包含有複數條導電線路於該基板，用以電性連接該至少一第 1244715 一被動元件及該第一半導體元件。 191244715 10. Scope of patent application: 1. A semiconductor package structure comprising: a substrate having a first groove portion on an upper surface thereof; at least one first passive element is electrically connected and fixed on the substrate, and the at least A first passive element is placed in the first groove portion of the substrate; and a first semiconductor element is electrically connected and fixed on the substrate, and the first semiconductor element is placed across the first groove portion of the substrate and Located above the at least one first passive element. 2. The semiconductor package structure described in item 1 of the scope of patent application, further comprising a plurality of connecting wires for electrically connecting the first semiconductor element to the substrate, and a package covering the first semiconductor element, the The connecting line and the at least one first passive component are on the upper surface of the substrate. 3. The semiconductor package structure according to item 1 of the scope of patent application, wherein the first semiconductor element is not in contact with the at least one first passive element. 4. The semiconductor package structure described in item 1 of the scope of the patent application, further comprising a plurality of metal bumps for mechanically and electrically connecting the first semiconductor element to the substrate. 5. The semiconductor package structure described in item 1 of the scope of patent application, further comprising an insulating adhesive layer between the first semiconductor element and the substrate, so as to fix the first semiconductor element to the substrate and cover the at least A first passive element by 15 1244715. tSemiconductor package structure described in item 1 of the scope of patent application, including 3rd-semiconductor element: t 隹 is stacked on the first semiconductor element and a plurality of metal bumps for mechanically and electrically connecting the second semiconductor Device to the one semiconductor device. 々7. The semiconductor package structure according to item 6 of the patent application scope, wherein the second semiconductor element includes a plurality of integrated passive circuit elements. • ^ The semiconductor package structure described in item 1 of the scope of patent application, further comprising a second semiconductor element stacked on the first semiconductor element and wire-connected to the substrate. 9. The semiconductor package structure according to item 8 of the scope of patent application, wherein the second semiconductor element includes a plurality of integrated passive circuit elements. / 、 10 · The semiconductor package structure according to item 1 of the scope of patent application, wherein a second groove portion is provided on the upper surface of the substrate, and the semiconductor package structure further includes at least a second passive component placed on the substrate Inside the second groove portion, and a second semiconductor element is straddled over the second groove portion of the substrate and located above the at least one passive component. 11. The semiconductor package structure described in item 1 of the scope of the patent application, additional package 16 1244715 is provided on the substrate for electrically connecting the at least one first passive element and the first semiconductor element. 12. The semiconductor package structure according to item 11 of the scope of patent application, wherein the first semiconductor element is electrically connected to a set of contacts on the upper surface of the substrate, and the conductive lines are formed by the first groove portion. The bottom surface extends to the set of contacts through the side surface of the groove portion. 13. The semiconductor package structure according to item 11 of the scope of patent application, wherein the first semiconductor element is electrically connected to a set of contacts on the upper surface of the substrate, and the conductive lines are formed by the first groove portion. The bottom surface extends to the position below the contacts, and is connected to the set of contacts through a dedicated vertical terminal provided in the substrate. 14. A semiconductor package structure comprising: a substrate; a first semiconductor element; a plurality of metal bumps for mechanically and electrically connecting the first semiconductor element to the substrate; and at least one first passive element electrically Connected and fixed on the substrate, the at least one first passive element is placed between the first semiconductor element and the substrate, wherein the first semiconductor element and the substrate are spaced from each other by a sufficiently preset distance so that the first The semiconductor element is not in contact with the at least one first passive element. 0 17 1244715 15. According to the semiconductor package structure described in item 14 of the scope of patent application, the upper surface of the vertical substrate is provided with a groove, and the semiconductor structure The package 3 is at least-the second passive element is placed in the groove portion of the substrate, and a second semiconductor element is placed across the groove portion of the substrate and is positioned above the passive element. Leyi 16. The semiconductor package structure described in the patent application scope 14_, further including-a second semiconductor element stacked on the first semiconductor and connected to the substrate. Silver I7. The semiconductor package structure according to the scope of the patent application No. 10, wherein the second semiconductor element includes a plurality of integrated passive circuit elements. /, 18 · The semiconductor package structure as described in claim 14 of the patent | a hi, further comprising-a second semiconductor element stacked on the first semiconductor element and a plurality of metal bumps for mechanically and electrically connecting the The second semiconductor element to the I9. The semiconductor package structure described in the item of the patent application $ IS, wherein the second semiconductor element includes a plurality of integrated passive circuit elements. 20. The semiconductor package structure described in item 14 of the scope of the patent application, further comprising a plurality of conductive lines on the substrate for electrically connecting the at least one 1244715 passive component and the first semiconductor component. 19
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