JPS6256664B2 - - Google Patents

Info

Publication number
JPS6256664B2
JPS6256664B2 JP55184737A JP18473780A JPS6256664B2 JP S6256664 B2 JPS6256664 B2 JP S6256664B2 JP 55184737 A JP55184737 A JP 55184737A JP 18473780 A JP18473780 A JP 18473780A JP S6256664 B2 JPS6256664 B2 JP S6256664B2
Authority
JP
Japan
Prior art keywords
conductor
grounding
conductors
layer
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55184737A
Other languages
Japanese (ja)
Other versions
JPS57107059A (en
Inventor
Norikuni Azuma
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55184737A priority Critical patent/JPS6256664B2/ja
Publication of JPS57107059A publication Critical patent/JPS57107059A/en
Publication of JPS6256664B2 publication Critical patent/JPS6256664B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221Crossover interconnections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To improve reliability by minimizing the level variation for reduction in noise with a grounding conductor only or a grounding conductor and a power supply conductor provided at the bottom of and also around the sides of the chip inside the package. CONSTITUTION:In a package composed of ceramic, for example, the grounding conductor 10 consisting of a bottom conductor 11, side conductors 12 and exposed conductors 13 is provided at the cavity for accommodating the IC chip 1. A wide connecting conductor 14 is provided for connection between the ground conductor 10 and an external terminal by forming an underneath layer which is different from the bond wirings 2. On the exposed conductors 13, ground wire bonding is applied. Other than the layer of the ground conductor 10, an another conductor layers, the power supply conductor 15, may be provided in double layer construction with a ceramic sheet interlaid. This layer consists likewise of a bottom conductor 16, side conductors 17, exposed conductors 18 and connecting conductor 19. This construction gives higher reliability which can allow preventing variation of the grounding level or power supply level.
JP55184737A 1980-12-25 1980-12-25 Expired JPS6256664B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55184737A JPS6256664B2 (en) 1980-12-25 1980-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55184737A JPS6256664B2 (en) 1980-12-25 1980-12-25

Publications (2)

Publication Number Publication Date
JPS57107059A JPS57107059A (en) 1982-07-03
JPS6256664B2 true JPS6256664B2 (en) 1987-11-26

Family

ID=16158474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55184737A Expired JPS6256664B2 (en) 1980-12-25 1980-12-25

Country Status (1)

Country Link
JP (1) JPS6256664B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417266A (en) * 1981-08-14 1983-11-22 Amp Incorporated Power and ground plane structure for chip carrier
JPS596563A (en) * 1982-07-05 1984-01-13 Nec Corp Integrated circuit device
JPH0481330B2 (en) * 1983-08-12 1992-12-22 Hitachi Ltd
JPH0160941B2 (en) * 1984-01-13 1989-12-26 Nippon Electric Co
JPH0134355Y2 (en) * 1984-07-12 1989-10-19
JP2978533B2 (en) * 1990-06-15 1999-11-15 株式会社日立製作所 Semiconductor integrated circuit device
JPH06103721B2 (en) * 1990-09-25 1994-12-14 松下電工株式会社 Semiconductor chip carrier
KR100582497B1 (en) * 2004-02-24 2006-05-23 삼성전자주식회사 memory card using printed circuit board having electrostatic discharge protection pattern

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5185349A (en) * 1975-01-24 1976-07-26 Hitachi Ltd
JPS5272169A (en) * 1975-12-12 1977-06-16 Nec Corp Semiconductor device
JPS5415663A (en) * 1974-01-10 1979-02-05 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5415663A (en) * 1974-01-10 1979-02-05 Nec Corp Semiconductor device
JPS5185349A (en) * 1975-01-24 1976-07-26 Hitachi Ltd
JPS5272169A (en) * 1975-12-12 1977-06-16 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS57107059A (en) 1982-07-03

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