JPH02244753A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH02244753A JPH02244753A JP6553989A JP6553989A JPH02244753A JP H02244753 A JPH02244753 A JP H02244753A JP 6553989 A JP6553989 A JP 6553989A JP 6553989 A JP6553989 A JP 6553989A JP H02244753 A JPH02244753 A JP H02244753A
- Authority
- JP
- Japan
- Prior art keywords
- package
- chips
- chip
- integrated circuit
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 108010011222 cyclo(Arg-Pro) Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明はＬＳＩパッケージに複数のチップを搭載した集
積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device in which a plurality of chips are mounted on an LSI package.
［従来の技術］
従来から、この種の集積回路装置として第２図に示す装
置が知られている。絶縁９体にて構成されたＬＳＩバ、
ツケージ１１の一方の面側には、チップを搭載するため
の凹部が形成されており、この凹部に複数のチップ１２
ａｌ ｌ ２ ｂ＋ １２ ｃが搭載されている
。ＬＳＩパッケージ１１の凹部を囲むパッケージ周縁部
の上面には、複数のパッケージパッド１３ ａ、 １
３ ｂ、 １３ ｃが設けられており、チップ１２ａ
乃至１２ｃに配置されたチップパッド１４ａ乃至１４ｃ
と上記パッケージパッド１３ａ乃至１３ｃとがボンディ
ングワイヤ１５ ａ ＋１５ｂ、１５ｃを夫々介して接
続されている。チップパッド１４ａ乃至１４ｃは、ＬＳ
Ｉパッケージ１１の図示しない内部配線によって外部リ
ード１６と接続されている。[Prior Art] A device shown in FIG. 2 has been known as this type of integrated circuit device. LSI board composed of 9 insulators,
A recess for mounting chips is formed on one side of the cage 11, and a plurality of chips 12 are mounted in this recess.
al l 2 b + 12 c is installed. A plurality of package pads 13 a, 1 are provided on the upper surface of the peripheral edge of the LSI package 11 surrounding the concave portion.
3b and 13c are provided, and the chip 12a
Chip pads 14a to 14c arranged at 12c to 14c
and the package pads 13a to 13c are connected via bonding wires 15a+15b and 15c, respectively. Chip pads 14a to 14c are LS
It is connected to the external lead 16 by internal wiring (not shown) of the I package 11.
［発明が解決しようとする課題］
このような集積回路装置では、チップ実装数が増えるほ
どチップ間の相互配線等による実装効率の向上が期待で
きるが、チップとパッケージとの間のボンディングスペ
ースの縮小が困難であることから、ＬＳＩパッケージの
大型化を招くことなしにチップ搭載数を増やすことは困
難であるという問題点があった。[Problem to be solved by the invention] In such an integrated circuit device, as the number of chips mounted increases, it is expected that the mounting efficiency will improve due to interconnection between chips, etc. However, the bonding space between the chip and the package will be reduced. Therefore, there was a problem in that it was difficult to increase the number of chips mounted without increasing the size of the LSI package.
本発明はかかる問題点に鑑みてなされたものであって、
ＬＳＩチップパッケージの大型化を招来することなくチ
ップ搭載数を増やすことができる集積回路装置を提供す
ることを目的とする。The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide an integrated circuit device in which the number of chips mounted can be increased without increasing the size of an LSI chip package.
Ｃ課題を解決するための手段］
本発明に係る集積回路装置は、両面にチップ搭載部及び
パッケージバッドを備えた集積回路パッケージと、この
集積回路パッケージの両面の前記チップ搭載部に夫々搭
載された複数の半導体チップと、これら半導体チップの
チップバッドと前記パッケージパッドとを接続する手段
とを備えたことを特徴とする。Means for Solving Problem C] An integrated circuit device according to the present invention includes an integrated circuit package having a chip mounting portion and a package pad on both sides, and a chip mounting portion mounted on each of the chip mounting portions on both sides of the integrated circuit package. It is characterized by comprising a plurality of semiconductor chips and means for connecting chip pads of these semiconductor chips and the package pad.
［作用］
本発明においては、集積回路パッケージの両面にチップ
を搭載し、各面側で夫々チップバッドとパッケージとの
接続を行っているので、パッケージの大型化を招かずに
チップ搭載数を増やすことができる。[Function] In the present invention, chips are mounted on both sides of the integrated circuit package, and the chip pads and the package are connected to each other on each side, so the number of chips mounted can be increased without increasing the size of the package. be able to.
また、このようにチップの実装数が増えることにより、
パッケージ内でのチップ間の相互配線等によって、チッ
プ当たりの外部リード端子数を大幅に減少させることが
でき、これによってもパッケージの小型化が図れること
になる。Also, as the number of chips mounted increases in this way,
By interconnecting the chips within the package, the number of external lead terminals per chip can be significantly reduced, and this also allows the package to be made smaller.
［実施例］
次に、添付の図面を参照しながら本発明の実施例につい
て説明する。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の実施例に係る集積回路装置の概略構成
を示す図で、同図（ａ）は同図（ｂ）のＩ−Ｘ線による
断面図、同図（ｂ）は平面図である。FIG. 1 is a diagram showing a schematic configuration of an integrated circuit device according to an embodiment of the present invention, in which (a) is a cross-sectional view taken along line I-X in (b), and (b) is a plan view. It is.
例えば多層配線基板によって形成されたＬＳＩパッケー
ジ１には、その両面にチップ搭載部となる凹部が形成さ
れている。そして、一方の面の凹部には、チップ２ａ、
２ｂが搭載され、他方の而の凹部には、チップ２ｅ、２
ｄ（但し、２ｄは図示せず）が搭載されている。ＬＳＩ
パッケージ１の各面の凹部を囲む周縁部には、各チップ
２ａ乃至２ｄに対応するパッケージパッド３ａ、３ｂ。For example, an LSI package 1 formed of a multilayer wiring board has recesses that serve as chip mounting portions formed on both surfaces thereof. The chip 2a,
2b is mounted, and the other recess has chips 2e, 2
d (however, 2d is not shown) is mounted. LSI
At the periphery surrounding the recess on each side of the package 1, package pads 3a, 3b corresponding to each of the chips 2a to 2d are provided.
３ｅ、３ｄ（但し、３ｄは図示せず）が配置されている
。これらパッケージバッド３ａ乃至３ｄは、ＬＳＩパッ
ケージ１の内部配線によって共通部分について選択的に
相互接続されたものとなっている。3e and 3d (3d is not shown) are arranged. These package pads 3a to 3d are selectively interconnected at common portions by internal wiring of the LSI package 1.
一方、チップ２ａ乃至２ｄの周辺にはチップパッド４
ａ、４ ｂ＊ ４ ＣＩ ４ ｄ （但し、４ｄは図示
せず）が配置されており、これらチップバッド４ａ乃至
４ｄと前述したパッケージバッド３ａ乃至３ｄとがボン
ディングワイヤ５ａ、５ｂ、５ｅ＋５ｄ（但し５ｄは図
示せず）を介して接続されている。On the other hand, chip pads 4 are located around the chips 2a to 2d.
a, 4 b* 4 CI 4 d (however, 4 d is not shown) are arranged, and these chip pads 4 a to 4 d and the above-mentioned package pads 3 a to 3 d are connected to bonding wires 5 a, 5 b, 5 e + 5 d (however, 5 d (not shown).
更に、ＬＳＩパッケージ１の側面には、複数の外部リー
ド６が配設されている。この外部リード６は、基喘部が
ＬＳＩパッケージ１の内部配線と選択的に接続されたも
のとなっている。Furthermore, a plurality of external leads 6 are arranged on the side surface of the LSI package 1. The base portion of the external lead 6 is selectively connected to the internal wiring of the LSI package 1.
このような構成によれば、チップ２ａ乃至２ｄがＬＳＩ
パッケージ１の両面に配置されているので、従来方式で
は、２つのチップしか搭載できなかったパッケージサイ
ズで４つのチップ２ａ乃至２ｄを搭載することが可能に
なり、搭載数を倍にすることができる。According to such a configuration, the chips 2a to 2d are LSI
Since they are arranged on both sides of the package 1, it is now possible to mount four chips 2a to 2d in a package size that could only mount two chips in the conventional method, doubling the number of chips mounted. .
また、このようにチップ搭載数が増えることにより１．
チップ間の端子の相互接続数が増えるので、チップ当た
りの外部リード端子数も減らすことができ、更にパッケ
ージサイズの小型化を図ることができる。In addition, as the number of chips mounted increases in this way, 1.
Since the number of terminal interconnections between chips increases, the number of external lead terminals per chip can also be reduced, and the package size can further be reduced.
なお、上述した実施例は本発明の一例であって、本発明
がこの実施例に限定されるものでないことはいうまでも
ない。Note that the above-mentioned embodiment is an example of the present invention, and it goes without saying that the present invention is not limited to this embodiment.
例えば上記実施例では、チップパッドとパッケージパッ
ドとをボンディングワイヤで接続したが、ハンダバンブ
により接続するようにしても良い。For example, in the above embodiment, the chip pad and the package pad are connected by bonding wires, but they may be connected by solder bumps.
また、外部リードの引出し方法についても、」二連した
方法に限定されず、ＤＩＰ型、フラットバック型及びＴ
ＡＢ型等の形態を採用することが可能である。In addition, the method of pulling out external leads is not limited to the two-way method, but is also limited to the DIP type, flat back type, and T.
It is possible to adopt a form such as AB type.
［発明の効果］
以上説明したように、本発明はＬＳＩパッケージの上下
両面にチップを搭載するようにしたから、パッケージサ
イズの大型化を招くことなしにチップ搭載数を増すこと
ができ、これにより、チップの実装効率の向上を図るこ
とができる。[Effects of the Invention] As explained above, since the present invention mounts chips on both the upper and lower surfaces of an LSI package, the number of chips mounted can be increased without increasing the package size. , it is possible to improve chip mounting efficiency.
第１図は本発明に係る集積回路装置の要部構成を示す図
で、同図（ａ）は同図（ｂ）のＩ−Ｉ線による断面図、
同図（ｂ）は平面図、第２図は従来の集積回路装置の要
部を示す図で、同図（ａ）は同図（ｂ）の■−■線によ
る断面図、同図（ｂ）は平面図である。
１．１１；ＬＳＩパッケージ、２ａ乃至２ｃ１１２ａ乃
至１２Ｃ；チップ、３ａ乃至３ｃ、１３ａ乃至１３ｃ：
パッケージパッド、４ａ乃至４ｃ。FIG. 1 is a diagram showing the main part configuration of an integrated circuit device according to the present invention, and FIG. 1(a) is a cross-sectional view taken along the line II in FIG.
Figure 2 (b) is a plan view, Figure 2 is a diagram showing the main parts of a conventional integrated circuit device, Figure (a) is a sectional view taken along the line ) is a plan view. 1.11; LSI packages, 2a to 2c112a to 12C; chips, 3a to 3c, 13a to 13c:
Package pads, 4a to 4c.
Claims (1)
た集積回路パッケージと、この集積回路パッケージの両
面の前記チップ搭載部に夫々搭載された複数の半導体チ
ップと、これら半導体チップのチップパッドと前記パッ
ケージパッドとを接続する手段とを備えたことを特徴と
する集積回路装置。(1) An integrated circuit package having a chip mounting portion and a package pad on both sides, a plurality of semiconductor chips mounted on the chip mounting portions on both sides of this integrated circuit package, the chip pads of these semiconductor chips, and the package. An integrated circuit device comprising means for connecting the pad to the pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6553989A JPH02244753A (en) | 1989-03-17 | 1989-03-17 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6553989A JPH02244753A (en) | 1989-03-17 | 1989-03-17 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02244753A true JPH02244753A (en) | 1990-09-28 |
Family
ID=13289922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6553989A Pending JPH02244753A (en) | 1989-03-17 | 1989-03-17 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02244753A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004022610A (en) * | 2002-06-12 | 2004-01-22 | Matsushita Electric Ind Co Ltd | Interposer, semiconductor package, interposer-manufacturing method, and semiconductor package manufacturing method |
-
1989
- 1989-03-17 JP JP6553989A patent/JPH02244753A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004022610A (en) * | 2002-06-12 | 2004-01-22 | Matsushita Electric Ind Co Ltd | Interposer, semiconductor package, interposer-manufacturing method, and semiconductor package manufacturing method |
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