JPS5839037A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPS5839037A JPS5839037A JP56138010A JP13801081A JPS5839037A JP S5839037 A JPS5839037 A JP S5839037A JP 56138010 A JP56138010 A JP 56138010A JP 13801081 A JP13801081 A JP 13801081A JP S5839037 A JPS5839037 A JP S5839037A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip carrier
- external connection
- chip
- connection bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
本発明はアルミナ基板にＩＣ，Ｌ８Ｉ等を搭載し、パッ
ケージングしてなるチップキャリアの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a chip carrier in which ICs, L8I, etc. are mounted on an alumina substrate and packaged.
従来のこの種のチップキャリアの外部接続用端子は基板
周辺の４辺に１列に配されており、リード、あるいはノ
１ンダ付用のノくラドや／くンプで形成されている。こ
のような端子間の間隔は、チップキャリアを多層配線基
板に搭載する際に、半田によるショートの問題などがお
り、あまり小さくすることはできない。External connection terminals of conventional chip carriers of this type are arranged in a row on the four sides of the substrate, and are formed of leads or solder pads or clamps for attaching a solder. Such a distance between the terminals cannot be made very small because there are problems such as short circuits caused by solder when the chip carrier is mounted on a multilayer wiring board.
しかし、端子数を増やすと端子数と間隔の積で基板の周
辺の長さが規定されてしまうことからチップキャリアの
外形ｔ１それにともなって大きくする必要がある。However, if the number of terminals is increased, the length of the periphery of the substrate is determined by the product of the number of terminals and the spacing, so it is necessary to increase the size in accordance with the external dimension t1 of the chip carrier.
近年、ＩＣ，ＬＳＩの１つのチップに形成される回路数
は大幅に増えており、それにともなってＩＣ，ＬＳＩの
必要とする繻子数も１す１す増加している。したがって
これらのＩＣ、ＬＳ Ｉを搭載するチップキャリアの外
形もそれにともがって大きくしなければならない。とこ
ろがチップキャリアが大きくなると、このチップキャリ
アを、多層配線基板上に多層のせることは表面積の関係
からできなくなる。つまり、せっかく１つのＩＣ，ＬＳ
１の集積度を上げても、それにともなってチップキャリ
アの外形も大さくなり、したがって多層配線基板に実装
する際には、それほど実装密度があがらないという問題
が生ずる。In recent years, the number of circuits formed on a single IC or LSI chip has increased significantly, and the number of silks required for the IC or LSI has also increased by one. Therefore, the external dimensions of chip carriers on which these ICs and LSIs are mounted must be increased accordingly. However, as the chip carrier becomes larger, it becomes impossible to mount multiple layers of the chip carrier on a multilayer wiring board due to surface area limitations. In other words, one IC, LS
Even if the degree of integration of chip carrier 1 is increased, the external size of the chip carrier also becomes larger, resulting in the problem that the packaging density cannot be increased that much when mounted on a multilayer wiring board.
本発明の目的は、チップキャリアの外形をそれほど大き
くしなくても多端子のＩＣ等を搭載でき、多層配線基板
上に高密度に実装可能なチップキャリアを提供すること
Ｋある。An object of the present invention is to provide a chip carrier on which a multi-terminal IC or the like can be mounted without increasing the external size of the chip carrier, and which can be mounted at high density on a multilayer wiring board.
前記目的を達成するために本５発明によるチップキャリ
アは基板にＩＣ，Ｌ８Ｉ等を搭載し、パッケージングし
てなるチップキャリアにおいて、チップキャリ、子基板
側面の１つに、配線によって基板表面に形成されたＩＣ
リードポンディングパッドに接続された外部接続用バン
プを格子状に配設し、前記基板側面を多層配線基板面に
対向させて実装できるように構成しである。In order to achieve the above object, the chip carrier according to the fifth invention is a chip carrier in which IC, L8I, etc. are mounted on a substrate and packaged, and the chip carrier is formed on the surface of the substrate by wiring on one of the side surfaces of the child substrate. IC
External connection bumps connected to lead bonding pads are arranged in a lattice pattern, and the device can be mounted with the side surface of the board facing the surface of the multilayer wiring board.
前記構成によればチップキャリアを立てて実装でき、チ
ップキャリアの高密度実装が可能となり本発明の目的は
完全に達成される。According to the above configuration, the chip carrier can be mounted upright, and the chip carrier can be mounted in high density, thereby completely achieving the object of the present invention.
以下、図面等を参照して本発明をさらに詳しく説明する
。Hereinafter, the present invention will be explained in more detail with reference to the drawings and the like.
第１図は本発明によるチップキャリアのアルミナ基板の
一実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of an alumina substrate of a chip carrier according to the present invention.
アルミナ基板１１の表面にはＩＣリードポンディングパ
ッド１２が形成されており、この表面と直角の位置関係
にある１つの基板側面１３には格子状に配された外部接
続バンプ１４が、形成されている。各ＩＣリードポンデ
ィングパッド１２は内層に設けられた配線１５によって
各外部接続バンプ１４に接続されている。凹部１６には
パッド１２にワイヤもしくはリードによって結線される
ＩＣチップが搭載可能である。An IC lead bonding pad 12 is formed on the surface of the alumina substrate 11, and external connection bumps 14 arranged in a grid pattern are formed on one side surface 13 of the substrate perpendicular to this surface. There is. Each IC lead bonding pad 12 is connected to each external connection bump 14 by a wiring 15 provided on the inner layer. An IC chip connected to the pad 12 by a wire or lead can be mounted in the recess 16 .
第２図は第１図のアルミナ基板にＩＣチップを搭載した
時の断面図である。同図において、アルｔす基板２１の
表面に形成された凹部２６にはＩＣチップ２７が搭載さ
れてお′す、ＩＣリード２８がＩＣリードポンディング
パッド２２にボンディングされている。またキャップ２
９がＩＣテップ２７を保護するため基板２１の表面に取
り付けられている。FIG. 2 is a sectional view when an IC chip is mounted on the alumina substrate of FIG. 1. In the figure, an IC chip 27 is mounted in a recess 26 formed on the surface of an aluminum substrate 21, and an IC lead 28 is bonded to an IC lead bonding pad 22. Also cap 2
9 is attached to the surface of the substrate 21 to protect the IC chip 27.
さらに基板２１の裏面には放熱のためのヒートシンク２
０が取り付けられている。Furthermore, a heat sink 2 for heat dissipation is provided on the back side of the board 21.
0 is attached.
第３図は本チップキャリアを多層配線基板に実装した場
合の断面図である。同図において、チップキャリア３１
ハ基板側面に形成された外部接続バンプ３２によって多
層配線基板３３にたてに接続され、高密度実装が可能に
なる。FIG. 3 is a cross-sectional view of the present chip carrier mounted on a multilayer wiring board. In the figure, a chip carrier 31
C. It is vertically connected to the multilayer wiring board 33 by external connection bumps 32 formed on the side surface of the board, thereby enabling high-density mounting.
本発明はバンプが格子状に配列されているため、端子数
が増加してもバンプを形成するための基板側面の大きさ
はそれほど増加しない。これを例えば端子数が１２０で
端子間隔がα５謹の場合を例に説明する。、従来のチッ
プキャリアは、端子を周辺の４辺に１列に形成するため
１辺の大きさは、おおよそ３０ Ｘ Ｑ５＝ １５ｍで
面積ｔｉ１５Ｘ１５＝２２５−となる。つまりこの面積
だけ多層配線基板上に占めることになる。本発明でｔｊ
１２０の端子を２０Ｘ６列のように配列すれば、側面
の大きさは、おおよそ１０謹×３冒で面積は３０−にす
ぎない。これに５−の高さのヒートシンクをつけると１
０Ｘ５−５０−の増加となり、あわせて３０ ＋ ５０
−８０−の面積が多層配線基板上に占めるととＫなる。In the present invention, since the bumps are arranged in a grid pattern, even if the number of terminals increases, the size of the side surface of the substrate for forming the bumps does not increase significantly. This will be explained using an example in which the number of terminals is 120 and the terminal interval is α5. In the conventional chip carrier, the terminals are formed in one row on the four peripheral sides, so the size of one side is approximately 30 x Q5 = 15 m, and the area is ti15 x 15 = 225 -. In other words, this area occupies the multilayer wiring board. In the present invention, tj
If 120 terminals are arranged in 20 x 6 rows, the size of the side surface is approximately 10 x 3, and the area is only 30 -. If you add a heat sink with a height of 5- to this, it will be 1
0X5-50- increase, totaling 30 + 50
If the area -80- occupies the multilayer wiring board, then it becomes K.
この値は、従来の２２５−と比較して約亮であり、大幅
な高密度化が可能でおることがわかる。This value is approximately brighter than the conventional 225-, and it can be seen that a significant increase in density is possible.
第４図に本発明の第２の実施例を示す断面図である。同
図において、アルミナ基板４１Ｆｉ、２段の段差がつけ
られている。一番下の段４１ｂにはＩＣチップ４７が搭
載され、ＩＣリードポンディングパッド４２ Ｋ Ｉ
Ｃリード４８がボンディングされている。ＩＣチップ搭
載面から基板裏面までの厚さを薄くすることにより、Ｉ
Ｃチップ４７から発生する熱が、基板裏面に取り付けら
れるヒートシンクにすみやかに伝わるようになっている
。また２段目の段差４１ａＫｔ１キヤツプの取り付けが
容易におこなえ、かつシーリング性の向上を目的とした
キャップ４９が挿入されている。FIG. 4 is a sectional view showing a second embodiment of the present invention. In the figure, an alumina substrate 41Fi has two steps. An IC chip 47 is mounted on the bottom stage 41b, and an IC lead bonding pad 42 K I
A C lead 48 is bonded. By reducing the thickness from the IC chip mounting surface to the back surface of the board,
Heat generated from the C-chip 47 is quickly transferred to a heat sink attached to the back surface of the board. In addition, a cap 49 is inserted to facilitate attachment of the second step 41aKt1 cap and to improve sealing performance.
このような構造でも、基板側面４３の大きさは第１の実
施例と同じであり、接続用バンプ４４ハ十分形成できす
。Even in this structure, the size of the side surface 43 of the substrate is the same as in the first embodiment, and the connection bumps 44 can be sufficiently formed.
また、ＩＣリードポンディングパッド４２と、バンプ４
４とを内部配線４５で結ぶことは、このような形状であ
っても十分可能である。In addition, the IC lead bonding pad 42 and the bump 4
4 through the internal wiring 45 is sufficiently possible even with such a shape.
第５図は、このチップキャリアにヒートシンク５０を取
り付は多層配線基板５３に実装した場合の断面図である
。ＩＣのパワーが増加し２発熱量が大きくなっても本図
のようにヒートシンク５０を上に伸ばすことによって対
処できる。さらに冷却が必要ならばコールドプレート等
を利用した水冷も可能で、このようなチップキャリアの
縦形実装は冷却上も問題ない。本チップキャリアにバン
プ５２によって多層配線基板と接続されるが、チップキ
ャリア間にはヒートシンクのために５ｍ程度の間熱が必
要である。このスペースは多層配線基板上では、改造パ
ッド５４のための領域として利用することができる。こ
のような高密度実装においては、多層配線基板上での改
造は必須であり、このための領域をとっておかなければ
ならない。これも多層配線基板上での実装密度を下げる
要因であったが、本チップキャリアを用いることにより
、実装密度を下げることなく、改造のためのスペースを
確保することができる。FIG. 5 is a cross-sectional view when a heat sink 50 is attached to this chip carrier and mounted on a multilayer wiring board 53. Even if the power of the IC increases and the amount of heat generated increases, this can be dealt with by extending the heat sink 50 upward as shown in this figure. If further cooling is required, water cooling using a cold plate or the like is also possible, and such vertical mounting of the chip carrier poses no problem in terms of cooling. This chip carrier is connected to the multilayer wiring board by bumps 52, but heat is required for about 5 m between the chip carriers for a heat sink. This space can be used as an area for the modified pad 54 on the multilayer wiring board. In such high-density packaging, modification on the multilayer wiring board is essential, and space must be reserved for this purpose. This was also a factor in lowering the packaging density on the multilayer wiring board, but by using this chip carrier, space for modification can be secured without lowering the packaging density.
第６図は本発明の第３の実施例を示す断面図である。基
板６１に搭載されているＩＣチップ６７に、いわゆるフ
リップチップ形のものであり、チップのバンプと基板上
のパッド６２がポンディングされている。バッド６２Ｆ
ｉ基板側面に形成された外部接続用バンプ６４に内部配
線６５にされている。このようにして本チップキャリア
を用いることにより、フリップチップの特徴である多端
子接続をそこかうことなく、ヒートシンクをつけ冷却能
力を高めるとともに、改造スペースがとれることから、
多層配線基板上への高密度実装が可能となる。FIG. 6 is a sectional view showing a third embodiment of the present invention. This is a so-called flip-chip type IC chip 67 mounted on a substrate 61, and the bumps of the chip and pads 62 on the substrate are bonded. Bad 62F
An internal wiring 65 is provided on an external connection bump 64 formed on the side surface of the i-board. By using this chip carrier in this way, it is possible to attach a heat sink to increase the cooling capacity and save space for modification without compromising the multi-terminal connection that is a feature of flip chips.
High-density mounting on multilayer wiring boards becomes possible.
以上詳しく説明したようＫ、本発明によれば外部接続用
バンプを基板側面に格子状に配列することにより、チッ
プキャリアの大きさをそれほど大きくしなくても、多端
子ＩＣを搭載でき、多層配線基板に高密度に実装できる
。As explained in detail above, according to the present invention, by arranging external connection bumps in a lattice pattern on the side surface of the substrate, a multi-terminal IC can be mounted without increasing the size of the chip carrier, and multi-layer wiring Can be mounted on a board with high density.
第１図は本発明の一実施例を示す斜視図、第２図は第１
図のアルＺす基板にＩＣを搭載した時の断面図、＠３図
は１３２図のチップキャリアを多層配線基板に実装した
場合の部分断面図である。第４図は本発明の第２の実施
例を示す断面図、第５図は第４図のチップキャリアを多
層配線基板に実装した場合の部分断面図である。
１３６図は本発明の第３の実施例を示す断面図である。
１１．２１，４１，６．１・・・アルミン基板３１ 、
５１・・・チップキャリア
１２．２２，６２・・・ＩＣリードポンディングパッド
１３ 、２３ 、４３・・・基板側向
１４ 、２４ 、３２ 、４４ 、５２ 、６４−・・
外部接続用バンプ１５ 、２５ 、４５ 、６５−・・
内部配線１６ 、２６・・・凹部 ２７ 、４７ 、６
７・・、ＩＣチップ２８ 、４８・・・ＩＣリード ２
９ 、４９・−・キャップ２Ｇ 、 ５０ 、６０・・
・ヒートシンク３３．５３・−・多層配線基板 ５４・
−・改造用パッド特許出願人 日本電気株式会社
代理人 弁理士井ノロ 壽
第１区
６
ｊ
２２図
才５図
３３
才４図
オ・５図
２６図FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing one embodiment of the present invention.
Figure 132 is a cross-sectional view when an IC is mounted on a board, and Figure 3 is a partial cross-sectional view when the chip carrier shown in Figure 132 is mounted on a multilayer wiring board. FIG. 4 is a sectional view showing a second embodiment of the present invention, and FIG. 5 is a partial sectional view when the chip carrier of FIG. 4 is mounted on a multilayer wiring board. FIG. 136 is a sectional view showing a third embodiment of the present invention. 11.21, 41, 6.1... aluminum substrate 31,
51... Chip carrier 12. 22, 62... IC lead bonding pads 13, 23, 43... Board side direction 14, 24, 32, 44, 52, 64-...
External connection bumps 15, 25, 45, 65--
Internal wiring 16, 26... recess 27, 47, 6
7..., IC chip 28, 48... IC lead 2
9, 49... Cap 2G, 50, 60...
・Heat sink 33.53・-・Multilayer wiring board 54・
-・Remodeling Pad Patent Applicant NEC Corporation Agent Patent Attorney Inoro Ju 1st Ward 6 J 22 Figure 5 Figure 33 Age 4 Figure O 5 Figure 26
Claims (1)
るチップキャリアにおいて、チップキャリア基板側面の
１つに、配線によって基板表面に形成されたＩＣリード
ボンデイングツ２ツドに接続された外部接続用バンプを
格子状に配設し、前記基板側面を多層配線基板面に対向
させて実装できるように構成したことを特徴とするチッ
プキャリア。In a chip carrier in which an IC, LSI, etc. is mounted on a substrate and packaged, an external connection bump is connected to one of the sides of the chip carrier substrate by wiring to two IC lead bonding points formed on the substrate surface. What is claimed is: 1. A chip carrier, characterized in that the chips are arranged in a lattice pattern and can be mounted with the side surface of the substrate facing the surface of the multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138010A JPS5839037A (en) | 1981-09-01 | 1981-09-01 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138010A JPS5839037A (en) | 1981-09-01 | 1981-09-01 | Chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5839037A true JPS5839037A (en) | 1983-03-07 |
Family
ID=15211943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56138010A Pending JPS5839037A (en) | 1981-09-01 | 1981-09-01 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839037A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63141352A (en) * | 1986-12-03 | 1988-06-13 | Nec Corp | Suface-packaged integrated circuit module |
| JPS63258048A (en) * | 1987-04-15 | 1988-10-25 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0230169A (en) * | 1988-07-19 | 1990-01-31 | Fujitsu Ltd | Semiconductor device |
| US20110139987A1 (en) * | 2008-06-13 | 2011-06-16 | Bruker Nano BmbH | Sensor head for an x-ray detector and x-ray detector containing said sensor head |
-
1981
- 1981-09-01 JP JP56138010A patent/JPS5839037A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63141352A (en) * | 1986-12-03 | 1988-06-13 | Nec Corp | Suface-packaged integrated circuit module |
| JPS63258048A (en) * | 1987-04-15 | 1988-10-25 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0230169A (en) * | 1988-07-19 | 1990-01-31 | Fujitsu Ltd | Semiconductor device |
| US20110139987A1 (en) * | 2008-06-13 | 2011-06-16 | Bruker Nano BmbH | Sensor head for an x-ray detector and x-ray detector containing said sensor head |
| US8558175B2 (en) * | 2008-06-13 | 2013-10-15 | Bruker Nano Gmbh | Sensor head for an x-ray detector and x-ray detector containing said sensor head |
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