JPH0230169A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0230169A JPH0230169A JP18106488A JP18106488A JPH0230169A JP H0230169 A JPH0230169 A JP H0230169A JP 18106488 A JP18106488 A JP 18106488A JP 18106488 A JP18106488 A JP 18106488A JP H0230169 A JPH0230169 A JP H0230169A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- mounting
- terminals
- connection pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000919 ceramic Substances 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 238000005452 bending Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 241000282326 Felis catus Species 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 235000012771 pancakes Nutrition 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 235000014347 soups Nutrition 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
搭載基板に実装された時に専有面積が小さく高密度に搭
載が可能な半導体装置に関し、搭載時の専有面積が小さ
く、かつ端子数を多くとれるパッケージを備えた半導体
装置を提供することを目的とし、
パッケージ内に収容された半導体チップを搭載基板に接
続する複数のリードが、該半導体チップの主面と平行方
向にパッケージの１側面６と導出されさらにその先端が
前記導出の方向と直角な同一面となるように曲折されて
表面実装用の接続バッドもしくは接続端子に形成された
構成である。[Detailed Description of the Invention] [Summary] Regarding a semiconductor device that occupies a small area when mounted on a mounting board and can be mounted at high density, the present invention has a package that occupies a small area when mounted and can have a large number of terminals. A plurality of leads for connecting a semiconductor chip housed in a package to a mounting board are led out from one side surface 6 of the package in a direction parallel to the main surface of the semiconductor chip, and are further connected to one side surface 6 of the package. The tip is bent so as to be on the same plane perpendicular to the direction of the lead-out, and is formed into a connection pad or connection terminal for surface mounting.
本発明は、半導体集積回路のパッケージに係り、特に搭
載基板に実装された時に専有面積が小さく高密度に搭載
が可能な半導体装置に関する。The present invention relates to a semiconductor integrated circuit package, and more particularly to a semiconductor device that occupies a small area when mounted on a mounting substrate and can be mounted at high density.
半導体集積回路ではその集積度が増大すると通常は外部
引出し端子数が増大する。これをプリント仮などの搭載
基板に信頼度よく接続するためには、隣接端子間に所定
の間隔が必要であり、成る程度の周辺長を必要とするの
でパッケージが大型化する。In semiconductor integrated circuits, as the degree of integration increases, the number of external lead-out terminals usually increases. In order to reliably connect this to a mounting board such as a printed circuit board, a predetermined interval is required between adjacent terminals, and a certain amount of peripheral length is required, which increases the size of the package.
従来外部接続端子数の多い半導体装置のパッケージとし
ては、半導体チップの主面と平行な面内の２つまたは４
つの側面から、パッケージの外部へリード端子が導出し
さらに、直角に下方に曲げられて先端にＬ字状の表面接
続端子部が形成さたフラットバック型やＱ Ｆ Ｐ （
Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）型が用いられて
いる。また最近では、セラミックパッケージの下面の周
縁部に複数の接続バンドを有し、表面実装されるＬ Ｃ
Ｃ（Ｌｅｅｄｌｅｓｓ Ｃｈｉｐ Ｃａｒｒｉｅｒ：リ
ードレスチップキャリヤ）型のパッケージも用いられる
ようになった。Conventionally, packages for semiconductor devices with a large number of external connection terminals have two or four external connection terminals in a plane parallel to the main surface of the semiconductor chip.
A flat back type or Q F P (
Quad Flat Package) type is used. Recently, surface-mounted L C
C (Leedless Chip Carrier) type packages have also come into use.
これらのパッケージは搭載基板にリード端子挿入用のス
ルーホールを必要としない表面実装方式であるため、リ
ード端子の間隔をつめることができパッケージの限られ
た周辺長で端子数を多くとれる。These packages are surface-mounted packages that do not require through-holes on the mounting board for inserting lead terminals, so the spacing between the lead terminals can be reduced and the number of terminals can be increased within the limited peripheral length of the package.
しかしこれらのパッケージはいずれも搭載基板上にねか
せて（即ち表面積最大の面が搭載基板に接するように）
実装されるため基板上での専有面積が大きくなり、高密
度実装に対する制約となる。However, all of these packages should be laid on the mounting board (i.e., the side with the largest surface area should be in contact with the mounting board).
Since it is mounted, the area occupied on the board becomes large, which becomes a constraint on high-density mounting.
そこで搭載基板上での専有面積を減らすために、パッケ
ージの１側面部に外部接続リード端子を配設することに
よって、搭載基板面上に垂直にパッケージを搭載するＳ
Ｉ Ｐ （Ｓｉｎｇｌｅ Ｉｎ−１ｉｎｅ Ｐａｃｋ
ａｇｅ ）型やＺ Ｉ Ｐ （Ｚｉｇ−ｚａｇ Ｉｎ−
１ｉｎｅ Ｐａｃｋａｇｅ）型のパッケージが用いられ
ることも多い。この場合は表面実装型でないため、搭載
基板にリード端子挿入用のスルーホールを設ける必要が
あるため、端子密度をあまり高くすることができず、端
子数が制約される。Therefore, in order to reduce the area occupied on the mounting board, an external connection lead terminal is provided on one side of the package, allowing the package to be mounted vertically on the mounting board surface.
I P (Single In-1ine Pack
age) type and ZIP (Zig-zag In-
1ine Package) type packages are often used. In this case, since it is not a surface mount type, it is necessary to provide a through hole in the mounting board for inserting the lead terminal, so the terminal density cannot be increased very much, and the number of terminals is restricted.
以上説明した如く、従来のＱＦＰやＬＣＣのパッケージ
では搭載時の専有面積が大きくなり基板に高密度に搭載
することができないし、またＳＩＰやＺＩＰは、プリン
ト配線基板にリード端子挿入用のスルーホールを必要と
するので、端子密度を小さくするすることができず端子
数を多くとれない。従って端子数の多い半導体装置を高
密度に搭載基板に実装しようとする場合には、上記いず
れかのパッケージでは不十分であるという問題点があっ
た。As explained above, conventional QFP and LCC packages take up a large area when mounted and cannot be mounted on the board at high density, and SIP and ZIP have through holes on the printed wiring board for inserting lead terminals. Therefore, the terminal density cannot be reduced and the number of terminals cannot be increased. Therefore, when a semiconductor device having a large number of terminals is to be mounted on a mounting board at high density, there is a problem in that any of the above-mentioned packages is insufficient.
そこで本発明は両者を結合させることによって上記問題
点を解決するもので、搭載時の専有面積が小さく、かつ
端子数を多くとれるパッケージを備えた半導体装置を提
供することを目的とする。Therefore, the present invention solves the above problems by combining the two, and aims to provide a semiconductor device equipped with a package that occupies a small area when mounted and can have a large number of terminals.
上記の問題点は、
パッケージ内に収容された半導体チップを搭載基板に接
続する複数のリードが、該半導体チップの主面と平行方
向にパッケージの一側面に導出されさらにその先端が前
記導出の方向と直角な同一面となるように曲折されて表
面実装用の接続パッドもしくは接続端子に形成されてい
ることを特徴とする本発明の半導体装置により解決され
る。The above problem is that the plurality of leads connecting the semiconductor chip housed in the package to the mounting board are led out to one side of the package in a direction parallel to the main surface of the semiconductor chip, and their tips are directed in the direction of the leading out. This problem is solved by the semiconductor device of the present invention, which is bent so as to be on the same plane perpendicular to the surface and formed into a surface mounting connection pad or connection terminal.
全部のリードがパッケージの−の側面に導出しているの
で、パッケージを搭載基板に立てて実装されるため、１
個当たりの専有面積が小さくなり実装密度を向上させる
ことができる。Since all the leads are led out to the - side of the package, the package is mounted upright on the mounting board, so 1.
The area occupied by each device is reduced, and packaging density can be improved.
また搭載基板への接続部として基板と平行な表面実装用
の端子を有するので、搭載基板にスルーホールを設ける
必要がなく、端子の配列ピンチを小さくできるので、外
部接続リードの本数を多（とることができる。In addition, since it has a surface mounting terminal parallel to the board as a connection part to the mounting board, there is no need to provide a through hole on the mounting board, and the arrangement pinch of the terminals can be reduced, so the number of external connection leads can be increased. be able to.
以下添付図により本発明の詳細な説明する。 The present invention will be explained in detail below with reference to the accompanying drawings.
第１図は本発明の１実施例を示す図で、（ａ）は外観斜
視図、（ｂ）は（ａ）におけるＡ−Ａ断面図、第１図は
、外部接続用の接続パッドがパッケージの側面に形成さ
れ、パッケージの外部へリード端子が突出しないＬＣＣ
型のパッケージに本発明を適用したものである。FIG. 1 is a diagram showing one embodiment of the present invention, in which (a) is an external perspective view, (b) is a sectional view taken along line A-A in (a), and FIG. 1 shows that connection pads for external connection are packaged. The LCC is formed on the side of the package so that the lead terminals do not protrude to the outside of the package.
The present invention is applied to a mold package.
図において１は、集積回路が形成された半導体チップ、
２は多層の配線パターンが埋め込まれたセラミックパッ
ケージ、３はキャップである。In the figure, 1 is a semiconductor chip on which an integrated circuit is formed;
2 is a ceramic package in which a multilayer wiring pattern is embedded, and 3 is a cap.
セラミックパッケージ２は多層セラミック板よりなり、
中央に半導体チップ１が接着収納される凹部２２を有し
、眉間には半導体チップ１の主面に平行にパッケージの
一側面にリードとして導出する内部配線パターン２１を
備えている。凹部２２の周辺には内部配線パターン２１
の一部がポンディングパッド２１ａとなって同一面に配
列しており、ボンディングワイヤ４で半導体チソブエと
接続されている。ポンディングパッドの一部はスルーホ
ール２１ｃにより別の層の内部配線パターン２１に接続
されたのち、パッケージの端面まで導出されている。The ceramic package 2 is made of a multilayer ceramic plate,
It has a recess 22 in the center in which the semiconductor chip 1 is adhered and accommodated, and an internal wiring pattern 21 extending as a lead on one side of the package parallel to the main surface of the semiconductor chip 1 between the eyebrows. An internal wiring pattern 21 is formed around the recess 22.
A part of the bonding pads 21a are arranged on the same surface, and are connected to the semiconductor chip by a bonding wire 4. A part of the bonding pad is connected to an internal wiring pattern 21 in another layer through a through hole 21c, and then led out to the end surface of the package.
またパッケージの一側面（図では下面）には表面実装用
の接続パッド２１ｂが例えば２列のジグザグ配列に形成
され、端面に導出する内部配線パターン２１と接続して
いる。この接続パッド２１ｂはタングステンペーストを
所定のパターンに被着・ブレーズしたのち、ニッケル下
地の金めっきして耐蝕性と半田付は性を向上させである
。Furthermore, connection pads 21b for surface mounting are formed in, for example, a two-row zigzag arrangement on one side surface (lower surface in the figure) of the package, and are connected to the internal wiring pattern 21 led out to the end surface. The connection pads 21b are coated with tungsten paste in a predetermined pattern, blazed, and then gold plated on a nickel base to improve corrosion resistance and solderability.
キャンプ３はコバール等の金属よりなり、パッケージに
ボンディングされた半導体子ツブ１を密閉するように、
金−錫合金などで封止される。The camp 3 is made of metal such as Kovar, and is designed to seal the semiconductor chip 1 bonded to the package.
Sealed with gold-tin alloy, etc.
第２図は、本発明の半導体装置の実装状態を示す図であ
る。FIG. 2 is a diagram showing a mounting state of the semiconductor device of the present invention.
上記の如く構成されたＬＣＣパッケージ型の半導体装置
（図の左側の２つ）は、接続パッド２１ｂの配列に対応
してプリント配線板などの搭載基板５の上面に形成され
かつ半田ペースト５２が塗布された半田付はパッド５１
上に載置され、例えば気相加熱（Ｖａｐｏｕｒ−５ｏｌ
ｄｅｒｉｎｇ）などでリフロー半田付けされて、プリン
ト配線基板５に実装される。The LCC package type semiconductor devices (the two on the left side of the figure) configured as described above are formed on the upper surface of a mounting board 5 such as a printed wiring board in correspondence with the arrangement of the connection pads 21b, and solder paste 52 is applied. The soldered pad 51
For example, vapor phase heating (Vapour-5ol
dering), etc., and mounted on the printed wiring board 5.
このように表面積が小さいパッケージの−の側面に外部
接続用の接続バンドが形成されているので、搭載基板上
に立てて搭載することが可能となり、寝かせて実装する
従来のＬＣＣ型パッケージに比べて専有面積が大幅に削
減し、高密度に搭載できる。Since the connection band for external connections is formed on the - side of the package, which has a small surface area, it is possible to mount the package vertically on the mounting board, compared to the conventional LCC type package which is mounted lying down. The dedicated area is significantly reduced, allowing for high-density installation.
さらに搭載基板がエポキシ等の樹脂基板の場合は、パッ
ケージのセラミック材料との熱膨張率の差により半田付
は部に応力が加わり、亀裂が入るなどの不具合があり、
しかもこれはパンケージが基板に接触する面積が大きい
ほど、亀裂障害発生の確率は高まるとされているが、本
発明を適用したＬＣＣパッケージでは、基板と接触する
面積が小さくなるのでこのような不具合の発生が抑制さ
れるという効果もある。Furthermore, if the mounting board is a resin board such as epoxy, the difference in thermal expansion coefficient with the ceramic material of the package causes stress to be applied to the soldering part, causing problems such as cracks.
Moreover, it is said that the larger the area of contact between the pancage and the substrate, the higher the probability of crack failure occurring, but in the LCC package to which the present invention is applied, the area of contact with the substrate is smaller, so such problems are less likely to occur. It also has the effect of suppressing outbreaks.
第３図は他の実施例を示す斜視図である。FIG. 3 is a perspective view showing another embodiment.
これは従来のＺＩＰ型のパッケージに、本発明を適用し
たもので、リード端子が一方向きに導出するように形成
されたリードフレームに半導体装ツブ１をボンディング
接続した後、封止用のエポキシ樹脂などでパンケージ６
の外形を形成し、タイハーカソトで複数のり−ド６１を
独立させる。そして一方に導出したリード６１の先端が
交互に逆方向に直角に曲折されて表面実装用の接続端子
６１ａが形成されている。This is a conventional ZIP type package to which the present invention is applied. After a semiconductor chip 1 is bonded to a lead frame formed so that lead terminals are led out in one direction, epoxy resin for sealing is applied. Pancake 6 with etc.
The outer shape of the board is formed, and the plurality of boards 61 are made independent with a tie-back. The tips of the leads 61 led out to one side are alternately bent at right angles in opposite directions to form connection terminals 61a for surface mounting.
この場合は第２図の右端に示す如く、搭載基板リード端
子挿入用のスルーホールを形成する必要のない表面実装
タイプのＳＩＰ型のパッケージ６となるので、スルーホ
ール径による端子ピッチ制限が緩和され、従来のＺＩＰ
構造に比べて外部引出しり一部６１を増やすことができ
る。In this case, as shown on the right side of Fig. 2, the package 6 is a surface mount type SIP type that does not require the formation of through holes for inserting lead terminals on the mounting board, so the terminal pitch restriction due to the through hole diameter is relaxed. , traditional ZIP
The number of external drawer portions 61 can be increased compared to the structure.
以上述べたように本発明によれば、配線基板上での専有
面積が小さく表面実装可能なパッケージを有する半導体
装置を提供することが可能となり、電子装置の実装密度
の向上に寄与すること顕著である。As described above, according to the present invention, it is possible to provide a semiconductor device having a package that occupies a small area on a wiring board and can be surface mounted, which significantly contributes to improving the packaging density of electronic devices. be.
第１図は本発明の実施例を示す図、
第２図は本発明の半導体装置の実装状態を示す図、
第３図は本発明の他の実施例を示す斜視図、である。
図において、
１−半導体チップ、 ２．６−パッケージ、２１−
内部配線パターン、２１ａ・・−ボンディングパソド
・ ２１ｂ −接続パ、７ド、２１
ｃｍ−スルーホール、３−キャップ、５−搭載基板、
６１・−リード、６１ａ・・・接続端子、
である。
＊１ａｙｑｑイｅｎ’ｉネせ乙４ダ１ジ）免汁ネｉｉコ
第
図
本余日月（ｙ）Ｐｉ蓼イ本業１の宗装状態とオＶす７第
図
（乙と）〉７ト観斜イ兜Ｃ≧り
（し）（α）にお・１するＡ−△〆（ｒ面図Ａに５？５
Ｂ月のソぎ勿礼イケＩＦ示１間第 １ 図FIG. 1 is a diagram showing an embodiment of the invention, FIG. 2 is a diagram showing a mounting state of a semiconductor device of the invention, and FIG. 3 is a perspective view showing another embodiment of the invention. In the figure, 1- semiconductor chip, 2.6- package, 21-
Internal wiring pattern, 21a... - bonding pad, 21b - connection pad, 7 pad, 21
cm - through hole, 3 - cap, 5 - mounting board,
61 - lead, 61a... connection terminal. *1 ayqq yen'i nese etsu 4 da 1 ji) Menu soup cat ii fig. motoyo day moon (y) Pi 蓼ii main job 1's religious attire state and O Vsu 7 fig. (Otsu and)〉7 A-△〆 (5? 5 on r side view A)
B Month's Sogi Butrei Ike IF Show 1st Figure 1
Claims (1)
）を搭載基板（５）に接続する複数の内部配線パターン
（２１）もしくはリード（６１）が、該半導体チップ（
１）の主面と平行方向にパッケージ（２、６）の一側面
に導出されさらにその先端が前記導出の方向と直角な同
一面となるように曲折されて表面実装用の接続パッド（
２１ｂ）もしくは接続端子（６１ａ）に形成されている
ことを特徴とする半導体装置。A semiconductor chip (1) housed in a package (2, 6)
) to the mounting board (5) are a plurality of internal wiring patterns (21) or leads (61) that connect the semiconductor chip (
A connection pad for surface mounting (
21b) or a connecting terminal (61a).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18106488A JPH0230169A (en) | 1988-07-19 | 1988-07-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18106488A JPH0230169A (en) | 1988-07-19 | 1988-07-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0230169A true JPH0230169A (en) | 1990-01-31 |
Family
ID=16094160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18106488A Pending JPH0230169A (en) | 1988-07-19 | 1988-07-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0230169A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032953A (en) * | 1990-08-15 | 1991-07-16 | Pulse Engineering, Inc. | Surface mounted single in-line electronic component package with mounting projections and chamfered viewing edge |
| JPH0786477A (en) * | 1993-09-03 | 1995-03-31 | Internatl Business Mach Corp <Ibm> | Circuit package and its forming method |
| US5621619A (en) * | 1990-10-25 | 1997-04-15 | Cts Corporation | All ceramic surface mount sip and dip networks having spacers and solder barriers |
| US7073605B2 (en) | 2004-03-05 | 2006-07-11 | Hitachi Koki Co., Ltd. | Impact drill |
| US7093670B2 (en) | 2003-08-06 | 2006-08-22 | Hitachi Koki Co., Ltd. | Impact drill |
| US7213659B2 (en) | 2004-03-05 | 2007-05-08 | Hitachi Koki Co., Ltd. | Impact drill |
| JP2009026926A (en) * | 2007-07-19 | 2009-02-05 | Kyocera Corp | Package for housing electronic component |
| US7658238B2 (en) | 2003-08-06 | 2010-02-09 | Hitachi Koki Co., Ltd. | Impact drill |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5839037A (en) * | 1981-09-01 | 1983-03-07 | Nec Corp | Chip carrier |
| JPS6354754A (en) * | 1986-08-25 | 1988-03-09 | Hitachi Ltd | Circuit package |
-
1988
- 1988-07-19 JP JP18106488A patent/JPH0230169A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5839037A (en) * | 1981-09-01 | 1983-03-07 | Nec Corp | Chip carrier |
| JPS6354754A (en) * | 1986-08-25 | 1988-03-09 | Hitachi Ltd | Circuit package |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032953A (en) * | 1990-08-15 | 1991-07-16 | Pulse Engineering, Inc. | Surface mounted single in-line electronic component package with mounting projections and chamfered viewing edge |
| US5621619A (en) * | 1990-10-25 | 1997-04-15 | Cts Corporation | All ceramic surface mount sip and dip networks having spacers and solder barriers |
| JPH0786477A (en) * | 1993-09-03 | 1995-03-31 | Internatl Business Mach Corp <Ibm> | Circuit package and its forming method |
| US7093670B2 (en) | 2003-08-06 | 2006-08-22 | Hitachi Koki Co., Ltd. | Impact drill |
| US7658238B2 (en) | 2003-08-06 | 2010-02-09 | Hitachi Koki Co., Ltd. | Impact drill |
| US7073605B2 (en) | 2004-03-05 | 2006-07-11 | Hitachi Koki Co., Ltd. | Impact drill |
| US7213659B2 (en) | 2004-03-05 | 2007-05-08 | Hitachi Koki Co., Ltd. | Impact drill |
| JP2009026926A (en) * | 2007-07-19 | 2009-02-05 | Kyocera Corp | Package for housing electronic component |
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