JPH0258257A - Semiconductor package with leads - Google Patents
Semiconductor package with leadsInfo
- Publication number
- JPH0258257A JPH0258257A JP20920388A JP20920388A JPH0258257A JP H0258257 A JPH0258257 A JP H0258257A JP 20920388 A JP20920388 A JP 20920388A JP 20920388 A JP20920388 A JP 20920388A JP H0258257 A JPH0258257 A JP H0258257A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- substrate
- package
- lead
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000000919 ceramic Substances 0.000 claims abstract description 42
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 6
- 239000003822 epoxy resin Substances 0.000 abstract 1
- 229920000647 polyepoxide Polymers 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000005219 brazing Methods 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052742 iron Inorganic materials 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007606 doctor blade method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- LWUVWAREOOAHDW-UHFFFAOYSA-N lead silver Chemical compound [Ag].[Pb] LWUVWAREOOAHDW-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野］
本発明は、集積回路、主にＬＳＩチップを搭載し、プリ
ント基板等への実装を容易にするためのリードを備えた
半導体パッケージに閏する。[Detailed Description of the Invention] "Field of Industrial Application" The present invention relates to a semiconductor package mounted with an integrated circuit, mainly an LSI chip, and equipped with leads for easy mounting on a printed circuit board, etc. .
［従来の技術］
ＬＳＩを搭載したリード付き半導体パッケージでは、Ｌ
ＳＩの電極数に応じた多数のリードが必要となり、従来
では、例えば、多層セラミック基板を採用した半導体パ
ッケージ（以下ＩＣパッケージと略す）では、基板の表
面に、メタライズにより得られた配線パターンの引出部
が配列して設けられ、その引出部に、欽・ニッケル系合
金、例えば４２７０イやコバール（Ｋｏｖａｒ）より形
成されるリード（円柱状、平板状がある）を銀ろう付け
で接続して、外部接続端子を形成していた。[Conventional technology] In a leaded semiconductor package equipped with an LSI,
A large number of leads are required depending on the number of electrodes in the SI, and conventionally, for example, in a semiconductor package that uses a multilayer ceramic substrate (hereinafter referred to as an IC package), a wiring pattern obtained by metallization is drawn out on the surface of the substrate. Leads (cylindrical and flat plate shapes available) made of a nickel-based alloy such as 4270I or Kovar are connected to the lead-out portions using silver brazing. It formed an external connection terminal.
［発明が解決しようとする課題１
こうしたＩＣパッケージでは、リード取付けの信頼性を
高める為に、リードは接続強度を確保するに充分な大き
さが必要であり、且つリード間に充分な絶縁間隔が必要
である。それゆえ、ＩＣ素子が微細化し、集積回路が高
密度化するのに伴ない、ＩＣパッケージ内に形成される
集積回路の端子が増加すると、必然的に外部接続端子で
あるリードの数が増加し、リード取付けの信頼性を高め
る為に、ＩＣパッケージは大きくなる。[Problem to be Solved by the Invention 1] In such an IC package, in order to improve the reliability of lead attachment, the leads must be large enough to ensure connection strength, and there must be sufficient insulation spacing between the leads. is necessary. Therefore, as IC elements become smaller and integrated circuits become more densely packed, the number of integrated circuit terminals formed within an IC package increases, which inevitably leads to an increase in the number of leads, which are external connection terminals. , IC packages become larger to increase the reliability of lead attachment.
このため、ＩＣパッケージの製作費は、その大きさに比
例して高価になる。Therefore, the manufacturing cost of an IC package increases in proportion to its size.
また、多層セラミック基板に、多数のリードを直接銀ろ
う付けするため、高価な銀ろう付けが必要になり、且つ
ＩＣチップのマウント部には必要であるがリードには不
要の（Ｎｉ＋Ａｕ）メツキによる表面仕上げがリードに
まで同時に実施されることとなり高価になる。In addition, since many leads are directly silver soldered to the multilayer ceramic substrate, expensive silver soldering is required, and (Ni+Au) plating is required for the IC chip mounting part but not for the leads. Surface finishing is also performed on the leads at the same time, which increases the cost.
本発明は、上記事情に鑑みてなされたもので、その目的
は、多層セラミック基板をできるかぎり小さくするとと
もに、高い信頼性を維持しつつ、ｎつ低価格のリード付
き半導体パッケージの提供にある。The present invention has been made in view of the above circumstances, and its purpose is to provide a leaded semiconductor package that is as low in price as possible while making a multilayer ceramic substrate as small as possible and maintaining high reliability.
［課題を解決するための手段］
本発明は、上記目的を達成するために、集積回路を形成
した半導体素子を搭載するとともに、同一面に前記集積
回路の複数の電極とそれぞれ電気的に接続された複数の
端子を有するセラミックパッケージと、該セラミックパ
ッケージの前記複数の端子にそれぞれ対応して、複数の
リードを固着した絶縁性基板とからなり、前記複数の端
子と前記複数のリードとを接続したことを技術的手段と
する。[Means for Solving the Problems] In order to achieve the above object, the present invention mounts a semiconductor element forming an integrated circuit and electrically connects each to a plurality of electrodes of the integrated circuit on the same surface. a ceramic package having a plurality of terminals, and an insulating substrate to which a plurality of leads are fixed, corresponding to the plurality of terminals of the ceramic package, and the plurality of terminals and the plurality of leads are connected. This is a technical means.
［作用および発明の効果］ 以」−の構成により、次の作用および効果を奏する。[Action and effect of invention] The configuration described below provides the following functions and effects.
（Ａ＞絶縁性基板にリードを取付ける方法は、従来のリ
ード付きＩＣパッケージにおける銀ろう付けに限定され
ず、安価なカシメ、ガラス付け、半田付は等が利用でき
る。(A> The method of attaching leads to an insulating substrate is not limited to silver brazing in conventional leaded IC packages, and inexpensive caulking, glass attachment, soldering, etc. can be used.
（Ｂ）使用するリードの材料は、セラミックとの熱膨張
差を考慮する必要がないため、相系材料、純鉄等の安価
な材料を利用できる。また、リードのメツキをＩＣチッ
プマウント部と別途に行うことができるので、リードに
対してはＡＬＪメツキの必要がなくなり、半田メツキ（
デイツプ）、Ｓｕメツキト半田デイツプ等の安価な手法
が利用できる。(B) Since there is no need to take into account the difference in thermal expansion between the leads and the ceramic, inexpensive materials such as phase-based materials and pure iron can be used. Also, since the leads can be plated separately from the IC chip mount part, there is no need for ALJ plating on the leads, and solder plating (
Inexpensive methods such as dip (dip), Su-metsuki solder dip, etc. can be used.
（Ｃ）セラミックパッケージの製作工程では、リード付
は工程およびＡｕメツキ工程がなくなる為、コストダウ
ンし、さらにリード間の絶縁間隔不足による不良品がで
きないので歩留りも向上する。(C) In the manufacturing process of a ceramic package, the lead attachment process and the Au plating process are eliminated, resulting in cost reductions, and the yield is also improved since there are no defective products due to insufficient insulation spacing between the leads.
（Ｄ）セラミックパッケージに対して、リード取付けの
信頼性と、セラミックパッケージの小型化が可能となり
、コストダウンできる。(D) For ceramic packages, it is possible to improve the reliability of lead attachment and to downsize the ceramic package, resulting in cost reduction.
（Ｅ）絶縁性基板は、特に積層セラミック基板である必
要がなく、安価な絶縁基板を採用できるので、リード取
付けの信頼性を考慮して充分な大きさにしても、コスト
ダウンできる。従って、リードは接続強度を確保するに
充分な大きさにでき、且つリード間は絶縁性を保証する
に充分な間隔を確保できる。(E) The insulating substrate does not need to be a laminated ceramic substrate, and an inexpensive insulating substrate can be used, so the cost can be reduced even if the size is sufficiently large considering the reliability of lead attachment. Therefore, the leads can be made large enough to ensure connection strength, and a sufficient distance can be secured between the leads to ensure insulation.
［実施例］
次に本発明を第１図〜第４１２ｉ１に示す第１実施例に
基づき説明する。[Example] Next, the present invention will be described based on a first example shown in FIGS. 1 to 412i1.
第１図は第１実施例の半導体パッケージの一例であるピ
ン・グリッド・アレイ型ＩＣパッケージ（以下ＰＧＡパ
ッケージと略す）の断面を示す。FIG. 1 shows a cross section of a pin grid array type IC package (hereinafter abbreviated as PGA package), which is an example of the semiconductor package of the first embodiment.
第１実施例のＰＧＡパッケージ１００は、ＩＣチップ（
集積回路が形成された半導体素子）１０を搭載した多層
セラミック基板２０と、リード基板４０とを接続して形
成される。The PGA package 100 of the first embodiment has an IC chip (
It is formed by connecting a multilayer ceramic substrate 20 on which a semiconductor element 10 (on which an integrated circuit is formed) is mounted and a lead substrate 40 .
多層セラミック基板２０は、シート積層法により製造さ
れる。The multilayer ceramic substrate 20 is manufactured by a sheet lamination method.
以下に、多層セラミック基板２０の一最的な構造および
製造方法について説明する。Below, the most suitable structure and manufacturing method of the multilayer ceramic substrate 20 will be explained.
ａ）アルミナを主原料とするセラミック粉末を、ドクタ
ーブレード法によってグリーンシート（未焼結セラミッ
ク生地）に作成する。a) Ceramic powder containing alumina as the main raw material is made into a green sheet (unsintered ceramic material) by the doctor blade method.
ｂ）各グリーンシートにタングステン（Ｗ）やモリブデ
ン（Ｍｏ）などの導体ペーストをスクリーン印刷すると
ともに、後述するバイアホール（Ｖｉａ Ｈｏ１ｅ）
となる孔を打抜き、熱圧着によって各グリーンシートを
積層した後、加湿雰囲気の水素炉中において高温焼成す
る。b) Screen-print a conductive paste such as tungsten (W) or molybdenum (Mo) on each green sheet, and create via holes (Via Hole) as described below.
Holes are punched out and the green sheets are laminated by thermocompression bonding, followed by high-temperature firing in a hydrogen furnace in a humidified atmosphere.
Ｃ）グリーンシートの焼結により多層セラミック基板２
０を得るとともに、グリーンシートにスクリーン印刷さ
れた導体ペーストも焼結して配線パターン２３を形成す
る。この配線パターン２３は、搭載するＩＣチップ（集
積回路が形成された半導体素子）１０の電極と電気的に
接続するもので、配線パターン２３の多層セラミック基
板２０表面への引出部となるバイアホール２２の表面側
には、バイアホール２２に接続して、配線パターン端部
２４がモリブデン（Ｍ ｏ ）またはタングステン（Ｗ
）を主成分とする厚膜または薄膜により形成される。C) Multilayer ceramic substrate 2 by sintering the green sheet
0 is obtained, and the conductor paste screen printed on the green sheet is also sintered to form the wiring pattern 23. This wiring pattern 23 is electrically connected to the electrode of the IC chip (semiconductor element on which an integrated circuit is formed) 10 to be mounted, and a via hole 22 serves as a lead-out portion of the wiring pattern 23 to the surface of the multilayer ceramic substrate 20. The wiring pattern end 24 is connected to the via hole 22 on the surface side of the wiring pattern.
) is formed from a thick or thin film containing as the main component.
ｄ）セラミック基板２０の表面に形成されたメタライズ
層（ＩＣチップのマウント部、ボンディングバット部、
配線パターン端部２４など）にニッケルメッキを施す、
ニッケ、ルメッキが施されたメタライズ層の各部に金メ
ツキを施す。d) A metallized layer formed on the surface of the ceramic substrate 20 (IC chip mount part, bonding butt part,
Nickel plating is applied to the wiring pattern end 24, etc.)
Gold plating is applied to each part of the metallized layer that has been nickel-plated and re-plated.
ｅ）ＩＣチップ１０の搭載やワイ六・ボンディング２５
を確実に行い、キャップ２６をシールする。e) Mounting of IC chip 10 and Wi-6 bonding 25
and seal the cap 26.
つぎにリード基板４０の構造および製造方法について説
明する。Next, the structure and manufacturing method of the lead substrate 40 will be explained.
ｆ）アルミナを主原料とするセラミック粉末を、ドクタ
ーブレード法によってグリーンシート（未焼結セラミッ
ク生地）に作成する。f) Ceramic powder containing alumina as the main raw material is made into a green sheet (unsintered ceramic material) by the doctor blade method.
ｇ）該グリーンシートの前記セラミック基板２０の配線
パターン端部２４に対応する所定位置に、ビン型のリー
ド５０を嵌込む多数の孔４１を打抜き、加浮雰囲気の水
素炉中において高温焼成する９ｈ）焼成しＣできたセラ
ミック製のリード基板４０の孔４１にビン型のリード（
銅系材料、純鉄製等）５０を嵌込む、嵌込まれたリード
５０を、本実施例では、第２図の要部拡大断面図に示す
ガラス付け６０でリード基板４０に固定する。（その他
の変形例として、第３図の要部拡大断面図に示す棒状の
リード５０Ｂをガラス付け６０により固定、第４図の要
部拡大断面図に示すリード５０Ｃをカシメ６１により固
定、第５図の要部拡大断面図に示す半田付け６２による
固定がある。）ｉ）ＦＭ込まれたビン型のリード５０に
半田メツキ（デイツプ）、Ｓｕメツキ十半田デイツプ等
の防錆油［を実施する。g) A large number of holes 41 into which bottle-shaped leads 50 are inserted are punched out at predetermined positions corresponding to the wiring pattern ends 24 of the ceramic substrate 20 of the green sheet, and the green sheet is fired at a high temperature in a hydrogen furnace in a floating atmosphere for 9 hours. ) A bottle-shaped lead (
In this embodiment, the fitted lead 50 into which the lead 50 (made of copper-based material, pure iron, etc.) is fitted is fixed to the lead substrate 40 with a glass attachment 60 shown in an enlarged cross-sectional view of the main part in FIG. (As other modifications, the rod-shaped lead 50B shown in the enlarged cross-sectional view of the main part in FIG. 3 is fixed with a glass attachment 60, the lead 50C shown in the enlarged cross-sectional view of the main part in FIG. Fixation is done by soldering 62 shown in the enlarged sectional view of the main part in the figure.) i) The bottle-shaped lead 50 containing the FM is coated with anti-corrosion oil such as solder plating (dip), Su plating, and solder dip. .
第１実施例のＰＧＡパッケージ１００は、上記に説明し
たごとき製造工程により形成された。多層セラミック基
板２０とリード基板４０とを、配線パターン端部２４と
それに対応するビン型のリード５０の端部５１を半田ま
たは導電性エポキシ７０等より接続してなる。The PGA package 100 of the first example was formed by the manufacturing process described above. The multilayer ceramic substrate 20 and the lead substrate 40 are connected to each other by connecting the wiring pattern ends 24 and the corresponding ends 51 of the bottle-shaped leads 50 using solder, conductive epoxy 70, or the like.
この工程を従来の一般的製造工程と比較すると、従来の
リード付き多層セラミック基板では、熱圧る°と高温焼
成により配線パターンを有する多層セラミック基板分形
成したあとのＩＫ！遣工程が、リード銀ろう付は荊のメ
タライズ層にニッケルメッキする工程−リードを銀ろう
付けする［稈−リード銀ろう付は後のニッケルメッキす
る工程−ニッケルメッキが施されたメタライズ層（ＩＣ
チップのマウント部、ボンディングバット部、リードな
ど）の各部に金メツキする工程と変わる。Comparing this process with the conventional general manufacturing process, in the conventional leaded multilayer ceramic substrate, the IK! Lead silver brazing is a process of nickel plating the metallized layer of the culm - silver brazing the lead [culm - lead silver brazing is a process of nickel plating later - the nickel plated metallized layer (IC
The process changes to the process of gold plating each part (chip mount, bonding butt, leads, etc.).
以上の変化のような従来の一般的製造工程と比較して本
実施例の製造工程は、
（１）ニッケルメッキの回数および面積が減少する。Compared to the conventional general manufacturing process as described above, the manufacturing process of this embodiment has the following: (1) The number of times and area of nickel plating is reduced.
（２）金メツキの面積が減少する。(2) The area of gold plating decreases.
また、別体のリード基板４０にリード５０を取付けるた
め、
（３）リード５０の取付けに、高価な銀ろう付けに限定
されず、安価なカシメ６１、ガラス付け６０、高温半田
付け６２等が利用できる。In addition, since the leads 50 are attached to the separate lead board 40, (3) the attachment of the leads 50 is not limited to expensive silver brazing, but inexpensive caulking 61, glass attachment 60, high temperature soldering 62, etc. can be used. can.
（４）使用する金属リードの材料は、セラミックとの熱
膨張差が考慮不要であるム、銅系材料、純鉄等の安価な
材料を利用できる。(4) As the material of the metal lead used, inexpensive materials such as aluminum, copper-based materials, and pure iron, which do not require consideration of the difference in thermal expansion with ceramic, can be used.
（５）多層セラミック基板２０を高密度にし、小さくで
きる。(5) The multilayer ceramic substrate 20 can be made high-density and small.
以上のｒ稈により、信頼性の高い多層セラミック基１ｉ
２０を採用し、信頼性が高く且つ従来の物に比べて低価
格に製造できる。With the above r culm, a highly reliable multilayer ceramic base 1i
20, it is highly reliable and can be manufactured at a lower cost than conventional products.
つぎに第６図に断面図で示す第２実施例について説明す
る。Next, a second embodiment shown in a sectional view in FIG. 6 will be described.
第２実施例のＩＣパッケージ２００は、ＩＣチップ１０
を搭載してなる多層セラミック基板２０と、リード基板
４ＯＡとを接続して形成される。The IC package 200 of the second embodiment includes an IC chip 10
It is formed by connecting a multilayer ceramic substrate 20 mounted with a lead substrate 4OA.
多層セラミック基板２０の構造および！！道方法は、第
１実施例と同様であり同等物は同一符号で表す。Structure of multilayer ceramic substrate 20 and! ! The method is the same as in the first embodiment, and equivalents are denoted by the same reference numerals.
つぎにリード基板４０Ａの構造および製造方法について
説明する。Next, the structure and manufacturing method of the lead substrate 40A will be explained.
ｊ）アルミナを主原料とするセラミック粉末を、ドクタ
ーブレード法によってグリーンシート（未焼結セラミッ
ク生地）に作成する。j) Ceramic powder whose main raw material is alumina is made into a green sheet (unsintered ceramic material) by the doctor blade method.
ｋ）グリーンシートを加湿雰囲気の水素炉中において高
温焼成する。k) The green sheet is fired at high temperature in a hydrogen furnace in a humidified atmosphere.
ｌ）焼成してできたセラミック製のリード基板４０Ａの
上面に、多数の屈曲した平板状のリード（銅系材料、１
４鉄製等）５０Ａをガラス付けまたは樹脂接着剤で固着
させ、リード５０Ａの端部５１Ａを配線パターン端部２
４に対応さぜる。l) A large number of bent flat leads (copper-based material, 1
4 iron, etc.) 50A with glass or resin adhesive, and connect the end 51A of the lead 50A to the wiring pattern end 2.
Correspond to 4.
以上の工程により、リード基板４０Ａが形成される。Through the above steps, the lead substrate 40A is formed.
第２実施例のＩＣパッケージ２００は、第１実施例と同
様の！！造工程により形成された多層セラミック基板２
０と、リード基板４０Ａとを、配線パターン端部２４と
それに対応する屈曲した平板状のり−ド５０Ａの端部５
１Ａを半田または導電性エポキシ７０等より接続してな
る。The IC package 200 of the second embodiment is similar to that of the first embodiment! ! Multilayer ceramic substrate 2 formed by the manufacturing process
0 and the lead board 40A, the wiring pattern end 24 and the corresponding end 5 of the bent flat board 50A.
1A is connected by solder or conductive epoxy 70 or the like.
第２実施例の効果は、第１実施例の効果と同様である。The effects of the second embodiment are similar to those of the first embodiment.
つぎにリード基板の変形例を記す。Next, a modified example of the lead board will be described.
上記の第１および第２実施例のリード基板４０゜４０Ａ
は、グリーンシートを焼成したセラミック基板を用いた
が、粉末プレス成型した後に焼成したセラミック基板を
用いても良いのは当然である。Lead board 40°40A of the above first and second embodiments
used a ceramic substrate obtained by firing a green sheet, but it goes without saying that a ceramic substrate obtained by powder press molding and then firing may also be used.
また、リード基板として樹脂製の基板を用いても良い、
樹脂基板を用いればセラミック基板より安価になるが、
セラミック製の半導体基板との熱膨張差において相性が
劣るので大型品には不向きである。Additionally, a resin substrate may be used as the lead substrate.
Using a resin substrate is cheaper than a ceramic substrate, but
It is not suitable for large products because it has poor compatibility with ceramic semiconductor substrates in terms of thermal expansion difference.
第１図は本発明に係るｖ・Ｓ体パッケージの第１実施例
であるＰＧＡパッケージの断面図、第２図はそのリード
ｇ、板の要部拡大断面図、第３図はそのリード基板のリ
ードの変形例の要部拡大断面図、第４図はそのリード基
板のリードの固定方法の変形例の要部拡大断面図、第５
図はそのリード基板のリードの固定方法の変形例の要部
拡大断面図、第６図は第２実施例であるＩＣパッケージ
の断面図である。
図中、１０・・・ＩＣチップ（半導体素子）、２゜・・
多層セラミック基板（セラミックバラゲージ〉、２４・
・配線ハターン端部（端子）、４ｏ、４０Ａ・・・リー
ド基板〈絶縁性基板）、５０．５０Ａ、５０Ｂ、５０Ｃ
・・・リード。
＼
＼
第１図Fig. 1 is a sectional view of a PGA package which is a first embodiment of the v/S body package according to the present invention, Fig. 2 is an enlarged sectional view of the main parts of the lead g and plate, and Fig. 3 is an enlarged sectional view of the lead board. FIG. 4 is an enlarged cross-sectional view of the main part of a modified example of the lead, and FIG.
The figure is an enlarged sectional view of a main part of a modification of the method of fixing the leads of the lead board, and FIG. 6 is a sectional view of an IC package according to the second embodiment. In the figure, 10...IC chip (semiconductor element), 2°...
Multilayer ceramic substrate (ceramic barrier gauge), 24.
・Wiring pattern end (terminal), 4o, 40A...Lead board (insulating board), 50.50A, 50B, 50C
...Lead. ＼ ＼ Figure 1
Claims (1)
、同一面に前記集積回路の複数の電極とそれぞれ電気的
に接続された複数の端子を有するセラミックパッケージ
と、 該セラミックパッケージの前記複数の端子にそれぞれ対
応して、複数のリードを固着した絶縁性基板とからなり
、 前記複数の端子と前記複数のリードとを接続したことを
特徴とするリード付き半導体パッケージ。[Scope of Claims] 1) A ceramic package that mounts a semiconductor element forming an integrated circuit and has a plurality of terminals electrically connected to a plurality of electrodes of the integrated circuit on the same surface; and the ceramic package. A semiconductor package with leads, comprising: an insulating substrate to which a plurality of leads are fixed, corresponding to the plurality of terminals, respectively, the plurality of terminals and the plurality of leads being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20920388A JPH0258257A (en) | 1988-08-23 | 1988-08-23 | Semiconductor package with leads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20920388A JPH0258257A (en) | 1988-08-23 | 1988-08-23 | Semiconductor package with leads |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0258257A true JPH0258257A (en) | 1990-02-27 |
Family
ID=16569060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20920388A Pending JPH0258257A (en) | 1988-08-23 | 1988-08-23 | Semiconductor package with leads |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0258257A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0536802A2 (en) * | 1991-10-11 | 1993-04-14 | Nec Corporation | Multilayer circuit board with repaired I/O pin and process for repairing I/O pin on multilayer circuit board |
| DE19523169C1 (en) * | 1995-06-26 | 1996-09-26 | Dainippon Ink & Chemicals | Prodn. of acryloyl-carbamate and acryloyl-urea cpds. |
| US5712768A (en) * | 1992-12-30 | 1998-01-27 | Interconnect Systems, Inc. | Space-saving assemblies for connecting integrated circuits to circuit boards |
| US5977623A (en) * | 1996-10-04 | 1999-11-02 | Lg Semicon Co., Ltd. | Semiconductor package and socket thereof and methods of fabricating same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56120147A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Integrated circuit package |
| JPS5835955A (en) * | 1981-08-28 | 1983-03-02 | Nec Corp | Structure of multilayer wiring substrate |
| JPH022151A (en) * | 1988-06-15 | 1990-01-08 | Hitachi Ltd | Package structure |
-
1988
- 1988-08-23 JP JP20920388A patent/JPH0258257A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56120147A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Integrated circuit package |
| JPS5835955A (en) * | 1981-08-28 | 1983-03-02 | Nec Corp | Structure of multilayer wiring substrate |
| JPH022151A (en) * | 1988-06-15 | 1990-01-08 | Hitachi Ltd | Package structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0536802A2 (en) * | 1991-10-11 | 1993-04-14 | Nec Corporation | Multilayer circuit board with repaired I/O pin and process for repairing I/O pin on multilayer circuit board |
| US5712768A (en) * | 1992-12-30 | 1998-01-27 | Interconnect Systems, Inc. | Space-saving assemblies for connecting integrated circuits to circuit boards |
| DE19523169C1 (en) * | 1995-06-26 | 1996-09-26 | Dainippon Ink & Chemicals | Prodn. of acryloyl-carbamate and acryloyl-urea cpds. |
| US5977623A (en) * | 1996-10-04 | 1999-11-02 | Lg Semicon Co., Ltd. | Semiconductor package and socket thereof and methods of fabricating same |
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