JPS6318335B2 - - Google Patents
Info
- Publication number
- JPS6318335B2 JPS6318335B2 JP54111894A JP11189479A JPS6318335B2 JP S6318335 B2 JPS6318335 B2 JP S6318335B2 JP 54111894 A JP54111894 A JP 54111894A JP 11189479 A JP11189479 A JP 11189479A JP S6318335 B2 JPS6318335 B2 JP S6318335B2
- Authority
- JP
- Japan
- Prior art keywords
- lead electrode
- semiconductor element
- opening
- film carrier
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 description 18
- 239000000758 substrate Substances 0.000 description 18
- 229910015363 Au—Sn Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Description
【発明の詳細な説明】
本発明は半導体装置およびその製造方法に関
し、特に、半導体素子上の電極上に形成した金属
突起物と、フイルムキヤリヤ上にこれと対応した
位置のビーム状のリード電極とを同時にホンデイ
ングを行なう、いわゆるフイルムキヤリヤ実装方
式において、クロスオーバ配線用のリード電極を
有したフイルムキヤリヤを用いた半導体装置を提
供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a metal protrusion formed on an electrode on a semiconductor element and a beam-shaped lead electrode at a corresponding position on a film carrier. The present invention provides a semiconductor device using a film carrier having lead electrodes for crossover wiring in a so-called film carrier mounting method in which bonding is carried out at the same time.
従来半導体素子上の電極と外部回路と接続され
る端子とを電気的に接続する手段として最も一般
的であるが、25〜37μm2のAu又はAl線によつて、
熱圧着法、超音波法等によつて行なういわゆるワ
イヤボンデイング法が知られている。 Conventionally, the most common means of electrically connecting electrodes on semiconductor elements and terminals connected to external circuits is by Au or Al wires of 25 to 37 μm2 .
A so-called wire bonding method is known, which is performed using a thermocompression method, an ultrasonic method, or the like.
この様な方法は半導体素子上の電極と外部回路
と接続される端子とを一本づつワイヤボンデイン
グしなければならない。このため、前記電極数が
増加するに従がい、ワイヤボンデイングのための
作業時間が著じるしく増加したり、あるいは特別
な形状を有した回路基板に前記半導体素子を載置
してワイヤボンデイングする場合は、回路基板の
形状が複雑になつたり、回路基板上に多数個の半
導体素子を載置するにしたがい、ワイヤボンデイ
ングの作業能率は低下し、更にボンデイングの信
頼性も低下さすものであつた。 In this method, electrodes on the semiconductor element and terminals connected to an external circuit must be wire bonded one by one. Therefore, as the number of electrodes increases, the working time for wire bonding increases significantly, or wire bonding is performed by placing the semiconductor element on a circuit board having a special shape. In this case, as the shape of the circuit board becomes more complex or a large number of semiconductor elements are placed on the circuit board, the efficiency of wire bonding decreases, and the reliability of the bonding also decreases. .
この様な欠点を一掃するために、半導体素子上
の電極に一度に全部のリード電極を形成させるワ
イヤレス技術があり、この中でも特に本発明でも
説明するフイルムキヤリヤ実装法は最近、特にそ
の作業性、信頼性等の優秀さから注目をあびてき
ている。 In order to eliminate such drawbacks, there is a wireless technology that forms all lead electrodes on the electrodes on a semiconductor element at once.Among these, the film carrier mounting method, which will be described in the present invention, has recently been developed with particular emphasis on workability. It has been attracting attention due to its excellent reliability.
フイルムキヤリヤ実装法は先ず、ウエハー段階
で前記半導体素子上の電極上に真空蒸着法により
Cr膜を1000Å、Cu膜を5000Å被着せしめ、次い
で電気メツキ法により、Au、Cu等の材料を10〜
30μｍ厚さに堆積せしめていわゆる金属突起物を
形成する。一方、ポリイミド樹脂からなるフイル
ムに35μｍ厚さのCu箔を貼りつけ、前記半導体素
子上の金属突起物と合致する位置に、フオトエツ
チング法によりCuパターンによるリード電極を
形成し、最後に前記Cuリード電極にSnメツキを
行なえば、連続したフイルムキヤリヤが出来上
る。 In the film carrier mounting method, first, at the wafer stage, a vacuum evaporation method is applied to the electrodes on the semiconductor element.
A Cr film of 1000 Å and a Cu film of 5000 Å are deposited, and then materials such as Au and Cu are deposited for 10 to 10 Å by electroplating.
It is deposited to a thickness of 30 μm to form so-called metal protrusions. On the other hand, a 35 μm thick Cu foil is attached to a film made of polyimide resin, and a lead electrode is formed using a Cu pattern using a photoetching method at a position that matches the metal protrusion on the semiconductor element, and finally the Cu lead If the electrode is plated with Sn, a continuous film carrier will be created.
こうしたのち、半導体素子上の金属突起物と
Cuリード電極とを第１図のごとく接続する。半
導体素子１上の金属突起物２とフイルムキヤリヤ
３上に形成されSnメツキしたCuリード電極４と
を位置合せし、Cuリード電極４上から、例えば、
温度450℃、加圧力20ｇ／電極を作用させれば、
金属突起物２とCuリード電極４とは共晶を起こ
し、機械的、電気的に接続される。ここで金属突
起物２がAuであれば、Cuリード電極４はSnメツ
キされているから約280℃位でAu−Snの合金を
形成して接着される事になる。 After this, metal protrusions on the semiconductor element and
Connect to the Cu lead electrode as shown in Figure 1. The metal protrusion 2 on the semiconductor element 1 and the Sn-plated Cu lead electrode 4 formed on the film carrier 3 are aligned, and from above the Cu lead electrode 4, for example,
If the temperature is 450℃ and the pressure is 20g/electrode,
The metal protrusion 2 and the Cu lead electrode 4 form eutectic and are mechanically and electrically connected. Here, if the metal protrusion 2 is Au, the Cu lead electrode 4 is plated with Sn, so it will be bonded by forming an Au-Sn alloy at about 280°C.
第１図においてフイルムキヤリヤ３の孔５は半
導体素子１を設置するための開孔部であり、孔６
はフイルムキヤリヤ３は数十ｍの長さに及ぶもの
であるから、このフイルムキヤリヤ３を正確に巻
き取りあるいは送るための開孔部である。更に
Cuリード電極で７の巾広い部分は、第１図の如
く半導体素子１がCuリード電極４と同時に接続
された後、電気的検査を行なうための触針用端子
部である。 In FIG. 1, the hole 5 of the film carrier 3 is an opening for installing the semiconductor element 1, and the hole 6
Since the film carrier 3 has a length of several tens of meters, this is an opening for accurately winding or feeding the film carrier 3. Furthermore
The wide portion 7 of the Cu lead electrode is a terminal portion for a stylus for electrical testing after the semiconductor element 1 is connected to the Cu lead electrode 4 at the same time as shown in FIG.
次に第１図の如く接続が終れば、Cuリード電
極４は孔５の端で切断される。 Next, when the connection is completed as shown in FIG. 1, the Cu lead electrode 4 is cut at the end of the hole 5.
第２図はセラミツク基板１１上に印刷配線パタ
ーン１２があり、この基板１１上に他の部品とと
もに素子１を装着した状態を示す。印刷配線パタ
ーン１２の端部がセラミツク基板１１の周縁で巾
広くなつているのは、他の回路と半田づけを行な
うための端子１３である。更に１５は例えばチツ
プ状の抵抗、コンデンサ等であつて、セラミツク
基板上１１に半田づけされる。第１図で説明した
ごとく孔５の端部でCuリード電極４′と接続され
た半導体素子１は、前記セラミツク基板１１上の
印刷配線パターン１２′と切断されたCuリード電
極４′とを位置合せし、これも又、全部のリード
電極を同時に半田又はAu−Sn等の合金化により
接続する。第２図の如くCuリード電極４′をもつ
半導体素子１をセラミツク基板１１に載置する事
によりセラミツク基板は、ひとつの回路機能を有
するものとなる。 FIG. 2 shows a state in which a printed wiring pattern 12 is provided on a ceramic substrate 11, and the element 1 is mounted on this substrate 11 together with other parts. The ends of the printed wiring pattern 12 that become wider at the periphery of the ceramic substrate 11 are terminals 13 for soldering to other circuits. Furthermore, numeral 15 is, for example, a chip-shaped resistor, capacitor, etc., which is soldered to the ceramic substrate 11. As explained in FIG. 1, the semiconductor element 1 is connected to the Cu lead electrode 4' at the end of the hole 5, and the printed wiring pattern 12' on the ceramic substrate 11 and the cut Cu lead electrode 4' are aligned. Again, all the lead electrodes are connected at the same time by soldering or alloying with Au-Sn or the like. As shown in FIG. 2, by placing a semiconductor element 1 having a Cu lead electrode 4' on a ceramic substrate 11, the ceramic substrate has one circuit function.
ところが、この様な回路構成において、印刷配
線パターン１３′と、前記印刷配線パターン１
３′とは半導体素子１に対して反対側にある印刷
配線パターン１３″とを点線の如く接続する場合、
セラミツク基板１１の印刷配線パターンの回路構
成では困難である。このような接続は多層印刷配
線とスルーホールによつて実現する事も出来る
が、この場合は前記セラミツク基板１１の製造コ
ストが著じるしく高価になる。第３図は前記第２
図のセラミツク基板を図示したＡ−A′の部分の
断面図を示すものである。 However, in such a circuit configuration, the printed wiring pattern 13' and the printed wiring pattern 1
3' is connected to the printed wiring pattern 13'' on the opposite side to the semiconductor element 1 as shown by the dotted line,
This is difficult with the circuit configuration of the printed wiring pattern of the ceramic substrate 11. Such a connection can also be realized by multilayer printed wiring and through holes, but in this case the manufacturing cost of the ceramic substrate 11 becomes significantly high. Figure 3 shows the second
2 is a sectional view taken along line A-A' of the ceramic substrate shown in the figure.
第３図ａに示す様に半導体素子１は放熱を必要
とするときセラミツク基板１１上に導電性接着剤
２１で固定され、そうでない場合はｂのごとくセ
ラミツク基板１１の開孔部２２に半導体素子１が
設置される。すなわち、第３図から明らかなごと
く印刷配線パターン１３′と１３″との接続は容易
でない。 As shown in FIG. 3a, the semiconductor element 1 is fixed on the ceramic substrate 11 with a conductive adhesive 21 when heat dissipation is required; otherwise, the semiconductor element 1 is fixed in the opening 22 of the ceramic substrate 11 as shown in FIG. 3b. 1 is installed. That is, as is clear from FIG. 3, it is not easy to connect the printed wiring patterns 13' and 13''.
本発明は、従来困難であつたクロスオーバーの
配線の問題をフイルムキヤリヤを用いて著じるし
く容易に解決せんとするものである。第４図で本
発明の一実施例を説明する。 The present invention aims to significantly and easily solve the problem of crossover wiring, which has been difficult in the past, by using a film carrier. An embodiment of the present invention will be explained with reference to FIG.
第４図ａにおいて、半導体素子上の金属突起物
と接続するためのCuリード電極４以外に前記フ
イルムキヤリヤ３の半導体素子載置部の開孔部５
の一辺から他辺へ延在し、連続したCuリード電
極３１を形成する。 In FIG. 4a, in addition to the Cu lead electrode 4 for connecting to the metal protrusion on the semiconductor element, the opening 5 of the semiconductor element mounting part of the film carrier 3 is shown.
A continuous Cu lead electrode 31 is formed extending from one side to the other side.
次にフイルムキヤリヤ３の開孔部５に半導体素
子１を設置し、半導体素子１上の金属突起物２と
前記Cuリード端子４とを位置合せし、例えば温
度450℃で、加圧力20ｇ／電極を加えれば、金属
突起起物（金属突起物をAuとする。）２とCuリ
ード電極（Cu部分に0.4μｍ程度のSnメツキが施
こされている。）４とはAu−Snの共晶を起こし、
機械的、電気的に接続される（第４図ｂ）。この
状態にいては、Cuリード電極３１は半導体素子
１とは接しておらず、開孔部５の周縁のフイルム
キヤリヤ部に固定されている。 Next, the semiconductor element 1 is placed in the opening 5 of the film carrier 3, the metal protrusion 2 on the semiconductor element 1 and the Cu lead terminal 4 are aligned, and the temperature is 450°C, for example, and the pressing force is 20g/ If electrodes are added, the metal protrusions (the metal protrusions are Au) 2 and the Cu lead electrode (Sn plating of about 0.4 μm is applied to the Cu part) 4 are Au-Sn common. Wake up Akira,
mechanically and electrically connected (Figure 4b). In this state, the Cu lead electrode 31 is not in contact with the semiconductor element 1, but is fixed to the film carrier portion at the periphery of the opening 5.
次に二点鎖点で示した位置４１よりフイルムキ
ヤリヤ３を含めて切断する。第４図ｃはフイルム
キヤリヤ３′を残して切断した状態を示す。切断
されたフイルムキヤリヤ３′は半導体素子１を囲
む様構成され、全てのCuリード電極４′，３１が
前記フイルムキヤリヤ３′に固定された構造とな
る。切断されたフイルムキヤリヤ３′は主に開孔
部５の一辺から他辺へ延在したCuリード電極３
１を固定する役目を行なう他、他のCuリード電
極４′の先端が機械的な衝撃によつて曲がつたり
折れたりする事を防止する役目も行なうものであ
る。 Next, the film carrier 3 is cut from a position 41 indicated by a double-dotted chain dot. FIG. 4c shows the state in which the film carrier 3' is cut away. The cut film carrier 3' is constructed to surround the semiconductor element 1, and all the Cu lead electrodes 4', 31 are fixed to the film carrier 3'. The cut film carrier 3' mainly contains the Cu lead electrode 3 extending from one side of the opening 5 to the other side.
In addition to the role of fixing the Cu lead electrode 1, it also serves to prevent the tip of the other Cu lead electrode 4' from bending or breaking due to mechanical impact.
次に第４図ｃの如く切断された状態のフイルム
キヤリヤと半導体素子はたとえば第４図ｄのごと
くセラミツク基板１１上に実装される。Cuリー
ド電極子４′はセラミツク基板１１上に印刷され
た配線パターン１２′と、更にCuリード電極３１
は配線パターン１３′と１３″とに接続され、クロ
スオーバ配線となり所定の電気回路を構成するも
のである。Cuリード電極と配線パターンとの接
続は例えばCuリード電極にSnメツキされており
配線パターン半田メツキで構成されておれば、
Cuリード電極と配線パターンとを位置合せしCu
リード電極を押えながら300℃程度に加熱する事
により可能である。なお、Cuリード電極４′と印
刷配線パターン１２′は第４図ｅの如く４５の位
置で半田づけされる。 Next, the film carrier and semiconductor element cut as shown in FIG. 4c are mounted on a ceramic substrate 11 as shown in FIG. 4d, for example. The Cu lead electrode element 4' has a wiring pattern 12' printed on the ceramic substrate 11 and a Cu lead electrode 31.
is connected to the wiring patterns 13' and 13'', forming a crossover wiring and configuring a predetermined electric circuit.For example, the Cu lead electrode is plated with Sn, and the wiring pattern is connected to the Cu lead electrode with Sn plating. If it is composed of solder plating,
Align the Cu lead electrode with the wiring pattern and
This can be done by heating the lead electrode to around 300℃ while holding it down. Incidentally, the Cu lead electrode 4' and the printed wiring pattern 12' are soldered at position 45 as shown in FIG. 4e.
たとえば、半導体素子１は導電性接着剤２１に
よつてセラミツク基板１１上に接着され、金属突
起物２に例えばAu−Snの共晶によつて接続され
たCuリード電極４′は印刷配線１２′と位置合わ
せし、加圧加熱する事により４５の部分半田づけ
される。また、切断されたフイルムキヤリヤ３′
は図の如く印刷配線パターン上に来る事になる。 For example, the semiconductor element 1 is bonded onto a ceramic substrate 11 with a conductive adhesive 21, and the Cu lead electrode 4' connected to the metal protrusion 2 by, for example, Au-Sn eutectic, is connected to the printed wiring 12'. 45 is partially soldered by positioning and applying pressure and heat. Also, the cut film carrier 3'
will appear on the printed wiring pattern as shown in the figure.
他の実施例を第５図で説明する。使用するフイ
ルムキヤリヤ３は前述した実施例と同一のもので
あるが、半導体素子上に金属突起物３２を設け、
前述した方法によりCuリード電極４，３１を接
続すれば第５図ａの状態を得る。すなわちCuリ
ード電極３１は半導体素子１上の金属突起物３２
によつて固定される事になる。この状態で２点鎖
点３５の位置で切断すれば第５図ｂの状態を得
る。この実施例においては開孔部の一辺から他辺
へ延在したCuリード電極３１は金属突起物３２
で固定されるので第４図ｃの実施例の如くのフイ
ルムキヤリヤ３′は必要としない。 Another embodiment will be explained with reference to FIG. The film carrier 3 used is the same as in the above-mentioned embodiment, but a metal protrusion 32 is provided on the semiconductor element.
If the Cu lead electrodes 4 and 31 are connected by the method described above, the state shown in FIG. 5a is obtained. That is, the Cu lead electrode 31 is connected to the metal protrusion 32 on the semiconductor element 1.
It will be fixed by. In this state, if the wire is cut at the double-dot chain point 35, the state shown in FIG. 5b will be obtained. In this embodiment, the Cu lead electrode 31 extending from one side of the opening to the other side is formed by a metal protrusion 32.
Therefore, a film carrier 3' as in the embodiment of FIG. 4c is not required.
この様に本発明は、セラミツク基板１１の印刷
配線パターンにスルーホールや多層印刷等の複雑
な処理を施こす必要もなく、半導体素子１の接続
時に著じるしく容易にクロスオーバ配線を実施出
来る。又、前記開口部の一辺から他辺へ延在した
Cuリード電極３１は他のCuリード電極４の形成
時に同時に形成出来、新たに別の工程を準備する
ことなくクロスオーバ配線の形成ができる等の効
果を有するものである。したがつて複雑な配線を
処理する場合、容易に本発明の方法を用いる事が
出来、安価な実装を提供することが出来、半導体
装置の実装に大きく寄与するものである。 As described above, the present invention does not require complex processing such as through holes or multilayer printing on the printed wiring pattern of the ceramic substrate 11, and it is possible to perform crossover wiring with remarkable ease when connecting the semiconductor elements 1. . Further, the opening extends from one side to the other side of the opening.
The Cu lead electrode 31 can be formed at the same time as the other Cu lead electrodes 4, and has the advantage that crossover wiring can be formed without preparing another process. Therefore, when processing complicated wiring, the method of the present invention can be easily used and inexpensive packaging can be provided, which greatly contributes to the packaging of semiconductor devices.
第１図は従来のフイルムキヤリヤの要部平面
図、第２図は従来のフイルムキヤリヤを実装した
セラミツク基板への平面図、第３図ａ，ｂは第２
図のＡ−A′線のセラミツク基板の断面図、第４
図ａ〜ｄは本発明の一実施例のフイルムキヤリヤ
半導体装置の製造工程図、第４図ｅは第４図ｄの
Ｂ−B′線の部分断面図、第５図ａ，ｂは本発明
の他の実施例の方法の工程平面図である。
１……半導体素子、２……金属突起物、４，
４′……Cuリード電極、５……開孔部、１１……
セラミツク基板、１２′，１３′，１３″……配線
パターン。
Fig. 1 is a plan view of the main part of a conventional film carrier, Fig. 2 is a plan view of a ceramic substrate on which the conventional film carrier is mounted, and Figs.
Cross-sectional view of the ceramic substrate taken along line A-A' in the figure, No. 4
Figures a to d are manufacturing process diagrams of a film carrier semiconductor device according to an embodiment of the present invention, Figure 4e is a partial sectional view taken along line B-B' in Figure 4d, and Figures 5a and b are the main FIG. 7 is a process plan view of a method according to another embodiment of the invention. 1...Semiconductor element, 2...Metal protrusion, 4,
4'...Cu lead electrode, 5...Opening part, 11...
Ceramic board, 12', 13', 13''...wiring pattern.
Claims (1)
部に突出したリード電極と、前記開孔部内に載置
された前記半導体素子上に形成され前記開孔部の
一辺から他辺へ延在するリード電極とを有するこ
とを特徴とする半導体装置。 ２ 開孔部の一辺から他辺へ延在するリード電極
の一部が半導体素子上の金属突起物と接続されて
なる事を特徴とする特許請求の範囲第１項に記載
の半導体装置。 ３ 半導体素子を載置するためのフイルムに開孔
部を設けるとともに、このフイルム上に前記開孔
部に突出したリード電極と、前記開孔部内に載置
される前記半導体素子上に位置して前記開孔部の
一辺から他辺へ延在するリード電極を形成する工
程と、前記開孔部内に前記半導体素子を載置する
工程を有することを特徴とする半導体装置の製造
方法。[Scope of Claims] 1. A lead electrode protruding into an opening of a film for placing a semiconductor element, and a lead electrode formed on the semiconductor element placed in the opening and extending from one side of the opening. A semiconductor device characterized by having a lead electrode extending to the other side. 2. The semiconductor device according to claim 1, wherein a part of the lead electrode extending from one side of the opening to the other side is connected to a metal protrusion on the semiconductor element. 3. An opening is provided in a film for placing a semiconductor element, and a lead electrode is provided on the film that protrudes into the opening, and a lead electrode is located on the semiconductor element placed in the opening. A method for manufacturing a semiconductor device, comprising the steps of: forming a lead electrode extending from one side of the opening to the other side; and placing the semiconductor element in the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11189479A JPS5636147A (en) | 1979-08-31 | 1979-08-31 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11189479A JPS5636147A (en) | 1979-08-31 | 1979-08-31 | Semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5636147A JPS5636147A (en) | 1981-04-09 |
| JPS6318335B2 true JPS6318335B2 (en) | 1988-04-18 |
Family
ID=14572797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11189479A Granted JPS5636147A (en) | 1979-08-31 | 1979-08-31 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5636147A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331565U (en) * | 1986-08-14 | 1988-03-01 | ||
| US4903113A (en) * | 1988-01-15 | 1990-02-20 | International Business Machines Corporation | Enhanced tab package |
| JP2682072B2 (en) * | 1988-10-28 | 1997-11-26 | 日本電気株式会社 | Hybrid integrated circuit device |
| GB2292004A (en) * | 1994-07-29 | 1996-02-07 | Ibm Uk | Electronic circuit package |
| JP4529216B2 (en) * | 2000-01-25 | 2010-08-25 | 凸版印刷株式会社 | IC card and manufacturing method thereof |
-
1979
- 1979-08-31 JP JP11189479A patent/JPS5636147A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5636147A (en) | 1981-04-09 |
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