GB2292004A - Electronic circuit package - Google Patents
Electronic circuit package Download PDFInfo
- Publication number
- GB2292004A GB2292004A GB9415297A GB9415297A GB2292004A GB 2292004 A GB2292004 A GB 2292004A GB 9415297 A GB9415297 A GB 9415297A GB 9415297 A GB9415297 A GB 9415297A GB 2292004 A GB2292004 A GB 2292004A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conductive
- circuit
- substrate
- electronic circuit
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
Abstract
An electronic circuit package comprises a carrier substrate 20 e.g. in the form of a flexible circuit, having a plurality of electrical contacts 40 - 45 defined thereon, an integrated circuit device 10 mounted on the substrate including a plurality of terminals 30, 32, 50 - 54 located towards the periphery of the device, the plurality of terminals being individually connected by means of conductive wires 31 to a corresponding electrical contact on the substrate. The package further comprises a conductive path means 150 acting as a conductive bridge between a selected device terminal eg 50 and an associated electrical contact on the substrate 43, the conductive path means comprising a conductive region defined in or on an outward facing surface of the device, the selected terminal eg 50 connected by a first conductive wire 180 to the conductive region 162, 166 which is in turn connected by a second conductive wire 182 to the associated electrical contact 108. The conductive region is advantageously formed in a separate circuit element e.g. a flexible circuit which is bonded onto the surface of the device. <IMAGE>
Description
ELECTRONIC CIRCUIT PACKAGE
Technical Field of the Invention
This invention relates to electronic circuit packages and particularly to the electrical interconnection of integrated circuit devices to a carrier substrate.
Backaround of the Invention
One technique for mounting unpackaged integrated circuit (IC) devices to a substrate or carrier is called direct chip attach. This attachment technique is well established for the attachment of IC devices directly to printed circuit boards and more recently it has been developed for use in attaching IC devices to flexible circuits. This latter application is known as chip-on-flex. In both applications, electrical connection between the IC device and the printed circuit on the substrate may be achieved by wirebonding connection pads on the chip to circuit lines defined on the substrate.
The wireability of circuits using wirebonded direct chip attach IC devices is becoming more and more difficult due to the increasing complexity of the device. In order to accommodate the pin-out of a particular device it is often necessary to introduce extra circuit layers and shielding layers on the substrate onto which the IC device is mounted.
The problem is exemplified in Figure 1 which shows a schematic plan view of an IC chip 10 mounted on a printed circuit carrier 20. Around the periphery of the upper surface of the chip are a plurality of terminals (or pins) which are employed to connect the semiconductor components of the chip (not shown) to circuit lines on the circuit carrier. The printed circuit carrier also includes a row of connectors 40 to which terminals 30 of the chip are to be connected. Circuit lines 80 are defined on the carrier extending from the periphery of the chip to the external connectors. The terminals 30 on the device are connected by wirebonds 31 to the circuit lines 80. Also included on the circuit carrier is a second row of connectors 42 to which terminals 32 are connected via wirebonds 31 and circuit lines 82. Circuit lines 80 and 82 are provided in a single circuit layer on the substrate.
It can be seen that the pin-out configuration of the device requires that terminal 50 and terminal 51 on the chip are connected to connector 43.
This requirement necessitates the provision, in the circuit, of contact pads 60 and 61 to which terminals 51 and 52 are respectively connected by means of wire bonds 31. Connecting contact pads 60 and 61 to connector 43 is circuit line 102 (shown in phantom) which extends around the edge of the device. In a similar manner, terminals 53 and 54 are connected to connector 44 by means of contact pads 62 and 63 on circuit line 104.
Similarly, terminal 52 is connected to connector 45 by means of contact pad 64 on circuit line 106.
It is clear from Figure 1 that provision of circuit lines 102, 104 and 106 necessitates the provision of an additional circuit layer. A shielding layer (not shown) may also be required to reduce interference between signals carried on e.g. circuit lines 80 and 102 or circuit lines 80 and 106.
It will be appreciated that for reasons of clarity, Figure 1 demonstrates only a simple example of the problem which is solved by means of a relatively simple two layer circuit pattern on the carrier. In reality, the pin-out configuration of a particular IC device may require a significantly more complex circuit pattern comprising three or more circuit layers and possibly shield layers to reduce the amount of interference between circuit lines. The reduction of interference is especially critical where for example the signals on lines 80 are extremely low in amplitude e.g. signals produced when reading magnetically recorded data from a data storage disk.
Thus it can be seen that with the increase in complexity of today's integrated circuit devices, the electrical connection of an integrated circuit device to a carrier substrate is becoming more complex and often results in the need to employ multiple circuit layers in order to achieve the required interconnection while ensuring that electrical interference between the circuit lines is kept to a minimum.
Disclosure of the Invention
The present invention seeks to address this problem and accordingly provides, in a first aspect, an electronic circuit package comprising a carrier substrate having a plurality of electrical contacts defined thereon, an integrated circuit device mounted on the substrate including a plurality of terminals located towards the periphery of the device, said plurality of terminals being individually connected by means of conductive wires to a corresponding electrical contact on the substrate, and conductive path means acting as a conductive bridge between a selected device terminal and an associated electrical contact on the substrate, said conductive path means comprising a conductive region defined in or on an outward facing surface of the device, said selected terminal connected by a first conductive wire to said conductive region, said region connected by a second conductive wire to said associated electrical contact.
Although it is possible that the conductive path means would comprise a single conductive region for bridging between a single terminal and a single electrical contact, the present invention finds especially advantageous use in bridging between multiple electrical contacts and terminals. Accordingly, a preferred circuit package comprises a plurality of conductive path means for connecting individual selected device terminals with associated electrical contacts on the substrate, said plurality of conductive path means including a plurality of conductive regions in the form of conductive lines defined in or on said substrate surface.
The present invention may be employed to connect a terminal at one edge of the device with an electrical contact adjacent the same edge of the device. However, it will be apparent that in the majority of applications, the conductive bridge is especially useful in connecting a terminal at one edge of the device to an electrical contact adjacent a second edge of the device.
In a preferred embodiment, the conductive regions are located in or on a central area of said substrate surface. In one embodiment, the conductive regions are formed into a circuit element which is attached to the substrate surface. The plurality of conductive regions may advantageously be disposed in multiple circuit layers of the circuit element.
The carrier substrate may take the form of a hard printed circuit board, or in a preferred embodiment, a flexible circuit having a printed circuit, including said electrical contacts, defined thereon.
In a second aspect of the invention there is provided an integrated circuit device having such conductive regions defined thereon which, when the device is mounted on a substrate, are connectable to selected device terminals and electrical contacts to provide a conductive bridge therebetween.
The invention has significant advantages over the prior art wiring technique. Firstly, the use of such a conductive bridge on or in said substrate allows for a reduction in the complexity of the circuitry on the circuit substrate and in particular provides a reduction in wiring density which results in the ability to more efficiently position chip interconnections with the circuit substrate in order to minimise copper conductor lengths.
A reduction in wiring density further allows for maximisation of line widths and spaces which improves manufacturing yield.
Furthermore, a simplified wiring layout leads to the potential for reducing the number of wiring levels (i.e. circuit layers) in those situations where the two dimensional layout area is restricted. This reduction in the number of circuit layers leads to a reduction in manufacturing costs of the circuit substrate.
An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings.
Brief Description of the Drawings
Figure 1 shows in schematic plan view an integrated circuit package comprising an integrated device mounted on a circuit carrier having a circuit pattern according to the prior art;
Figure 2 shows in schematic plan view an integrated circuit package according to one embodiment of the present invention.
Detailed Description of the Invention
As has been mentioned previously, for the purposes of clarity in the drawings, the schematics of Figures 1 and 2 are greatly simplified in comparison to actual electronic circuit packages. In particular it is to be noted that the total number of terminals shown on the integrated circuit device is smaller than will commonly be required on IC devices.
For example a typical device may include upwards of twenty terminals along each peripheral edge with a resultant requirement for a greatly increased number of circuit lines on the carrier substrate.
Turning to a consideration of Figure 2, there is shown an electronic circuit package in which the integrated circuit device has the same pinout configuration as that of the device in Figure 1. The carrier substrate 20 is formed from conventional flexible circuit comprising a flexible polyimide carrier to which is bonded a copper layer. The circuit pattern is defined in the copper layer by conventional techniques e.g. by etching. The flexible circuit is mounted on a metal layer e.g. of aluminum onto which the integrated circuit device is directly attached, through an aperture in the flex circuit, by means of thermally conductive adhesive. The aluminum layer acts as a heat sink for the device. As in the package of Figure 1, there is included a first row of connectors 40 and a second row of connectors including connectors 42.Connection of terminals 30 to connectors 40 is effected in the same manner as is employed in Figure 1 i.e. by means of circuit lines 80 leading from the connectors 40 towards the periphery of the device in position relative to the terminals 30 to allow wirebonding between an individual terminal and circuit line. Terminals 32 are connected to connectors 42 also in the same manner as described above in relation to Figure 1. As is known in the art, one common wirebonding technique involves aluminum or gold wires which are ultrasonically bonded to the terminal and to the circuit line on the flexible circuit. Layers of nickel and gold are placed on the circuit line to form a robust contact pad for the ultrasonic bond.
In contrast to the electronic package of Figure 1, the package of Figure 2 further includes a circuit coupon 150 comprising a flexible carrier layer e.g. of polyimide on which are defined copper pads 160 to 167. Also defined on the polyimide layer are copper connecting lines 170, 172 and 174. The coupon is bonded to the upper surface of the device by means of a suitable adhesive.
As in Figure 1, terminals 50 and 51 are required to be connected to connector 43. This connection is achieved as follows: terminal 50 is connected by wirebond 180 to pad 162. Terminal 51 is connected by wirebond 181, over the IC device, to pad 163. Pad 166 is connected by wirebond 182 to an additional circuit line 108 which extends from the periphery of the chip to connector 43.
It will be appreciated that circuit line 108 is fabricated in the same circuit layer as circuit lines 80 and 82. Thus connection of a terminal at one edge of chip to a carrier circuit connector beyond the opposite side of the chip is effected by wirebonding across the chip, in contrast to the known wiring technique as exemplified in Figure 1 in which it is necessary to take a circuit line around the edge of the chip.
Connection of terminals 53 and 54 to connector 44 is achieved in a similar manner by means of wirebond 183 to pad 160 and wirebond 184 to pad 161. Wirebond 185 is connected between pad 167 and circuit line 109 extending from the periphery of the chip to connector 44. In a similar manner, terminal 52 is connected to connector 45 by means of wirebond 186, contact pad 164, circuit line 174, pad 165, wirebond 187 and circuit line 110. As for circuit line 108, circuit lines 109 and 110 are fabricated in the same circuit layer as lines 80 and 82.
It will be readily appreciated from a comparison of the figures that the printed circuit layout of Figure 2 is greatly simplified over that of
Figure 1. Furthermore, all circuit lines are provided in a single circuit layer thus leading to a reduction in manufacturing complexity and cost.
In addition, the fact that there is no 'crossing' of circuit lines in different layers (e.g. lines 80 and line 106 in Figure 1), the scope for interference between signals on the circuit lines is much reduced.
Although the coupon of the described embodiment comprises only a single circuit layer, it will be apparent that depending on the particular pinout of the IC device and configuration of the circuit pattern it may be advantageous or necessary to employ a multi circuit layer coupon.
Furthermore although in the above described embodiment a coupon or patch is employed to provide the interconnection across the IC device, the present invention may alternatively be implemented by means of contact pads and wires introduced directly into the IC device during its construction. This alternative implementation may, in many circumstances, be the preferred implementation as it avoids the need to manufacture a separate coupon for attachment to the device. Furthermore, this alternative implementation lends itself to a further adaptation of the invention wherein, for example, terminal 50 is positioned away from the edge of the IC device towards the centre and wirebonding directly across the device from terminal 50 in its more central position to circuit line 108.
Claims (8)
1. An electronic circuit package comprising:
a carrier substrate having a plurality of electrical contacts defined thereon;
an integrated circuit device mounted on the substrate including a plurality of terminals located towards the periphery of the device, said plurality of terminals being individually connected by means of conductive wires to a corresponding electrical contact on the substrate; and
conductive path means acting as a conductive bridge between a selected device terminal and an associated electrical contact on the substrate, said conductive path means comprising a conductive region defined in or on an outward facing surface of the device, said selected terminal connected by a first conductive wire to said conductive region, said region connected by a second conductive wire to said associated electrical contact.
2. An electronic circuit package as claimed in claim 1, comprising a plurality of conductive path means for connecting individual selected device terminals with associated electrical contacts on the substrate, said plurality of conductive path means including a plurality of conductive regions in the form of conductive lines defined in or on said substrate surface.
3. An electronic circuit package as claimed in claim 2 wherein at least one of said plurality of conductive paths means acts as a conductive bridge between a device terminal located at a first edge of said device and an associated electrical contact located adjacent a second edge of said device.
4. An electronic circuit package as claimed in claim 2 or claim 3 wherein said conductive regions are located in or on a central area of said substrate surface.
5. An electronic circuit package as claimed in any of claims 2 to 4 wherein said conductive regions are formed in a circuit element which is attached to said substrate surface.
6. An electronic circuit package as claimed in any of claims 2 to 5, wherein each of said conductive regions comprises a pair of electrical wirebond contact pads interconnected by a circuit line.
7. An electronic package as claimed in any preceding claim, wherein the carrier substrate comprises a flexible circuit having a printed circuit, including said electrical contacts, defined thereon.
8. An electronic circuit package as claimed in any preceding claim, further including an encapsulant layer encapsulating said integrated circuit device and said conductive wires.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9415297A GB2292004A (en) | 1994-07-29 | 1994-07-29 | Electronic circuit package |
| AU31193/95A AU3119395A (en) | 1994-07-29 | 1995-07-27 | Electronic circuit package |
| PCT/GB1995/001785 WO1996004682A1 (en) | 1994-07-29 | 1995-07-27 | Electronic circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9415297A GB2292004A (en) | 1994-07-29 | 1994-07-29 | Electronic circuit package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9415297D0 GB9415297D0 (en) | 1994-09-21 |
| GB2292004A true GB2292004A (en) | 1996-02-07 |
Family
ID=10759059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9415297A Withdrawn GB2292004A (en) | 1994-07-29 | 1994-07-29 | Electronic circuit package |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU3119395A (en) |
| GB (1) | GB2292004A (en) |
| WO (1) | WO1996004682A1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905639A (en) * | 1997-09-29 | 1999-05-18 | Raytheon Company | Three-dimensional component stacking using high density multichip interconnect decals and three-bond daisy-chained wedge bonds |
| DE10214847A1 (en) * | 2002-04-04 | 2003-10-23 | Diehl Munitionssysteme Gmbh | Flexible thin circuit construction |
| US8716932B2 (en) | 2011-02-28 | 2014-05-06 | Apple Inc. | Displays with minimized borders |
| US8804347B2 (en) | 2011-09-09 | 2014-08-12 | Apple Inc. | Reducing the border area of a device |
| US9110320B2 (en) | 2012-08-14 | 2015-08-18 | Apple Inc. | Display with bent inactive edge regions |
| US9195108B2 (en) | 2012-08-21 | 2015-11-24 | Apple Inc. | Displays with bent signal lines |
| US9601557B2 (en) | 2012-11-16 | 2017-03-21 | Apple Inc. | Flexible display |
| US9209207B2 (en) | 2013-04-09 | 2015-12-08 | Apple Inc. | Flexible display with bent edge regions |
| US9600112B2 (en) | 2014-10-10 | 2017-03-21 | Apple Inc. | Signal trace patterns for flexible substrates |
| KR20180075733A (en) | 2016-12-26 | 2018-07-05 | 엘지디스플레이 주식회사 | Flexible display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2218847A (en) * | 1988-05-16 | 1989-11-22 | Gen Electric Co Plc | Semiconductor devices |
| EP0368741A1 (en) * | 1988-11-08 | 1990-05-16 | Bull S.A. | Integrated-circuit support and its manufacturing method, integrated circuit adapted to the support and resulting housings |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636147A (en) * | 1979-08-31 | 1981-04-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| US5016082A (en) * | 1988-09-16 | 1991-05-14 | Delco Electronics Corporation | Integrated circuit interconnect design |
| US5055907A (en) * | 1989-01-25 | 1991-10-08 | Mosaic, Inc. | Extended integration semiconductor structure with wiring layers |
| US5231305A (en) * | 1990-03-19 | 1993-07-27 | Texas Instruments Incorporated | Ceramic bonding bridge |
| US5060052A (en) * | 1990-09-04 | 1991-10-22 | Motorola, Inc. | TAB bonded semiconductor device having off-chip power and ground distribution |
-
1994
- 1994-07-29 GB GB9415297A patent/GB2292004A/en not_active Withdrawn
-
1995
- 1995-07-27 WO PCT/GB1995/001785 patent/WO1996004682A1/en active Application Filing
- 1995-07-27 AU AU31193/95A patent/AU3119395A/en not_active Abandoned
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2218847A (en) * | 1988-05-16 | 1989-11-22 | Gen Electric Co Plc | Semiconductor devices |
| EP0368741A1 (en) * | 1988-11-08 | 1990-05-16 | Bull S.A. | Integrated-circuit support and its manufacturing method, integrated circuit adapted to the support and resulting housings |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1996004682A1 (en) | 1996-02-15 |
| GB9415297D0 (en) | 1994-09-21 |
| AU3119395A (en) | 1996-03-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 730 | Substitution of applicants allowed (sect. 30/1977) | ||
| 730A | Proceeding under section 30 patents act 1977 | ||
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |