GB2218847A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
GB2218847A
GB2218847A GB8811583A GB8811583A GB2218847A GB 2218847 A GB2218847 A GB 2218847A GB 8811583 A GB8811583 A GB 8811583A GB 8811583 A GB8811583 A GB 8811583A GB 2218847 A GB2218847 A GB 2218847A
Authority
GB
United Kingdom
Prior art keywords
frame
compartment
chips
chip
members
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8811583A
Other versions
GB2218847B (en
GB8811583D0 (en
Inventor
Gerald Herbert Swallow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co PLC
Original Assignee
General Electric Co PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co PLC filed Critical General Electric Co PLC
Priority to GB8811583A priority Critical patent/GB2218847B/en
Publication of GB8811583D0 publication Critical patent/GB8811583D0/en
Publication of GB2218847A publication Critical patent/GB2218847A/en
Application granted granted Critical
Publication of GB2218847B publication Critical patent/GB2218847B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor chip carrier which allows connections to points within the area of the carried chip or chips (9) instead of, or as well as, to points along the edges of the chips. The carrier comprises a frame defining a generally planar compartment for the chips and having an edge portion (13) extending around the edge of the compartment and at least one bridge portion (15) extending across the compartment between spaced locations on the edge portion. The bridge portion carries electrical conductors (19) for effecting connection between the chip and terminals (17) carried by the frame. <IMAGE>

Description

Semiconductor Devices This invention relates to semiconductor devices.
More particularly the invention relates to semiconductor devices comprising relatively large area planar semiconductor chips.
In such a device it may be desirable to make connections to points within the area of the chip instead of, or as well as to points along edges of the chip. This requirement may arise particularly where the large area chip is in fact constituted by a number of smaller chips placed side by side in a planar array.
It is an object of the present invention to provide a semiconductor chip carrier which facilitates the provision of such connections.
According to the present invention there is provided a semiconductor chip carrier comprising a frame defining a generally planar compartment for housing a planar semiconductor chip or a plurality of chips assembled in a planar array, the frame comprising an edge portion which extends around the edge of the compartment and at least one bridge portion extending across the compartment between spaced locations on the edge portion of the frame and carrying electrical conductors for effecting connection between the chip or chips and terminals carried by the frame for external connection of the chip or chips.
In a preferred arrangement in accordance with the invention the frame and compartment defined thereby are of generally rectangular form and the or each said bridge member extends between locations on opposite sides of the compartment.
One semiconductor chip carrier in accordance with the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a bottom view of the carrier; Figure 2 is a top view of the carrier; and Figure 3 is a side view of the carrier.
The carrier is designed to hold an array of nine charge coupled device image sensor semiconductor chips, e.g. for use in converting an x-ray radiation image to a corresponding electrical signal of suitable format.
Referring to the drawings, the carrier comprises a frame 1 of ceramic material, such as alumina, which defines a shallow planar rectangular compartment. To this end the frame 1 comprises first and second planar rectangular members 3 and 5 between which are sandwiched planar spacer members 7 around the edges of the members 3, 5 to hold the members 3, 5 in parallel spaced relationship to form the compartment.
In use of the carrier the compartment houses the nine CCD image sensor chips 9 in a 3 x 3 array.
To allow radiation to impinge on a face of each chip 9 the member 3 has formed in it nine rectangular apertures 11, one for each chip 9.
The member 5 comprises an edge portion 13 which extends around the edge of the compartment and hence around the edge of the array of chips 9 housed in the compartment. The member 5 further includes three bridge portions 15 which extend between the narrower sides of the edge portion 13 of the member 5, the bridge portions 15 being in parallel spaced relation with one another and the longer sides of the edge portion 13.
Along the outer edges of each of the shorter sides of the edge portion 13 there are carried leads 17 for making external connections to the chips 9. Connections between the leads 17 and the chips 9 are provided by way of conductors 19 in the form of metallised coatings carried on the outer surface of the member 5, and extending along the bridge portions 15. Each bridge portion 15 extends centrally along a different line of three of the chips 9 and carries conductors 19 for making connection to either of the longer pair of opposite sides of each chip 9 in the line of three chips 9 along which it extends.
Connection between the conductors 19 on the member 5 and the chips 9 is effected in known manner by welding flying leads (not shown) between the conductors 19 and tabs (not shown) on the chips 9.
Whilst the chip carrier described above by way of example has bridge portions carrying conductors on one side only of the chips 9, in other carriers according to the invention such bridge portions may be provided on both sides of the chip or chips.
It will be understood that whilst the chip carrier described above by way of example has a rectangular form, other carriers according to the invention may have a different geometry.
Furthermore whilst the chip carrier described above by way of example carries an array of chips, other carriers in accordance with the invention may be designed to carry a single chip.

Claims (7)

1. A semiconductor chip carrier comprising a frame defining a generally planar compartment for housing a planar semiconductor chip or a plurality of chips assembled in a planar array, the frame comprising an edge portion which extends around the edge of the compartment and at least one bridge portion extending across the compartment between spaced locations on the edge portion of the frame and carrying electrical conductors for effecting connection between the chip or chips and terminals carried by the frame for external connection of the chip or chips.
2. A carrier according to Claim 1 wherein the frame and the compartment defined thereby are of generally rectangular form and the or each said bridge member extends between locations on opposite sides of the compartment.
3. A carrier according to Claim 2 wherein the or each bridge portion extends in a parallel spaced relation with a pair of opposite sides of said frame portion.
4. A carrier according to any one of the preceding claims wherein said frame comprises first and second planar members held in parallel spaced relationship by one or more spacer members sandwiched between said first and second members around the edges of said first and second members, the or each said bridge portion constituting part of one or other of said first and second members.
5. A carrier according to any one of the preceding claims wherein said frame consists of a ceramic material.
6. A carrier according to Claim 5 wherein said ceramic material is alumina.
7. A semiconductor chip carrier substantially as hereinbefore described with reference to the accompanying drawing.
GB8811583A 1988-05-16 1988-05-16 Carrier for semiconductor devices Expired - Fee Related GB2218847B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8811583A GB2218847B (en) 1988-05-16 1988-05-16 Carrier for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8811583A GB2218847B (en) 1988-05-16 1988-05-16 Carrier for semiconductor devices

Publications (3)

Publication Number Publication Date
GB8811583D0 GB8811583D0 (en) 1988-06-22
GB2218847A true GB2218847A (en) 1989-11-22
GB2218847B GB2218847B (en) 1991-04-24

Family

ID=10636985

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8811583A Expired - Fee Related GB2218847B (en) 1988-05-16 1988-05-16 Carrier for semiconductor devices

Country Status (1)

Country Link
GB (1) GB2218847B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0413451A2 (en) * 1989-08-14 1991-02-20 STMicroelectronics Limited Packaging semiconductor chips
GB2292004A (en) * 1994-07-29 1996-02-07 Ibm Uk Electronic circuit package
US6683373B1 (en) * 1999-08-02 2004-01-27 Alcatel Method of modifying connecting leads and thinning bases of encapsulated modular electronic components to obtain a high-density module, and a module obtained thereby

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1303350A (en) * 1971-05-24 1973-01-17
GB1553559A (en) * 1977-05-02 1979-09-26 Philips Nv Hybrid circuits

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH518005A (en) * 1970-01-21 1972-01-15 Siemens Ag Electrical connection element for connecting a microelectronic circuit with external wiring

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1303350A (en) * 1971-05-24 1973-01-17
GB1553559A (en) * 1977-05-02 1979-09-26 Philips Nv Hybrid circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0413451A2 (en) * 1989-08-14 1991-02-20 STMicroelectronics Limited Packaging semiconductor chips
EP0413451A3 (en) * 1989-08-14 1991-09-04 Inmos Limited Packaging semiconductor chips
GB2292004A (en) * 1994-07-29 1996-02-07 Ibm Uk Electronic circuit package
US6683373B1 (en) * 1999-08-02 2004-01-27 Alcatel Method of modifying connecting leads and thinning bases of encapsulated modular electronic components to obtain a high-density module, and a module obtained thereby

Also Published As

Publication number Publication date
GB2218847B (en) 1991-04-24
GB8811583D0 (en) 1988-06-22

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930516