AU3119395A - Electronic circuit package - Google Patents
Electronic circuit packageInfo
- Publication number
- AU3119395A AU3119395A AU31193/95A AU3119395A AU3119395A AU 3119395 A AU3119395 A AU 3119395A AU 31193/95 A AU31193/95 A AU 31193/95A AU 3119395 A AU3119395 A AU 3119395A AU 3119395 A AU3119395 A AU 3119395A
- Authority
- AU
- Australia
- Prior art keywords
- electronic circuit
- circuit package
- package
- electronic
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9415297 | 1994-07-29 | ||
GB9415297A GB2292004A (en) | 1994-07-29 | 1994-07-29 | Electronic circuit package |
PCT/GB1995/001785 WO1996004682A1 (en) | 1994-07-29 | 1995-07-27 | Electronic circuit package |
Publications (1)
Publication Number | Publication Date |
---|---|
AU3119395A true AU3119395A (en) | 1996-03-04 |
Family
ID=10759059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU31193/95A Abandoned AU3119395A (en) | 1994-07-29 | 1995-07-27 | Electronic circuit package |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU3119395A (en) |
GB (1) | GB2292004A (en) |
WO (1) | WO1996004682A1 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5905639A (en) * | 1997-09-29 | 1999-05-18 | Raytheon Company | Three-dimensional component stacking using high density multichip interconnect decals and three-bond daisy-chained wedge bonds |
DE10214847A1 (en) * | 2002-04-04 | 2003-10-23 | Diehl Munitionssysteme Gmbh | Flexible thin circuit construction |
US8716932B2 (en) | 2011-02-28 | 2014-05-06 | Apple Inc. | Displays with minimized borders |
US8804347B2 (en) | 2011-09-09 | 2014-08-12 | Apple Inc. | Reducing the border area of a device |
US9110320B2 (en) | 2012-08-14 | 2015-08-18 | Apple Inc. | Display with bent inactive edge regions |
US9195108B2 (en) | 2012-08-21 | 2015-11-24 | Apple Inc. | Displays with bent signal lines |
US9601557B2 (en) | 2012-11-16 | 2017-03-21 | Apple Inc. | Flexible display |
US9209207B2 (en) | 2013-04-09 | 2015-12-08 | Apple Inc. | Flexible display with bent edge regions |
US9600112B2 (en) | 2014-10-10 | 2017-03-21 | Apple Inc. | Signal trace patterns for flexible substrates |
KR20180075733A (en) | 2016-12-26 | 2018-07-05 | 엘지디스플레이 주식회사 | Flexible display device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5636147A (en) * | 1979-08-31 | 1981-04-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
GB2218847B (en) * | 1988-05-16 | 1991-04-24 | Gen Electric Co Plc | Carrier for semiconductor devices |
US5016082A (en) * | 1988-09-16 | 1991-05-14 | Delco Electronics Corporation | Integrated circuit interconnect design |
FR2638895A1 (en) * | 1988-11-08 | 1990-05-11 | Bull Sa | INTEGRATED CIRCUIT SUPPORT AND MANUFACTURING METHOD THEREOF, INTEGRATED CIRCUIT SUITABLE FOR THE SUPPORT AND RESULTING HOUSING |
US5055907A (en) * | 1989-01-25 | 1991-10-08 | Mosaic, Inc. | Extended integration semiconductor structure with wiring layers |
US5231305A (en) * | 1990-03-19 | 1993-07-27 | Texas Instruments Incorporated | Ceramic bonding bridge |
US5060052A (en) * | 1990-09-04 | 1991-10-22 | Motorola, Inc. | TAB bonded semiconductor device having off-chip power and ground distribution |
-
1994
- 1994-07-29 GB GB9415297A patent/GB2292004A/en not_active Withdrawn
-
1995
- 1995-07-27 AU AU31193/95A patent/AU3119395A/en not_active Abandoned
- 1995-07-27 WO PCT/GB1995/001785 patent/WO1996004682A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO1996004682A1 (en) | 1996-02-15 |
GB2292004A (en) | 1996-02-07 |
GB9415297D0 (en) | 1994-09-21 |
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