JPH04144145A - Packaging of semiconductor device - Google Patents
Packaging of semiconductor deviceInfo
- Publication number
- JPH04144145A JPH04144145A JP2267675A JP26767590A JPH04144145A JP H04144145 A JPH04144145 A JP H04144145A JP 2267675 A JP2267675 A JP 2267675A JP 26767590 A JP26767590 A JP 26767590A JP H04144145 A JPH04144145 A JP H04144145A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- conductive
- circuit board
- electrode
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000011231 conductive filler Substances 0.000 claims abstract description 14
- 229910000510 noble metal Inorganic materials 0.000 claims abstract description 6
- 229910052709 silver Inorganic materials 0.000 claims abstract description 6
- 239000004332 silver Substances 0.000 claims abstract description 6
- 239000010953 base metal Substances 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims abstract description 5
- 239000000853 adhesive Substances 0.000 claims description 20
- 230000001070 adhesive effect Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 239000000843 powder Substances 0.000 abstract description 17
- 239000007767 bonding agent Substances 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 6
- 239000000945 filler Substances 0.000 description 5
- 238000005987 sulfurization reaction Methods 0.000 description 4
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- 238000003113 dilution method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は 半導体装置と回路基板上の端子電極部との電
気的接続に関するものであり、特番ζ 導電性接着剤を
用いたフェースダウンボンディング法に係る半導体装置
の実装方法に関するものであも
従来の技術
従来 電子部品の接続端子と回路基板上の回路パターン
端子との接続には半田付けがよく利用されていた力文
近瓢 例えばＩＣフラットパッケージ等の小型化と、接
続端子の増加により、接続端子連 いわゆるピッチ間隔
が次第に狭くなり、従来の半田付は技術で対処すること
が次第に困難になって来島
そこで、最近では裸の半導体装置を０回路基板上の端子
電極部に直付けして実装面積の効率的使用を図ろうとす
る方法が考案されてきた なかでＬ特願平１−２３２７
３５号公報に示されているように金属ワイヤを用いて入
出力電極上に電気的接続接点を構成し 電気的接続接点
と回路基板上の導体端子部との間に導電性接着剤を設け
て接合することにより電気的接続を得ようとする方法が
提案されていも
発明が解決しようとする課題
しかしながら上記のような方法で（Ｌ 第４図に示すご
とく、半導体チップ３と回路基板６の端子電極部５の電
気的接続は チップに形成された突起バンブ電極３を介
して導電性接着剤で行われているので、導電性接着剤１
００の導電フィラ１０１がＡｇフィラの場合には 第４
図の様にＡｇフィラ表面が酸化 硫化やヨウ化した部分
７が形成され接続抵抗値が増大すム また 微小間隔に
電界を加える所に用いた場合には 高温高湿下において
第５図の様にマイグレーション８（Ａｇの移行）が発生
して信頼性が低下する等の問題があム上記の問題を解決
するためＡｇ−Ｐｄ合金粉も用いられるがコストが高く
なってしまう等の問題点を有してい九
本発明は上記の問題点を鑑みてなされたものであり、そ
の目的とする所（よ 微細で密に構成されている半導体
チップ上に構成された突起状バンプと回路基板上の導体
端子部を安定かつ信頼性よく接続しようとするものであ
も
課題を解決するための手段
上記課題を解決するために本発明の半導体装置の実装方
法（Ｌ 導電フィラとして、Ｎｉ、Ｃｕ等の卑金属表面
にＰｄ、 Ａｕ、 Ｐｔ等の銀以外の貴金属をメッ
キ等で表面コートを施した微粉を用いた導電性接着剤で
半導体チップの突起バンプと回路基板の端子電極部を電
気的に接続することを特徴とするものであも
作 用
この方法によれは 半導体チップと回路基板とは導電性
接着剤により安定に接続されるため酸化硫化やヨウ化等
に対しても安定なものとなり、微小で密に形成された電
極間においてもマイグレーションが発生せず、低コスト
で信頼性よく電気的接続されも
実施例
以下、本発明の一実施例の半導体装置の実装方法につい
て、図面を参照しながら説明する。第３図は本発明の一
実施例における半導体装置の実装方法による接続部の拡
大図であり、第２図ζ友 本発明の一実施例における半
導体の実装方法の概略説明図であり、第１図は 本発明
の一実施例における導電性接着剤の概略構成図であム
第１図 第２図および第３図において、 ■は半導体装
置であり、 ２は電極パッド部である。３はバンブ電極
であり、 １０はＮ１粉にＰｄを５％コートシた導電粉
を導電フィラとする導電性接着剤であ翫 ５は端子電極
部であり、 ６は回路基板であ４ １１は重金［１２は
貴金入 １３はバインダーであム
以上のように構成された半導体装置の実装方法について
、以下図面を用いて説明すも
まず、半導体装置１の電極パッド部２上にあらかじめメ
ッキ等によりバンブ電極３を形成しておき、このバンブ
電極３に転写や印刷によってＮｉにＰｄを５％コートし
た導電粉を導電フィラとする導電性接着剤１０を形成す
も
その黴 この半導体装置１をフェースダウンで回路基板
６の端子電極部５に位置合せを行（＼ 回路基板６上に
半導体装置１をマウントした後、加熱により導電性接着
剤４を硬化させることによって、第２図および第３図に
示す様に 半導体装置１がバンブ電極およびＮ１にＰｄ
をコートした導電粉を導電フィラとする導電性接着剤１
０を介して回路基板６の端子電極５に電気的に接続され
もこのとき、表に示すように導電性接着剤４の導電フィ
ラとしてＮ１にＰｄを５％コートした導電粉を用いるた
ム 熱的にも安定であり、経時変化もなく、従来のＡｇ
フィラに見られるような酸化硫化やヨウ化等による劣化
がない。[Detailed Description of the Invention] Industrial Application Field The present invention relates to an electrical connection between a semiconductor device and a terminal electrode portion on a circuit board, and relates to a face-down bonding method using a special number ζ conductive adhesive. Related to the mounting method of semiconductor devices, conventional technology is a mechanical technique in which soldering was often used to connect the connection terminals of electronic components and the circuit pattern terminals on the circuit board.
For example, due to the miniaturization of IC flat packages and the increase in the number of connection terminals, the so-called pitch distance between the connection terminals has gradually become narrower, and it has become increasingly difficult to handle conventional soldering with technology. A method has been devised to try to use the mounting area efficiently by directly attaching a bare semiconductor device to the terminal electrode section on a circuit board.
As shown in Publication No. 35, electrical connection contacts are formed on the input/output electrodes using metal wires, and a conductive adhesive is provided between the electrical connection contacts and the conductor terminals on the circuit board. Even if a method of obtaining electrical connection by bonding has been proposed, the problem to be solved by the invention is, however, as shown in FIG. Since the electrical connection of the electrode part 5 is made with a conductive adhesive via the protruding bump electrode 3 formed on the chip, the conductive adhesive 1
When the conductive filler 101 of 00 is an Ag filler, the fourth
As shown in the figure, oxidized, sulfurized and iodized parts 7 are formed on the surface of the Ag filler, increasing the connection resistance value.Also, when used in a place where an electric field is applied at minute intervals, under high temperature and high humidity conditions, as shown in Figure 5. In order to solve the above problem, Ag-Pd alloy powder is also used, but it has problems such as increased cost. The present invention has been made in view of the above-mentioned problems, and its purpose is to solve the problems described above. Means for Solving the Problems In order to solve the above problems, the semiconductor device mounting method of the present invention (L) is intended to connect conductor terminal portions stably and reliably. The bumps on the semiconductor chip and the terminal electrodes on the circuit board are electrically connected using a conductive adhesive using a fine powder whose base metal surface is coated with a noble metal other than silver such as Pd, Au, or Pt by plating or the like. This method is characterized by the fact that the semiconductor chip and the circuit board are stably connected by the conductive adhesive, so it is stable against oxidation, sulfurization, iodization, etc. In the following, a method for mounting a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Fig. 3 is an enlarged view of a connection part according to a semiconductor device mounting method according to an embodiment of the present invention, and Fig. 2 is a schematic explanatory diagram of a semiconductor mounting method according to an embodiment of the present invention. , FIG. 1 is a schematic diagram of a conductive adhesive according to an embodiment of the present invention. In FIG. 1, FIG. 2, and FIG. 3, 2 is a semiconductor device, and 2 is an electrode pad portion. 3 is a bump electrode, 10 is a conductive adhesive whose conductive filler is conductive powder made of N1 powder coated with 5% Pd, 5 is a terminal electrode, 6 is a circuit board, 4 and 11 is a heavy metal. [12 is a precious metal. 13 is a binder. The mounting method of the semiconductor device configured as above will be explained below with reference to the drawings. A bump electrode 3 is formed in advance, and a conductive adhesive 10 is formed on the bump electrode 3 by transfer or printing using a conductive powder made of Ni coated with 5% Pd as a conductive filler. After the semiconductor device 1 is mounted on the circuit board 6, the conductive adhesive 4 is cured by heating to align it with the terminal electrode part 5 of the circuit board 6. As shown in , the semiconductor device 1 has Pd on the bump electrode and N1.
Conductive adhesive 1 whose conductive filler is conductive powder coated with
At this time, as shown in the table, a conductive powder made of N1 coated with 5% Pd was used as the conductive filler of the conductive adhesive 4. It is stable and does not change over time, compared to conventional Ag.
There is no deterioration due to oxidation, sulfurization, iodization, etc. that occurs with fillers.
また 微小間隔に電界を加える所にＡｇフィラからなる
導電性接着剤を用いた場合には 高温高湿下においてマ
イグレーションが発生して信頼性が低下する力叉 本発
明において１ｔＮｉにＰｄをコートした導電粉を導電フ
ィラとして用いるためイオン化することもなく安定であ
も
上記の酸化 硫化やヨウ化等による劣化やマイグレーシ
ョンを抑制するた？ｌｘＡｇ−Ｐｄ合金粉等も用いられ
るが約８０万円／ ｋ ｇとコストが高くなってしまう
。本発明のＮｉにＰｄをコートした導電粉ではＡｇの導
電粉と同等の約５万円／ｋｇ程度であム
以上のようにして、半導体装置１と回路基板６を極めて
安定で信頼性よく、高密度にかス 低コストで実装する
ことが可能となる。In addition, when a conductive adhesive made of Ag filler is used in a place where an electric field is applied at minute intervals, migration occurs under high temperature and high humidity, reducing reliability. Since the powder is used as a conductive filler, it is stable without ionization, but it also suppresses the deterioration and migration caused by oxidation, sulfurization, iodization, etc. mentioned above. lxAg-Pd alloy powder etc. can also be used, but the cost is high at about 800,000 yen/kg. The conductive powder of the present invention, which is Ni coated with Pd, costs about 50,000 yen/kg, which is the same as that of Ag conductive powder. It enables high-density, low-cost implementation.
な耘 導電性接着剤４の導電フィラとして（よＮｉにＰ
ｄをコートした導電粉に限られたものでなく、Ｎｉ、Ｃ
ｕ等の卑金属表面にＰｄ、Ａｕ。As a conductive filler for conductive adhesive 4 (Ni to P)
Not limited to conductive powder coated with d, but also Ni, C
Pd and Au on the surface of base metals such as u.
Ｐｔ等の銀以外の貴金属をメッキ等で表面コートを施し
た導電フィラを用いることができもまた 本実施例にお
いて導電性接着剤１０をバンプ電極３上に形成するとし
た力（導電性接着剤１０を回路基板６上の端子電極部５
側に印刷や転写法
以下余白
表
導電性接着剤の特性比較
本ガス希釈法
１００Ｈｒ後
本章
６０℃
９５％
０Ｖ
キ゛ヤフ７°０．２ｍｍ
１０００Ｈｒ後
などを用いて形成してもよい。It is also possible to use a conductive filler whose surface is coated with a noble metal other than silver such as Pt by plating or the like. The terminal electrode section 5 on the circuit board 6
It may also be formed by printing on the side or using a transfer method, margin surface, comparison of characteristics of conductive adhesive, gas dilution method, after 100 hours, 60°C, 95% 0V, cover 7°, 0.2 mm, after 1000 hours, etc.
発明の効果
以上に説明したように
本発明の半導体装置の
実装方法によりは 導電フィラとして卑金属表面に銀以
外の貴金属をコートした導電粉を用いた導電性接着剤に
よって半導体装置の電極パッド部上に形成したバンブ電
極と回路基板上の端子電極とを接着によって電気的な接
続を行うた敢 経時変化のない極めて安定な接続ができ
、微細ピッチでの接続においても信頼性の高い接続が実
現できるた数 極めて実用上価値の高いものであもEffects of the Invention As explained above, according to the method for mounting a semiconductor device of the present invention, a conductive adhesive using a conductive powder whose base metal surface is coated with a noble metal other than silver as a conductive filler is used to attach the semiconductor device to the electrode pad portion of the semiconductor device. By making an electrical connection between the formed bump electrode and the terminal electrode on the circuit board by adhesion, an extremely stable connection that does not change over time can be achieved, and a highly reliable connection can be achieved even at fine pitch connections. Number Even if it is of extremely high practical value
第１図は本発明の一実施例における導電性接着剤の概略
構成医 第２図は本発明の一実施例における半導体装置
の実装方法の概略図 第３図は本発明の一実施例におけ
る半導体装置の実装方法による接続部の拡大医 第４図
（友 酸（Ｌ 硫化等によるＡｇフィラ変化の概略図
第５図はマイグレーションの概略図である。
１−−一半導体装置 ２−一一電極バッド舐３−−−バ
ンプ電楓 １Ｏ−−−ＮｉにＰｄをコートした１粉を導
電フィラとする導電性接着剤５−−一端子電極ａ ６
−−−回路基楓 １１−一重金風
貴金属
一バイ
ン
ダー。FIG. 1 is a schematic diagram of the structure of a conductive adhesive in an embodiment of the present invention. FIG. 2 is a schematic diagram of a method for mounting a semiconductor device in an embodiment of the present invention. Fig. 4 (Schematic diagram of changes in Ag filler due to sulfurization, etc.) Fig. 5 is a schematic diagram of migration. 1--1 Semiconductor device 2-1- Electrode pad 3---Bump electric maple 1O---Conductive adhesive using 1 powder of Ni coated with Pd as conductive filler 5---One terminal electrode a 6
---Circuit base Kaede 11-Single gold-like precious metal-binder.
Claims (2)
法において、前記半導体装置の電極パッド部上にバンプ
電極を形成し、前記バンプ電極を、金属を銀以外の貴金
属で表面コートした導伝フィラを含む導電性接着剤を介
して回路基板上の端子電極部に電気的に接続することを
特徴とする半導体装置の実装方法。(1) In a method for mounting a semiconductor device on a terminal electrode portion on a circuit board, a bump electrode is formed on the electrode pad portion of the semiconductor device, and the bump electrode is formed of a conductive metal whose surface is coated with a noble metal other than silver. A method for mounting a semiconductor device, comprising electrically connecting to a terminal electrode portion on a circuit board via a conductive adhesive containing a conductive filler.
、Ｃｕ等の卑金属表面に、Ｐｄ、Ａｕ、Ｐｔ等の銀以外
の貴金属をメッキ等で表面コートを施した微粉を用いる
ことを特徴とする請求項（１）記載の半導体装置の実装
方法。(2) Ni as a conductive filler contained in the conductive adhesive
2. The method of mounting a semiconductor device according to claim 1, wherein the surface of a base metal such as , Cu or the like is coated with a noble metal other than silver such as Pd, Au or Pt by plating or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2267675A JPH04144145A (en) | 1990-10-04 | 1990-10-04 | Packaging of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2267675A JPH04144145A (en) | 1990-10-04 | 1990-10-04 | Packaging of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04144145A true JPH04144145A (en) | 1992-05-18 |
Family
ID=17447967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2267675A Pending JPH04144145A (en) | 1990-10-04 | 1990-10-04 | Packaging of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04144145A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
-
1990
- 1990-10-04 JP JP2267675A patent/JPH04144145A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
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