CN101552253A - Array package substrate - Google Patents
Array package substrate Download PDFInfo
- Publication number
- CN101552253A CN101552253A CNA2008100911150A CN200810091115A CN101552253A CN 101552253 A CN101552253 A CN 101552253A CN A2008100911150 A CNA2008100911150 A CN A2008100911150A CN 200810091115 A CN200810091115 A CN 200810091115A CN 101552253 A CN101552253 A CN 101552253A
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- array package
- base plate
- package base
- protuberance
- conduction projection
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Abstract
The invention discloses an array package substrate which comprises a patterning metal connecting layer, a plurality of connecting gaskets, a first insulation layer, a plurality of conductive projections and a second insulation layer. The patterning metal connecting layer is provided with a first surface and a second surface which corresponds to the first surface, the connecting gaskets are arranged on the first surface, the conductive projections are arranged on the second surface and are electrically connected with the connecting gaskets through the patterning metal connecting layer, wherein each conductive projection is provided with a connecting part and a projection part, and the connecting part of each conductive projection is connected with the patterning metal connecting layer. In addition, the first insulation layer is arranged at one side of the surface planar with the first surface or second surface and protrudes from the connecting gaskets. The second insulation layer is arranged at the other side of the surface and protrudes from the projection part of each conductive projection.
Description
Technical field
The present invention relates to a kind of array package base plate (array package substrate), and be particularly related to a kind of sphere grid array (ball grid array, BGA) base plate for packaging.
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and towards light, thin, short, little trend design.In semiconductor packaging process, array package base plate is one of potted element that often uses at present, and semiconductor element (for example chip) can correspondence be positioned on each array base palte.After semiconductor element and array base palte are finished electric connection, be to coat semiconductor elements all in each array base palte, to form the chip-packaging structure of array package kenel with sealing (molding compound).At last, cut each array base palte and corresponding adhesive body thereof, to form the chip packaging unit that independently separates.
From the above, in the trend of chip-packaging structure microminiaturization, semiconductor packaging also begins in the face of high pin number (high pin count), the challenge of little spacing (fine pitch), and sphere grid array (BGA) encapsulation promptly is the packaged type that is usually used in high pin number, little spacing (fine pitch) element now.What deserves to be mentioned is, using the next microminiaturized chip-packaging structure of sphere grid array (BGA) encapsulation technology, so that chip-packaging structure meets in the process of little spacing (fine pitch) design, because weld pad (bonding pad) area on the array base palte also can dwindle thereupon, therefore soldered ball (solder ball) promptly is difficult for attaching to the less weld pad surface of contact area, soldered ball promptly comes off on weld pad easily, causes the finished product rate not good.
Known another kind of technology is to utilize the increase size of solder ball to make soldered ball and weld pad that bigger contact area be arranged, to improve the problem that soldered ball comes off on weld pad.Yet chip-packaging structure increases size of solder ball and can make that the spacing of two adjacent soldered balls is too small under the situation that meets little spacing (fine pitch), and two adjacent soldered balls promptly have improper contact easily and cause the situation of short circuit to take place.Therefore, how to make chip-packaging structure under the situation that meets little spacing (fine pitch), it is an important topic that soldered ball also can effectively reach the weld pad surface that firmly adheres to microminiaturized chip-packaging structure.
Summary of the invention
The invention provides a kind of array package base plate, it meets the design of little spacing (fine pitch).
The invention provides a kind of array package base plate, it can solve the problem that soldered ball comes off easily.
The present invention proposes a kind of array package base plate, and it comprises pattern metal articulamentum (patternedmetal connecting layer), a plurality of connection pad (connecting pad), first insulating barrier (insulatinglayer), a plurality of conduction projection (conductive pillar) and second insulating barrier.The pattern metal articulamentum has first surface and one and the corresponding second surface of first surface, these connection pads are to be equipped on first surface, and these conduction projections are to be equipped on second surface, and these conduction projections electrically connect via pattern metal articulamentum and these connection pads.Wherein, each conduction projection has connecting portion and protuberance, and the connecting portion and the pattern metal articulamentum of each conduction projection join.In addition, first insulating barrier is to set and the first surface or a side on the coplanar surface of second surface, and exposes these connection pads.Second insulating barrier then is to be equipped on this surperficial opposite side, and exposes the protuberance of each conduction projection.
In one embodiment of this invention, array package base plate also comprises a plurality of and the corresponding soldered ball of these conduction projections, and these soldered balls are disposed at the protuberance of these conduction projections.
In one embodiment of this invention, array package base plate also comprises anti oxidation layer, and it covers the protuberance of each conduction projection.
In one embodiment of this invention, anti oxidation layer is nickel-gold layer, gold layer, tin layer or copper layer.
In one embodiment of this invention, the material of pattern metal articulamentum is nickel (Ni) or nickel chromium triangle (Ni-Cr).
In one embodiment of this invention, the material of these connection pads is copper (Cu).
In one embodiment of this invention, the material of these conduction projections is a copper.
Array package base plate of the present invention has the conduction projection that electrically connects with connection pad.The protuberance of each conduction projection is to expose to outside second insulating barrier, and protuberance has bigger exposed area compared to known weld pad.Therefore, when soldered ball is disposed at these conduction projections, bigger contact area is arranged promptly between soldered ball and the protuberance, soldered ball can be effectively and firmly is connected on the conduction projection.On the other hand, owing between soldered ball and the protuberance bigger contact area is arranged, therefore in the design of little spacing (fine pitch), soldered ball also still can firmly be connected on the conduction projection.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates the schematic diagram of the array package base plate of one embodiment of the invention.
Fig. 2 illustrates the schematic diagram of the array package base plate of another embodiment of the present invention.
Description of reference numerals
100,100 ': array package base plate 110: the pattern metal articulamentum
110a: first surface 120a: second surface
120: 130: the first insulating barriers of connection pad
140: conduction projection 142: connecting portion
144: 150: the second insulating barriers of protuberance
160: soldered ball 170: anti oxidation layer
S: surface
Embodiment
Fig. 1 illustrates the schematic diagram of the array package base plate of one embodiment of the invention.Please refer to Fig. 1, the array package base plate 100 of present embodiment is for example to be the semiconductor element of chip in order to carry one.Array package base plate 100 comprises that mainly a material for example is that the pattern metal articulamentum 110 (pattern metal articulamentum 110 for example is an etch barrier) of nickel or nickel chromium triangle, a plurality of material for example are that connection pad 120, first insulating barrier 130, a plurality of material of copper for example is the conduction projection 140 and second insulating barrier 150 of copper.In the present embodiment, pattern metal articulamentum 110 has first surface 110a and one and the corresponding second surface 110b of first surface 110a, these connection pads 120 are to be equipped on the first surface 110a, and these conduction projections 140 are to be equipped on the second surface 110b.Thus, these conduction projections 140 can electrically connect via pattern metal articulamentum 110 and these connection pads 120.
In addition, 130 of first insulating barriers are to be equipped on and a first surface 110a or the side of the coplanar surperficial S of second surface, and can expose these connection pads 120 (Fig. 1 illustrates first insulating barrier 130 and is equipped on a side with the coplanar surperficial S of first surface 110a).Therefore, for example be that the semiconductor element of chip can electrically connect by these connection pads 120 and array package base plate 100, to transmit electrical signal.In addition, 150 of second insulating barriers are the opposite sides that is equipped on this surperficial S, and can expose the part cylinder of each conduction projection 140.In more detail, the conduction projection 140 of present embodiment is made up of connecting portion 142 and protuberance 144.Wherein, the connecting portion 142 of each conduction projection 140 can join with pattern metal articulamentum 110, and protuberance 144 then is can be exposed to outside second insulating barrier 150.The material of above-mentioned first insulating barrier 130 and second insulating barrier 150 for example be polyimides (polyimide, PI) or other appropriate insulation materials.
What deserves to be mentioned is that because the protuberance 144 of each conduction projection 140 is to expose to outside second insulating barrier 150, and protuberance 144 has bigger exposed area compared to known weld pad.Therefore, the protuberance 144 of each conduction projection 140 promptly is suitable for joining with soldered ball effectively, and then allows soldered ball firmly be fixed on the protuberance 144.For more clearly understanding the execution mode of conduction projection 140 and soldered ball collocation, this paper will explain for another embodiment again.
Fig. 2 promptly illustrates the schematic diagram of the array package base plate of another embodiment of the present invention.The array package base plate 100 ' of present embodiment is similar with the array package base plate 100 of the foregoing description, only the two main difference is that the array package base plate 100 ' of this enforcement also comprises a plurality of and these conduction projection 140 corresponding soldered balls 160, and these soldered balls 160 promptly are the protuberances 144 that is disposed at these conduction projections 140.Wherein,, adhere to, so the soldered ball 160 of present embodiment can be effectively and firmly be connected on the conduction projection 140 for soldered ball 160 because protuberance 144 has bigger exposed area compared to known weld pad.
In addition, because present embodiment is by there being bigger contact area that soldered ball 160 firmly is attached on the conduction projection 140 between protuberance 144 and the soldered ball 160, therefore in the spacing of suitably reducing two adjacent conductive stud intercolumniations, and suitably reduce under the situation of soldered ball 160 sizes, also be difficult for causing two adjacent improper contact of soldered ball and soldered balls 160 on protuberance 144, to come off.That is present embodiment can suitably reduce the spacing of two adjacent conductive stud intercolumniations, and reduction soldered ball 160 sizes, so that array package base plate 100 ' more meets the design of little spacing (fine pitch).
Please follow simultaneously with reference to figure 1 and Fig. 2, for making array package base plate 100 (as shown in Figure 1) or 100 ' (as shown in Figure 2) that preferable oxidation resistance be arranged, meeting of the present invention covers anti oxidation layer 170 on the protuberance 144 of connection pad 120 and each conduction projection 140, to promote the oxidation resistance of array package base plate 100 and 100 '.Wherein, anti oxidation layer 170 for example is nickel-gold layer, gold layer, tin layer or copper layer
In sum, the present invention is provided with a plurality of conduction projections that electrically connect with connection pad in array package base plate, and the protuberance of each conduction projection is to expose to outside second insulating barrier.Wherein, because protuberance has bigger exposed area compared to known weld pad, for ball attach, so soldered ball can be effectively and firmly be connected on the conduction projection, and be difficult for having situation about coming off to take place.
On the other hand, because the present invention has bigger exposed area that soldered ball firmly is connected on the conduction projection by protuberance, therefore the present invention can suitably reduce two adjacent conductive stud intercolumniations, and the reduction size of solder ball, so that array package base plate more meets closely spaced design.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (7)
1. array package base plate comprises:
The pattern metal articulamentum has first surface and one and the corresponding second surface of this first surface;
A plurality of connection pads are equipped on this first surface;
First insulating barrier is equipped on and this first surface or a side on this coplanar surface of second surface, and exposes this connection pad;
A plurality of conduction projections, be equipped on this second surface, and should electrically connect via this pattern metal articulamentum and this connection pad by the conduction projection, wherein respectively this conduction projection has connecting portion and protuberance, and respectively this connecting portion of this conduction projection and this pattern metal articulamentum join; And
Second insulating barrier is equipped on this surperficial opposite side, and exposes respectively this protuberance of this conduction projection.
2. array package base plate as claimed in claim 1 also comprises a plurality of and the corresponding soldered ball of this conduction projection, and this soldered ball is disposed at this protuberance of this conduction projection.
3. array package base plate as claimed in claim 1 also comprises anti oxidation layer, and it covers this protuberance that respectively is somebody's turn to do the conduction projection.
4. array package base plate as claimed in claim 3, wherein this anti oxidation layer is nickel-gold layer, gold layer, tin layer or copper layer.
5. array package base plate as claimed in claim 1, wherein the material of this pattern metal articulamentum is nickel or nickel chromium triangle.
6. array package base plate as claimed in claim 1, wherein the material of this connection pad is a copper.
7. array package base plate as claimed in claim 1, wherein the material of this conduction projection is a copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100911150A CN101552253B (en) | 2008-04-02 | 2008-04-02 | Array package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100911150A CN101552253B (en) | 2008-04-02 | 2008-04-02 | Array package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101552253A true CN101552253A (en) | 2009-10-07 |
| CN101552253B CN101552253B (en) | 2011-05-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100911150A Expired - Fee Related CN101552253B (en) | 2008-04-02 | 2008-04-02 | Array package substrate |
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| Country | Link |
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| CN (1) | CN101552253B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915978A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
| CN102915981A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor device and packaging method thereof |
| US9293338B2 (en) | 2012-11-08 | 2016-03-22 | Nantong Fujitsu Microelectronics Co., Ltd. | Semiconductor packaging structure and method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100576476C (en) * | 2005-11-25 | 2009-12-30 | 全懋精密科技股份有限公司 | Chip buried in semiconductor encapsulation base plate structure and method for making thereof |
| CN100390983C (en) * | 2006-03-30 | 2008-05-28 | 威盛电子股份有限公司 | Chip packing-body |
-
2008
- 2008-04-02 CN CN2008100911150A patent/CN101552253B/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915978A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
| CN102915981A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor device and packaging method thereof |
| CN102915981B (en) * | 2012-11-08 | 2016-02-03 | 南通富士通微电子股份有限公司 | Semiconductor device and method for packing thereof |
| US9293338B2 (en) | 2012-11-08 | 2016-03-22 | Nantong Fujitsu Microelectronics Co., Ltd. | Semiconductor packaging structure and method |
| US9431325B2 (en) | 2012-11-08 | 2016-08-30 | Nantong Fujitsu Microelectronics Co., Ltd. | Semiconductor packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101552253B (en) | 2011-05-04 |
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