JP2002190544A - Wiring board, semiconductor device, and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the thickness of a semiconductor device wherein semiconductor chips are mounted on a wiring board. SOLUTION: The wiring board has wirings and the external connection terminals thereof, which are provided on the first principal surface of its insulation base material; via holes, pierced in its insulation base material which are provided in the prescribed places of the wirings; conductive members filled into the via holes; and plating layers provided on the surfaces of the conductive members and on the surfaces of the external connection terminals. In the wiring board, the thickness of the portion of each conductive member, which is present in the central portion of each via hole, is made larger than the one which is present in the sidewall portion of each via hole, and each conductive member, is protruded from the second principal surface of the insulation base material which faces opposite the first principal surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, a semiconductor device and a method of manufacturing the same, and more particularly, to an LGA (Land Grind).
d Array) -type semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device having a semiconductor chip mounted on a wiring board, a ball grid array (BGA) in which a ball-shaped terminal is connected to an external connection terminal provided on the wiring board and connected to an external device. ) Type semiconductor devices.

In the BGA type semiconductor device, FIG.
As shown in (a) and FIG. 11 (b), for example, a first main surface (front surface) of an insulating substrate 1 such as a polyimide tape
A wiring board provided with wiring 201 and its external connection terminals 202 is provided, and the semiconductor chip 5 is opposed to the surface of the wiring board (insulating substrate 1) on which the wiring 201 is formed, for example, the external electrodes 501 thereof are opposed to each other. The wiring 201 of the wiring board and the external electrode 501 of the semiconductor chip 5
Are connected by the projection conductor 9. Here, FIG. 11B is a cross-sectional view taken along line BB ′ of FIG. Further, in the semiconductor device, the space between the wiring board (insulating base material 1) and the semiconductor chip 5 is underfill-sealed with a sealing insulator 6 such as an epoxy-based thermosetting resin. . Further, a via hole 101 is provided at a predetermined position of the insulating base material 1, for example, at a portion where the external connection terminal 202 is provided, and a through-hole plating 203 provided along the via hole 101, or The conductive member filled in the via hole 101 is drawn out to the second main surface opposite to the first main surface. In the via hole 101, for example,
When a ball terminal 10 such as a solder ball is connected, B
It becomes a GA type semiconductor device.

[0004] The method of manufacturing the BGA type semiconductor device will be briefly described. First, a conductive thin film such as copper is formed on an insulating substrate 1 such as a polyimide tape, and a predetermined film of the insulating substrate 1 is formed. After a via hole 101 is formed at a position with a laser or the like, the conductive thin film is etched to prepare a wiring board having a predetermined pattern of wiring 201 and external connection terminals 202 formed thereon. At this time, if necessary, a through-hole plating 203 is formed in the via hole 101 or a conductive member is filled in the via hole 101. In addition, the wiring board is not limited to the above-described procedure. For example, an adhesive layer is formed on one main surface of the insulating base material 1 and a predetermined position of the insulating base material and the adhesive layer is formed by punching with a mold. Via hole 101
Is formed, a conductive thin film such as a copper foil is adhered by the adhesive layer, and the conductive thin film is etched to form a wiring 20.
1 and the external connection terminal 202 may be formed.

Next, the surface of the wiring board formed according to the above procedure, on which the wiring 201 is formed, and the circuit forming surface of the semiconductor chip 5, in other words, the surface on which the external electrodes 501 are formed, face each other. And the external electrode 501 of the semiconductor chip 5 are flip-chip bonded. When the flip-chip bonding is performed, a projecting conductor 9 such as a gold bump or a solder bump is formed on the external electrode 501 of the semiconductor chip or the connection portion of the wiring 201.

Next, the space between the wiring board (insulating substrate 1) and the semiconductor chip 5 is underfill-sealed with a sealing insulator 6 such as an epoxy-based thermosetting resin.
At this time, the sealing insulator 6 is applied to the side surface of the semiconductor chip 5 and flows between the wiring substrate (insulating base material 1) and the semiconductor chip 5 by a capillary phenomenon.

Next, the via hole 101 of the insulating substrate 1 is formed.
For example, by connecting a ball terminal 10 made of a Pb-Sn-based solder and cutting the insulating base material 1 at a predetermined position, as shown in FIG. 11A and FIG.
A GA type semiconductor device is obtained.

[0008]

However, in the prior art, as shown in FIG. 12, the ball terminals 10 of the BGA type semiconductor device are connected to the wiring 801 of a mounting substrate 8 such as a motherboard. Then, the height t from the mounting surface 8A of the mounting substrate 8 to the upper surface 5A of the semiconductor chip 5 of the semiconductor device is equal to the height t ′ of the ball terminal 10.
It will be higher by the amount of. Therefore, there is a problem that a storage container (housing) for storing the mounting board on which the BGA type semiconductor device is mounted becomes thick, and it is difficult to reduce the size.

In addition, when the semiconductor chip is flip-chip bonded to the wiring board, the projection conductor 9 is provided on the external electrode 501 of the semiconductor chip or the wiring 201 on the wiring board. Sometimes, the distance (stand-off) from the wiring board to the circuit formation surface of the semiconductor chip is increased, resulting in a problem that the semiconductor device becomes thicker.

As one of the methods for preventing the semiconductor device from being thickened by connecting the ball terminals 10 as in the BGA type semiconductor device, the ball terminals 1 are connected to each other.
Instead of 0, there is an LGA (Land Grid Array) type semiconductor device provided with planar external connection terminals (lands) on the insulating base material 1. As shown in FIG. 13, the LGA type semiconductor device has a wiring 201 on one main surface of an insulating substrate 1.
Are formed, and external connection terminals (lands) 202 are formed on the surface of the insulating base material 1 opposite to the surface on which the wiring is formed.
At this time, the wiring 201 and the land 202 are connected by a through-hole plating 203 formed along the via hole 101 provided in the insulating base material 1. The outer periphery of the land 202 is covered with a protective film 7 such as a solder resist, and the solder paste 11 or the like is applied to an exposed surface of the land 202 or a predetermined position of the wiring 801 on the mounting board 8. And implement it.

In the case of such an LGA type semiconductor device,
Since there is no ball terminal 10 as in the BGA type semiconductor device, the height from the mounting surface 8A when mounted on the mounting substrate 8 can be reduced. In order to form an external connection terminal (land) 202 on the surface opposite to the wiring forming surface of the insulating substrate 1, a tape material (a double-sided material) having a conductive thin film such as a copper foil provided on both surfaces of the insulating substrate 1 Tape material with copper foil). Therefore, there is a problem that the material cost is increased and the number of manufacturing steps is increased, so that the manufacturing cost of the wiring board and the semiconductor device is increased.

An object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device having a semiconductor chip mounted on a wiring board.

Another object of the present invention is to provide a technique capable of reducing the height from the mounting substrate to the upper surface of the semiconductor device when the semiconductor device having the semiconductor chip mounted on the wiring substrate is mounted on the mounting substrate. To provide.

Another object of the present invention is to provide a technique capable of simplifying a manufacturing process of a wiring board used for an LGA type semiconductor device and reducing a manufacturing cost.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

The summary of the invention disclosed in the present invention is as follows.

(1) Wiring and its external connection terminals are provided on the first main surface of the insulating base material, via holes are provided in the insulating base material at predetermined positions of the wiring, and conductive holes are provided in the via holes. In a wiring board in which a conductive member is filled and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal,
In the conductive member, a thickness of a center portion of the via hole is greater than a thickness of a side wall portion of the via hole, and a first portion of the insulating base material is provided.
The wiring substrate protrudes from the second main surface facing the main surface.

According to the means (1), a via hole is provided at a predetermined position of the insulating base material, and a conductive member is filled in the via hole so as to protrude from the insulating base material. Wiring provided on the first main surface side of the insulating base material is drawn out to the second main surface side, and the conductive member is connected to an external electrode of a semiconductor chip and a conductor (bump) for electrically connecting the wiring. Can be used as Therefore, a wiring substrate used for an LGA type semiconductor device can be obtained by using a tape material in which a conductive thin film is provided only on one main surface side of the insulating base material.

(2) Wirings and their external connection terminals are provided on the first main surface of the insulating base material, via holes are provided in the insulating base material at predetermined positions of the wirings, and conductive holes are provided in the via holes. In a wiring board in which a conductive member is filled and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal,
The conductive member is a wiring board in which a thickness of a central portion of the via hole is smaller than a thickness of a side wall portion of the via hole.

According to the means of the above (2), similarly to the means of the above (1), the LGA type is formed by using a tape material provided with a conductive thin film only on one main surface side of the insulating base material. The wiring board used for the semiconductor device described above can be obtained. Further, by forming the conductive member provided in the via hole into a concave shape, the wiring on the wiring board and the external electrode of the semiconductor device are connected by a projecting conductor such as a solder bump.
Since a part of the projecting conductor is sucked into the via hole, the height from the wiring board to the semiconductor chip can be reduced.

In the means of (1) and (2), an insulating layer is provided on the entire surface of the wiring and on the outer peripheral portion of the external connection terminal. By providing a plating layer of a tin alloy such as a tin-silver (Sn-Ag) alloy, a tin-bismuth (Sn-Bi) alloy, or a tin-copper (Sn-Cu) alloy, the plating layer is provided on the surface of the external electrode of the semiconductor chip. Bondability with the gold to be obtained is improved.
Further, by selecting an alloy containing no lead as the tin alloy, the burden on the environment can be reduced. Further, the plating layer is not limited to the tin alloy, and the plating layer may include gold (Au), palladium (Pd), silver (Ag),
Any one of rhodium (Rh) or an alloy containing at least one of them may be used. Said gold,
Since noble metal plating such as palladium, silver, and rhodium is not easily oxidized, it is difficult to form an oxide film on its surface, and it is possible to prevent a decrease in reliability of connection between the semiconductor chip and external electrodes.

(3) Wiring and its external connection terminals are provided on the first main surface of the insulating base material, and via holes are provided in the insulating base material at positions overlapping the external electrodes of the semiconductor chip in a plane. In a wiring board in which a conductive member is filled in the via hole and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal, a semiconductor chip has an external electrode and the conductive member. A semiconductor device mounted so as to face each other, wherein the conductive member and an external electrode of the semiconductor chip are electrically connected, and a connection portion between the semiconductor chip and the conductive member and the external electrode is sealed with a sealing insulator; It is.

According to the means (3), a via hole is formed in a portion of the insulating base material that overlaps with the external electrode of the semiconductor chip, and a projecting conductor is provided in the via hole. By connecting the electrode and the protruding conductor, the wiring and the external connection terminal of the insulating base can be provided on the surface facing the surface on which the semiconductor chip is mounted. Therefore, an LGA type semiconductor device can be obtained using a wiring board manufactured using a tape material provided with a conductive thin film only on one main surface side of the insulating base material.

(4) Wiring and its external connection terminals are provided on the first main surface of the insulating base material, via holes are provided in the insulating base material at predetermined positions of the wiring, and conductive holes are provided in the via holes. A semiconductor chip is mounted on a wiring board in which a conductive member is filled and a plating layer is provided on the surface of the conductive member and the surface of the external connection terminal so that the external electrode and the conductive member face each other, In a semiconductor device in which a conductive member and an external electrode of a semiconductor chip are electrically connected, and the semiconductor chip, and a connection portion between the conductive member and the external electrode are sealed with a sealing insulator, the conductive member includes: A semiconductor device in which a thickness of a central portion of the via hole is smaller than a thickness of a side wall portion of the via hole, and the conductive member and an external electrode of a semiconductor chip are electrically connected by a projecting conductor.

According to the means of (4), similarly to the means of (3), a wiring board manufactured by using a tape material having a conductive thin film provided on one main surface of the insulating base material is used. An LGA type semiconductor device can be obtained by using the same. Also, by providing the conductive member in the via hole in a concave shape, even when the conductive member and the external electrode of the semiconductor chip are connected by a projecting conductor, part of the projecting conductor is sucked into the via hole. Therefore, the mounting height (stand-off) of the semiconductor chip from the wiring board can be reduced.

(5) Wiring and external connection terminals are formed on the first main surface of the insulating base material, and via holes are formed in the insulating base at portions of the wiring connected to the external electrodes of the semiconductor chip. And forming a conductive member in the via hole by plating, and forming a plating layer on the surface of the conductive member and the surface of the external connection terminal. This is a method of manufacturing a wiring board, wherein the thickness of the central portion of the via hole is larger than the thickness of the side wall portion of the via hole.

According to the means (5), a via hole is provided in a portion of the insulating base material overlapping with the external electrode of the semiconductor chip, and a convex conductive member is formed in the via hole. Since the conductive member can be used as a conductor (bump) for connecting to an external electrode of a semiconductor chip,
A wiring substrate used for an LGA type semiconductor device can be manufactured using a tape material having a conductive thin film formed only on one main surface side of the insulating base material. Therefore, the manufacturing process of the wiring board used for the LGA type semiconductor device is simplified,
Manufacturing costs can be reduced.

(6) Wiring and its external connection terminals are formed on the first main surface of the insulating base material, and via holes are formed in the insulating base material at portions of the wiring connected to the external electrodes of the semiconductor chip. And forming a conductive member in the via hole by plating, and forming a plating layer on the surface of the conductive member and the surface of the external connection terminal. This is a method for manufacturing a wiring board in which a thickness of a central portion of a via hole is formed to be smaller than a thickness of a side wall portion of the via hole.

According to the means of (6), similarly to the means of (5), an LGA type semiconductor is formed by using a tape material having a conductive thin film formed only on one main surface side of the insulating base material. A wiring board used for the device can be manufactured. Therefore, the manufacturing process of the wiring board used for the LGA type semiconductor device can be simplified, and the manufacturing cost can be reduced.

In the means of (5) and (6), the plating layer formed on the surface of the conductive member may be, for example, a plating layer of a tin alloy such as tin-silver, tin-bismuth, or tin-copper. By doing so, the bondability between the external electrode surface of the semiconductor chip and gold is improved. Further, by using an alloy containing no lead as the tin alloy, the burden on the environment can be reduced. The plating layer may be a noble metal plating layer of, for example, gold, palladium, silver, or the like, in addition to the tin alloy. In the case of the noble metal plating layer, it is difficult to form an oxide film on the surface of the plating layer, so that it is possible to prevent a decrease in reliability of connection between the semiconductor chip and external electrodes.

In the case of forming a conductive member in which the center of the via hole is thin and concave as in the means of the above (6), it is added to a plating solution in order to flatten the surface of the plating layer. Adjust the leveler amount.

Hereinafter, the present invention will be described in detail along with embodiments (examples) with reference to the drawings.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

[0034]

(Embodiment 1) FIGS. 1 and 2 are schematic views showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention. FIG. 1 is a view seen from an external connection terminal side of the semiconductor device. FIG. 2 is a schematic cross-sectional view taken along line AA ′ of FIG.

1 and 2, reference numeral 1 denotes an insulating base material;
201 is a wiring, 202 is an external connection terminal (land), 3A
Is a convex conductive member (bump), 4A and 4B are plating layers, 5 is a semiconductor chip, 501 is an external electrode of the semiconductor chip, 6 is a sealing insulator, and 7 is a wiring protection film.

The semiconductor device of the first embodiment is shown in FIGS.
As shown in FIG. 1, a wiring 201 and its external connection terminals 202 are provided on a first main surface of an insulating base material 1 such as a polyimide tape, and a predetermined position of the wiring 201, in other words, an external electrode of a semiconductor chip is planar. A via hole 101 is provided in a portion of the insulating base material 1 that overlaps with the conductive member 3A, and the conductive member 3A is filled in the via hole 101. The surface of the conductive member 3A has a plating layer 4A and the surface of the external connection terminal 202 has a surface. A semiconductor chip 5 is provided on a wiring board provided with a plating layer 4B.
The external electrode 501 and the conductive member 3A are mounted so as to face each other, the conductive member 3A and the external electrode 501 of the semiconductor chip are electrically connected, and the space between the semiconductor chip 5 and the insulating base material 1 is sealed. This is an LGA (Land Grid Array) type semiconductor device sealed with an insulating insulator 6. The entire surface of the wiring 201 and the outer peripheral portion of the external connection terminal 202 are covered with a wiring protective film 7 such as a solder resist, and the external connection terminal 202 can be used as a connection terminal (land) of an external device. it can. Further, as shown in FIG. 2, the conductive member 3 </ b> A
1 is thicker than the thickness of the side wall of the via hole 101, and has a second portion facing the first main surface of the insulating base material 1.
It has a convex shape protruding from the main surface.

FIGS. 3 and 4 are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device of the first embodiment, and show cross-sectional views taken along the line AA 'of FIG. 1 in respective manufacturing steps. I have.

Hereinafter, the first embodiment will be described with reference to FIGS.
A method of manufacturing a semiconductor device will be described.

First, a conductive thin film layer made of copper or the like is formed on one main surface of the insulating base material 1 such as a polyimide tape by sputtering or the like.
In other words, after a via hole 101 is formed by, for example, a laser or the like in a portion that planarly overlaps the external electrode of the semiconductor chip, the conductive thin film layer is etched, and
The wiring 201 and its external connection terminals 202 are formed as shown in FIG. In addition, for example, an adhesive layer made of, for example, an epoxy-based thermosetting resin is formed on the first main surface of the insulating base material 1, and the insulating material is punched out by a mold. After forming via holes 101 at predetermined positions of the base material 1 and the adhesive layer, a conductive thin film such as a copper foil is bonded to the insulating base material 1 with the adhesive layer, and the conductive thin film is etched to form the wiring 201. And its external connection terminal 202
May be formed.

Next, as shown in FIG. 3B, a conductive member (bump) 3A is formed in the via hole 101 by using, for example, an electrolytic copper plating method or an electroless copper plating method. At this time, in the conductive member 3A, as shown in FIG. 3B, the thickness of the central portion of the via hole 101 is larger than the thickness of the side wall portion of the via hole 101, and the insulating substrate The first main surface (the wiring forming surface) is formed in a convex shape protruding from the second main surface facing the first main surface. The conductive member 3A
The difference between the thickness of the center portion and the thickness of the side wall portion can be arbitrarily selected by adjusting the amount of an additive such as a leveler added to the plating solution.

Next, a wiring protective film 7 such as a solder resist is formed so as to cover the entire surface of the wiring 201 and the outer peripheral portion of the external connection terminal 202, and as shown in FIG. A plating layer is formed on the surface of the conductive member (bump) 3A and the exposed surface of the external connection terminal 202. The plating layer is, for example, tin-silver (Sn-Ag) plating,
Bismuth (Sn-Bi) plating, tin-copper (Sn-Cu)
It is formed by tin alloy plating such as plating or noble metal plating such as gold, palladium, and silver.

According to the above procedure, a wiring board used for the semiconductor device of the first embodiment can be obtained.

Next, as shown in FIG. 4, a semiconductor chip 5 is provided on the second main surface side of the insulating base material 1 (wiring board), and the convex conductive member (bump) 3A and the The external electrodes 501 of the semiconductor chip 5 are aligned and mounted.
By heating, the external electrode 5 of the semiconductor chip is electrically connected to the conductive member 3A. Then, the semiconductor chip 5
When a sealing insulator 6 such as an epoxy-based thermosetting resin is poured and cured between the semiconductor chip 5 and the insulating base material 1 (wiring board) from the side surface of the semiconductor chip 5, as shown in FIGS. Semiconductor device can be obtained.

In the semiconductor device of the first embodiment, since the external connection terminal 202 can be used as a mounting terminal (land), a ball terminal for mounting is used as in a conventional BGA type semiconductor device. The connection does not need to be made, and the semiconductor device can be made thinner by the height of the ball terminals.

FIG. 5 is a schematic sectional view for explaining the operation and effect of the semiconductor device of the first embodiment.

As shown in FIG. 5, when the semiconductor device of the first embodiment is mounted on the mounting substrate 8 provided with the wiring 801, the external connection formed on the first main surface of the insulating base material 1 is formed. The terminals 202 are exposed on the surface of the semiconductor device, and since the plating layer 4B such as a tin alloy is formed on the surface, the terminals 202 can be mounted on the mounting substrate 8 such as a motherboard without connecting the ball terminals. Therefore, the height t from the mounting surface 8A of the mounting substrate 8 to the upper surface 5A of the semiconductor chip 5 can be reduced as compared with the conventional case where mounting is performed using ball terminals.

As described above, according to the first embodiment, the via hole 101 is provided in a portion of the insulating base material 101 which overlaps the external electrode of the semiconductor chip in a plane, and the via hole 101 is formed by plating. By forming the convex conductive member 3 </ b> A, the conductive member 3 </ b> A and the external electrode 501 of the semiconductor chip 5 can be connected. Further, the surface of the insulating substrate 1 on which the semiconductor chip 5 is mounted (second surface).
The wiring 201 and its external connection terminals 202 are formed on a surface (first main surface) opposite to the main surface), the external connection terminals 202 are formed at predetermined positions, and a plating layer of a tin alloy or the like is formed on the surface thereof. By providing the 4B, an LGA type semiconductor device without a connection terminal such as a ball terminal can be manufactured. At this time, the wiring substrate used for the semiconductor device can be manufactured using a tape material with a single-sided copper foil having a conductive thin film such as a copper foil formed on one main surface side of the insulating base material. The manufacturing cost of the wiring board can be reduced.

Also, unlike a BGA type semiconductor device, it is not necessary to connect a ball terminal to the external connection terminal, so that the height from the mounting surface of the semiconductor device when mounted on a mounting board is reduced. be able to.

The surface of the external electrode 501 of the semiconductor chip 5 electrically connected to the conductive member 3 is generally provided with a gold bump or the like.
By forming the plating layer 4B formed on the surface of A into a tin alloy plating layer such as tin-silver plating, tin-bismuth plating, or tin-copper plating, the conductive member 3 and the external electrode 501 are made of gold-tin. Bonding by mutual diffusion improves connection reliability. Further, by using a tin alloy containing no lead as the tin alloy plating, the load on the environment can be reduced.

When a noble metal plating such as gold, palladium, silver or rhodium is formed instead of the tin alloy plating as the plating layer 4B, the plating layer 4B
It is difficult to form an oxide film on the surface of the (conductive member 3). Therefore, for example, a film-like sealing material such as NCF (Non-Conductive Film) is provided on the wiring board, and the film-like sealing material is pushed away by gold bumps provided on the external electrodes 501 of the semiconductor chip 5, and the gold-containing material is pressed. Even when the film-like sealing material is cured and sealed while the bumps and the conductive member 3 are in contact with each other, the connection reliability between the gold bumps on the external electrodes 501 of the semiconductor chip and the conductive member 3 can be improved. Drop can be prevented.

(Embodiment 2) FIG. 6 is a schematic sectional view showing a schematic configuration of a semiconductor device according to Embodiment 2 of the present invention, and shows a cross section taken along line AA 'of FIG.

The semiconductor device of the second embodiment is the same as that of the first embodiment.
6, the wiring 201 and its external connection terminals 202 are provided on the first main surface of the insulating substrate 1 such as a polyimide tape, as shown in FIG.
A via hole 101 is provided in a predetermined position of the wiring 201, in other words, a portion of the insulating base material 1 that overlaps the external electrode of the semiconductor chip in a plane, and the via hole 101 is filled with a concave conductive member 3B. On a wiring board provided with a plating layer 4A on the surface of the conductive member 3B and a plating layer 4B on the surface of the external connection terminal 202, the semiconductor chip 5, the external electrode 501 and the conductive member 3B are provided. The conductive member 3B and the external electrode 501 of the semiconductor chip 5 are electrically connected to each other, and the space between the semiconductor chip 5 and the insulating base material 1 (wiring board) is sealed by a sealing insulator 6. It is a stopped LGA (Land Grid Array) type semiconductor device. In addition, the conductive member 3B is formed as shown in FIG.
As shown in the figure, the thickness of the central portion of the via hole 101 is a concave shape smaller than the thickness of the side wall portion of the via hole 101, and the conductive member 3B and the external electrode 50 of the semiconductor chip are formed.
1 is connected by a projecting conductor 9 such as a solder bump.

7 to 9 are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device of the second embodiment, and show cross-sectional views taken along the line AA 'of FIG. 1 in respective manufacturing steps. I have.

Hereinafter, the first embodiment will be described with reference to FIGS.
A method of manufacturing a semiconductor device will be described.

First, a via hole 10 is placed at a predetermined position of the insulating base material 1 such as a polyimide tape, in other words, at a position that overlaps the external electrode of the semiconductor chip in a plane, for example, with a laser or the like.
1 and a conductive thin film layer of, for example, copper or the like is formed on one main surface of the insulating base material 1 by sputtering, and then the conductive thin film layer is etched.
The wiring 201 and its external connection terminals 202 are formed as shown in FIG. In addition, for example, an adhesive layer made of, for example, an epoxy-based thermosetting resin is formed on the first main surface of the insulating base material 1, and the insulating material is punched out by a mold. After forming via holes 101 at predetermined positions of the base material 1 and the adhesive layer, a conductive thin film such as a copper foil is bonded to the insulating base material 1 with the adhesive layer, and the conductive thin film is etched to form the wiring 201. And its external connection terminal 202
May be formed.

Next, as shown in FIG. 7B, a conductive member (bump) 3B is formed in the via hole 101 by using, for example, an electrolytic copper plating method or an electroless copper plating method. The conductive member 3B formed by each of the plating methods
As shown in FIG. 7B, the thickness of the center of the via hole 101 is smaller than the thickness of the side wall of the via hole 101,
The amount of the leveler added to the plating solution is adjusted so as to form a concave shape. At this time, the conductive member 3B in the via hole 101 is formed to a height at least about half the depth of the via hole 101.

Next, a wiring protective film 7 such as a solder resist is formed so as to cover the entire surface of the wiring 201 and the outer peripheral portion of the external connection terminal 202, and as shown in FIG. Plating layer 4 on the surface of conductive member (bump) 3B
A and the plating layer 4B on the exposed surface of the external connection terminal 202
To form The plating layer 4B is made of, for example, tin-silver (S
tin alloy plating such as n-Ag) plating, tin-bismuth (Sn-Bi) plating, tin-copper (Sn-Cu) plating,
It is formed by plating of gold, palladium, silver, or the like.

According to the above-described procedure, a wiring board used for the semiconductor device of the second embodiment can be obtained.

Next, as shown in FIG. 8, a semiconductor chip 5 is provided on the second main surface of the insulating substrate 1 (wiring substrate) opposite to the surface (first main surface) on which the wiring is formed. The conductive member (bump) 3B and the external electrode 5 of the semiconductor chip 5
01 and then mount. At this time, projecting conductors 9 such as solder bumps are formed on the external electrodes 501 of the semiconductor chip as shown in FIG.

Next, when the solder bump 9 is heated,
A part thereof flows into the via hole 101, and the external electrode 501 of the semiconductor chip 5 and the conductive member 3B are electrically connected by the solder bump 9, as shown in FIG. Thereafter, a sealing insulator 6 such as an epoxy-based thermosetting resin is poured into the space between the semiconductor chip 5 and the insulating base material 1 (wiring board) from the side surface of the semiconductor chip 5 to form a seal. And the semiconductor device as shown in FIG. 6 can be obtained. At this time, since the external connection terminals 202 formed on the first main surface of the insulating base material 1 are exposed on the surface of the semiconductor device, and a plating layer of a tin alloy or the like is formed on the surface, An LGA type semiconductor device that can be mounted on a mounting substrate such as a motherboard without connecting ball terminals.

In the semiconductor device of the second embodiment, since the external connection terminal 202 can be used as a mounting terminal (land), a ball terminal is not connected unlike a conventional BGA type semiconductor device. The thickness of the semiconductor device can be reduced by the height of the ball terminals.

FIG. 10 is a schematic sectional view for explaining the operation and effect of the semiconductor device of the second embodiment.

As shown in FIG. 10, when the semiconductor device of the second embodiment is mounted on the mounting substrate 8 provided with the wiring 801, the external connection formed on the first main surface of the insulating base material 1 is formed. The terminals 202 are exposed on the surface of the semiconductor device, and since the plating layer 4B such as a tin alloy is formed on the surface, the terminals 202 can be mounted on a mounting board such as a motherboard without connecting ball terminals. For this reason, the mounting surface 8 of the mounting substrate 8 is compared with a conventional case where mounting is performed using ball terminals.
The height t from A to the upper surface 5A of the semiconductor chip 5 can be reduced. Also, via holes 10 in the insulating base material 1
1, a recessed conductive member 3B is formed, and a part of the projecting conductor provided on the external electrode of the semiconductor chip is poured into the via hole 101, so that a conventional external electrode of the semiconductor chip is formed. Can be reduced in height (stand-off) from the wiring board, and a thinner semiconductor device can be obtained.

As described above, according to the second embodiment, a via hole 101 is provided in a portion of the insulating base material 101 which overlaps the external electrode of the semiconductor chip in a plane, and the via hole 101 is formed by plating. By forming the convex conductive member 3 </ b> A, the conductive member 3 </ b> A and the external electrode 501 of the semiconductor chip 5 can be connected. Further, the surface of the insulating substrate 1 on which the semiconductor chip 5 is mounted (second surface).
The wiring 201 and its external connection terminals 202 are formed on a surface (first main surface) opposite to the main surface), the external connection terminals 202 are formed at predetermined positions, and a plating layer of a tin alloy or the like is formed on the surface thereof. By providing the 4B, an LGA type semiconductor device without a connection terminal such as a ball terminal can be manufactured. At this time, the wiring substrate used for the semiconductor device can be manufactured using a tape material with a single-sided copper foil having a conductive thin film such as a copper foil formed on one main surface side of the insulating base material. The manufacturing cost of the wiring board can be reduced.

Further, unlike the BGA type semiconductor device, the ball terminals need not be connected to the external connection terminals, so that the height from the mounting surface of the semiconductor device when mounted on the mounting board is reduced. be able to.

The surface of the external electrode 501 of the semiconductor chip 5 electrically connected to the conductive member 3B is generally provided with a gold bump or the like, and is formed on the surface of the conductive member 3B. The plating layer 4B is formed by tin-silver plating,
By forming a tin alloy plating layer such as tin-bismuth plating or tin-copper plating, the conductive member 3B and the external electrode 501 are formed.
Are bonded by mutual diffusion of gold-tin to improve connection reliability. Further, by using a tin alloy containing no lead as the tin alloy plating, the load on the environment can be reduced.

When a noble metal plating such as gold, palladium, silver, rhodium or the like is formed instead of the tin alloy plating as the plating layer 4B, the plating layer 4B
It is difficult to form an oxide film on the surface of the (conductive member 3). Therefore, for example, a film-like sealing material such as NCF (Non-Conductive Film) is provided on the wiring board, and the film-like sealing material is pushed away by gold bumps provided on the external electrodes 501 of the semiconductor chip 5, and the gold-containing material is pressed. Even when the film-like sealing material is cured and sealed in a state where the bumps and the conductive member 3B are in contact with each other, the connection reliability between the gold bumps on the external electrodes 501 of the semiconductor chip and the conductive member 3B can be improved. Drop can be prevented.

As described above, the present invention has been specifically described based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Of course.

[0069]

According to the invention disclosed in the present invention,
The effect obtained by the representative one will be briefly described as follows.

(1) A semiconductor device having a semiconductor chip mounted on a wiring board can be made thinner.

(2) The height from the mounting substrate to the upper surface of the semiconductor device when the semiconductor device having the semiconductor chip mounted on the wiring substrate is mounted on the mounting substrate can be reduced.

(3) The manufacturing process of the wiring board used for the LGA type semiconductor device can be simplified, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view illustrating a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view taken along line A-A 'of FIG.

3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. FIGS. 3A, 3B, and 3C are each a diagram illustrating a method for manufacturing a wiring substrate. It is a schematic cross section in a process.

FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 5 is a schematic cross-sectional view for explaining the operation and effect of the semiconductor device of the first embodiment.

6 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment of the present invention, which is a schematic cross-sectional view taken along a line AA ′ in FIG. 1;

FIGS. 7A, 7B, and 7C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment. FIGS. It is a schematic cross section in a process.

FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment.

FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment.

FIG. 10 is a schematic cross-sectional view for explaining the operation and effect of the semiconductor device of the second embodiment.

FIG. 11 is a schematic diagram showing a schematic configuration of a conventional BGA type semiconductor device, and FIG. 10A is a schematic plan view of the semiconductor device;
FIG. 10B is a schematic cross-sectional view taken along line BB ′ of FIG.

FIG. 12 is a schematic cross-sectional view for explaining a problem of a conventional BGA type semiconductor device.

FIG. 13 is a schematic sectional view illustrating a schematic configuration of a conventional LGA type semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating base material 101 via hole 201 wiring 202 external connection terminal 203 through-hole plating 3A convex conductive member 3B concave conductive member 4A, 4B plating layer 5 semiconductor chip 501 external electrode of semiconductor chip 5A top surface of semiconductor chip Reference Signs List 6 sealing insulator 7 wiring protective film 8 mounting substrate 801 wiring on mounting substrate 8A mounting surface of mounting substrate 9 projecting conductor 10 ball terminal 11 solder paste

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Norio Okabe 5-1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Cable Engineering Co., Ltd. (Reference) 5E336 AA04 BB02 BC01 CC32 CC43 CC55 GG30 5F044 KK17 KK19 LL01 QQ06

Claims (9)

[Claims] A wiring and an external connection terminal are provided on a first main surface of an insulating base material, a via hole is provided in the insulating base material at a predetermined position of the wiring, and a conductive material is provided in the via hole. In a wiring board in which a member is filled and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal, a thickness of a center portion of the via hole is a side wall of the via hole. The thickness of the first portion of the insulating base material is larger than the thickness of the portion.
A wiring substrate protruding from a second main surface facing the main surface. 2. A wiring and an external connection terminal are provided on a first main surface of the insulating base material, a via hole is provided in the insulating base material at a predetermined position of the wiring, and a conductive material is provided in the via hole. In a wiring board in which a member is filled and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal, a thickness of a center portion of the via hole is a side wall of the via hole. A wiring board characterized by being thinner than the thickness of the part. 3. The wiring board according to claim 1, wherein an insulating layer is provided on an entire surface of the wiring and an outer peripheral portion of the external connection terminal, and plating is performed on an exposed surface near a center of the external connection terminal. A wiring board, comprising a layer. 4. The wiring board according to claim 1, wherein the plating layer is made of a tin-silver (Sn—Ag) alloy, a tin-bismuth (Sn—Bi) alloy, A wiring substrate, which is one of a copper (Sn-Cu) alloy. 5. The wiring board according to claim 1, wherein the plating layer is made of one of gold (Au), palladium (Pd), silver (Ag), and rhodium (Rh). A wiring substrate comprising one or an alloy containing at least one of them. 6. A wiring and an external connection terminal are provided on a first main surface of the insulating base material, and a via hole is provided at a position of the insulating base material overlapping with an external electrode of the semiconductor chip in a plane.
A semiconductor chip has an external electrode and the conductive member facing a wiring board in which a conductive member is filled in the via hole and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal. Wherein the conductive member and the external electrode of the semiconductor chip are electrically connected, and the connection portion between the semiconductor chip and the conductive member and the external electrode is sealed with a sealing insulator. Semiconductor device. 7. A wiring and an external connection terminal are provided on the first main surface of the insulating base material, a via hole is provided in the insulating base material at a predetermined position of the wiring, and a conductive material is provided in the via hole. A semiconductor chip is mounted on a wiring board in which a member is filled and a plating layer is provided on a surface of the conductive member and a surface of the external connection terminal so that an external electrode thereof and the conductive member face each other. In a semiconductor device in which a conductive member and an external electrode of a semiconductor chip are electrically connected, and a connecting portion between the semiconductor chip and the conductive member and the external electrode is sealed with a sealing insulator, the conductive member is A semiconductor device, wherein a thickness of a central portion of a via hole is smaller than a thickness of a side wall portion of the via hole, and the conductive member and an external electrode of a semiconductor chip are electrically connected by a projecting conductor. . 8. A wiring and an external connection terminal thereof are formed on a first main surface of the insulating base material, and a via hole is formed in a portion of the insulating base material connected to the external electrode of the semiconductor chip. Forming a conductive member in the via hole by plating, and forming a plating layer on a surface of the conductive member and a surface of the external connection terminal, wherein the conductive member comprises the via A method of manufacturing a wiring board, wherein a thickness of a center portion of a hole is formed to be larger than a thickness of a side wall portion of the via hole. 9. A wiring and an external connection terminal thereof are formed on the first main surface of the insulating base material, and a via hole is formed in a portion of the insulating base material connected to the external electrode of the semiconductor chip of the wiring. Forming a conductive member in the via hole by plating, and forming a plating layer on a surface of the conductive member and a surface of the external connection terminal, wherein the conductive member comprises the via A method of manufacturing a wiring board, wherein a thickness of a center portion of a hole is formed to be smaller than a thickness of a side wall portion of the via hole.