CN117727705A

CN117727705A - Electronic device and method of manufacturing the same

Info

Publication number: CN117727705A
Application number: CN202311175916.6A
Authority: CN
Inventors: 朴大洋; 金炳辰; 金吉江; 江亨义; 孙权守; 金进勇
Original assignee: Anrely Technology Singapore Holdings Pte Ltd
Current assignee: Anrely Technology Singapore Holdings Pte Ltd
Priority date: 2022-09-17
Filing date: 2023-09-13
Publication date: 2024-03-19

Abstract

In one example, an electronic device includes an embedded module including a module substrate and a module assembly coupled to the module substrate. A device substrate is coupled to the first module substrate. A device terminal is coupled to the module assembly, and a device encapsulant structure encapsulates the embedded module, the device substrate, and the device terminal. A portion of the device substrate is exposed from the device encapsulant structure and a portion of the device terminals is exposed from the device encapsulant structure. Other examples and related methods are also disclosed herein.

Description

Electronic device and method of manufacturing the same

Cross Reference to Related Applications

The present application claims priority from U.S. provisional application No. 63/407,650, filed on month 17 of 2022, and U.S. provisional application No. 63/444,024, filed on month 8 of 2023, which provisional applications are hereby incorporated by reference.

Technical Field

The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods for manufacturing semiconductor devices.

Background

Existing semiconductor packages and methods for forming semiconductor packages suffer from drawbacks, such as excessive cost, reduced reliability, relatively low performance, or excessive package size. Additional limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure and through reference to the drawings.

Disclosure of Invention

The present description includes, among other features, structures and related methods relating to electronic devices having embedded modules and heat transfer or cooling structures. In some examples, an electronic device includes an embedded module having a module component attached to a module substrate. In some examples, the module substrate is coupled to the device terminals and the conductive substrate is coupled to an opposite side of the embedded module. In some examples, the device terminals may include a leadframe. In some examples, the conductive substrate may be thermally conductive. In some examples, the conductive substrate may be thermally and electrically conductive.

In some examples, an embedded module may include a pair of module substrates located on opposite sides of a module component (e.g., a power semiconductor component). In some examples, the pair of module substrates may be electrically coupled together. In some examples, the signal transmission structure may be attached to the embedded module. In other examples, the signal transmission structure may be attached to one or both conductive substrates. In some examples, the electronic device is enclosed within a package, with one or more features exposed from portions of the package. The structure and method of the present disclosure avoids the use of spacer structures, among other things, which has caused stacking tolerance problems in the past. Such stack-up tolerance issues have resulted in package non-planarity and component cracking issues.

In an example, an electronic device includes a first embedded module including a first module substrate and a first module assembly coupled to the first module substrate. A first device substrate is coupled to the first module substrate. A device terminal is coupled to the first module assembly, and a device encapsulant structure encapsulates the first embedded module, the first device substrate, and the device terminal. A portion of the first device substrate is exposed from the device encapsulant structure and a portion of the device terminal is exposed from the device encapsulant structure.

In an example, an electronic device includes a first embedded module including a first module substrate including a first conductive structure, a second module substrate including a second conductive structure, and a first module assembly interposed between the first module substrate and the second module substrate. The first module assembly includes a first assembly terminal coupled to the first conductive structure and a second assembly terminal coupled to the second conductive structure. A first device substrate is coupled to the first module substrate and includes a first outward conduction layer. A second device substrate is coupled to the second module substrate and includes a second outward conduction layer. A device terminal is coupled to the first module assembly, and a device encapsulant structure encapsulates the first embedded module, the first device substrate, the second device substrate, and the device terminal. The device terminals, the first outward conductive layer, and the second outward conductive layer are exposed from the device encapsulant structure.

In an example, a method of manufacturing an electronic device includes providing a first embedded module including a first module substrate including a first conductive structure, a second module substrate including a second conductive structure, and a first module assembly interposed between the first module substrate and the second module substrate. The first module assembly includes a first assembly terminal coupled to the first conductive structure and a second assembly terminal coupled to the second conductive structure. The method includes providing a first device substrate coupled to the first module substrate, the first device substrate including a first outward conduction layer. The method includes providing a second device substrate coupled to the second module substrate, the second device substrate including a second outward conduction layer. The method couples a device terminal to the module assembly. The method includes providing a device encapsulant structure that encapsulates the first embedded module, the first device substrate, the second device substrate, and the device terminals. The device terminals, the first outward conductive layer, and the second outward conductive layer are exposed from the device encapsulant structure.

Drawings

Fig. 1 illustrates a cross-sectional view of an example electronic device.

Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, 2O, 2P, 2Q, 2R, and 2S illustrate cross-sectional views of example methods for manufacturing example electronic devices.

Fig. 3 illustrates a cross-sectional view of an example electronic device.

Fig. 4 illustrates a cross-sectional view of an example electronic device.

Fig. 5 illustrates a cross-sectional view of an example electronic device.

Fig. 6 illustrates a cross-sectional view of an example electronic device.

Fig. 7A, 7B, 7C, and 7D illustrate cross-sectional views of example methods for manufacturing example electronic devices.

Fig. 8 illustrates a cross-sectional view of an example electronic device.

Fig. 9A, 9B, 9C, 9D, and 9E illustrate cross-sectional views of example methods for manufacturing example electronic devices.

Fig. 10 illustrates a cross-sectional view of an example electronic device.

Fig. 11 illustrates a cross-sectional view of an example electronic device.

Fig. 12 illustrates a cross-sectional view of an example electronic device.

Fig. 13 illustrates a cross-sectional view of an example electronic device.

Fig. 14A, 14B, 14C, and 14D illustrate cross-sectional views of example methods for manufacturing example electronic devices.

Fig. 15 illustrates a cross-sectional view of an example electronic device.

Fig. 16 illustrates a cross-sectional view of an example electronic device.

17A, 17B, 17C, 17D, and 17E illustrate cross-sectional views of example methods for manufacturing example electronic devices.

Fig. 18 illustrates a cross-sectional view of an example electronic device.

Fig. 19 illustrates a cross-sectional view of an example stacked embedded module.

20A, 20B, 20C, 20D, and 20E illustrate cross-sectional views of an example method for manufacturing an example stacked embedded module.

Fig. 21 illustrates a cross-sectional view of an example electronic device.

Fig. 22 illustrates a cross-sectional view of an example electronic device.

Fig. 23 illustrates a cross-sectional view of an example electronic device.

Fig. 24 illustrates a cross-sectional view of an example electronic device.

Fig. 25 illustrates a cross-sectional view of an example electronic device.

Fig. 26 illustrates a cross-sectional view of an example electronic device.

Fig. 27 illustrates a cross-sectional view of an example electronic device.

Fig. 28 illustrates a cross-sectional view of an example electronic device.

Fig. 29 illustrates a cross-sectional view of an example electronic device.

Fig. 30A shows a perspective view of an example electronic device.

FIG. 30B illustrates a cross-sectional view of the example electronic device taken along line 30B-30B in FIG. 30A.

FIG. 30C illustrates a cross-sectional view of the example electronic device taken along line 30C-30C in FIG. 30A.

Fig. 31A shows a cross-sectional view of an example embedded module taken along line 31A-31A in fig. 33A and 33B.

FIG. 31B illustrates a cross-sectional view of an example embedded module taken along line 31B-31B in FIGS. 33A and 33B.

Fig. 32A shows a top plan view of a first module substrate of the embedded module of fig. 31A and 31B.

Fig. 32B shows a bottom plan view of a second module substrate of the embedded module of fig. 31A and 31B.

Fig. 33A illustrates a top plan view of a module assembly coupled to the first module substrate of fig. 31A and 31B.

Fig. 33B illustrates a bottom plan view of the module assembly coupled to the second module substrate of fig. 31A and 31B.

Fig. 34A shows a top plan view of an inward metal layer pattern of a first device substrate of the electronic device of fig. 30A, 30B, and 30C.

Fig. 34B shows a bottom plan view of the inward metal layer pattern of the second device substrate of the electronic device of fig. 30A, 30B, and 30C.

Fig. 35A illustrates a plan view of an embedded module coupled to an inward metal layer of the first device substrate of fig. 34A.

Fig. 35B illustrates a plan view of an embedded module coupled to the inward metal layer of the second device substrate of fig. 34B.

The following discussion provides various examples of semiconductor devices and methods of fabricating semiconductor devices. Such examples are not limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "e.g." are non-limiting.

The drawings show general construction and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the disclosure. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of examples discussed in the present disclosure. Cross-hatching may be used to represent different portions of the drawings, but does not necessarily represent the same or different materials. Like numbers refer to like elements throughout the disclosure. Accordingly, elements having the same element numbers may be shown in the figures but need not be repeated here for clarity.

The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any element in the three-element set { (x), (y), (x, y) }. As another example, "x, y, or z" means any element in a seven-element set { (x), (y), (z), (x, y), (x, z), (y, z), (x, y, z) }.

The terms "comprises," "comprising," "includes," and "including" are open-ended terms and specify the presence of the stated features, but do not preclude the presence or addition of one or more other features.

The terms "first," "second," and the like may be used herein to describe various elements and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in this disclosure could be termed a second element without departing from the teachings of the disclosure.

The term "coupled," unless otherwise specified, may be used to describe two elements as directly contacting each other or as indirectly connected through one or more other elements. For example, if element a is coupled to element B, element a may be directly contacting element B or indirectly connected to element B through intermediate element C. As used herein, the term "coupled" may refer to either an electrical coupling or a mechanical coupling. Similarly, the term "above … …" or "on … …" may be used to describe two elements in direct contact with each other or to describe two elements indirectly connected by one or more other elements.

Detailed Description

Other examples are included in this disclosure. Such examples may be found in the drawings, claims, or in the specification of the present disclosure.

Fig. 1 illustrates a cross-sectional view of an example electronic device 10. In the example shown in fig. 1, the electronic device 10 may include an embedded module 11, a device substrate 12, a device substrate 13, device terminals 14, and a device encapsulant 15.

The embedded module 11 may include a first module substrate 111, a second module substrate 112, module interconnects 113, a module encapsulant 114, and one or more module assemblies 115. The first module substrate 111 may include a conductive structure 1111 and a dielectric structure 1112. Conductive structure 1111 may include inward terminals 1111i, outward terminals 1111o, traces 1111t, and plating 1111p. The second module substrate 112 may include a conductive structure 1121 and a dielectric structure 1122. The conductive structure 1121 may include an inward terminal 1121i, an outward terminal 1121o, a trace 1121t, and a plating 1121p. The module assemblies 115 may each include assembly terminals 1151, 1152, and 1153.

The device substrate 12 may include an inward metal layer 121, an outward metal layer 122, and a core layer 123. The inward metal layer 121 may include inward terminals 121i and traces 121t. The device substrate 13 may include an inward metal layer 131, an outward metal layer 132, and a core layer 133. The inward metal layer 131 may include inward terminals 131i and traces 131t.

The first module substrate 111, the second module substrate 112, the module encapsulant 114, the device substrates 12 and 13, and the device encapsulant 15 may include or be referred to as an electronic package or a package, and may protect the module assembly 115 from exposure to external elements or environments. The electronic package may also provide a coupling between the module assembly 115 and an external assembly or other electronic package.

Fig. 2A-2S illustrate cross-sectional views of an example method for manufacturing the example electronic device 10. Fig. 2A shows a cross-sectional view of the electronic device 10 at an early stage of manufacture.

In the example shown in fig. 2A, a first module substrate 111 may be provided. In some examples, the first module substrate 111 may include copper, copper alloy, nickel alloy, iron, or iron-nickel alloy. In some examples, the thickness of the first module substrate 111 may be in the range of about 125 micrometers (μm) to about 250 μm.

Fig. 2B shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2B, the outward terminals 1111o may be provided on the bottom side of the first module substrate 111. The outward terminals 1111o may be provided by removing a portion of the first module substrate 111 from the bottom side of the first module substrate 111. In some examples, the outward terminals 1111o may be formed using an etching process. For example, the etching process may include dry etching (e.g., plasma etching, reactive Ion Etching (RIE) or sputter etching) or wet etching (e.g., immersion and spraying). The outward terminals 1111o may be unetched portions of the bottom side of the first module substrate 111.

Fig. 2C shows a cross-sectional view of the electronic device 10 at a later stage of manufacture. In the example shown in fig. 2C, a first dielectric structure 1112 may be provided. In some examples, the first dielectric structure 1112 may include or be referred to as a resin, a polymer with a filler, a molding compound, a protective material, or a molding material. In some examples, the dielectric structure 1112 may be provided by a film assist molding process, a compression molding process, a transfer molding process, or a liquid resin screen printing process. The dielectric structure 1112 may fill the removed or etched portion of the first module substrate 111 (e.g., the first dielectric structure 1112 may be deposited or interposed between the outward terminals 1111 o). Dielectric structure 1112 may electrically isolate outward terminals 1111o from each other. The outward terminals 1111o may be exposed from the dielectric structure 1112 at the bottom side of the first module substrate 111. In some examples, after overmolding the bottom side of the first module substrate 111, a portion of the dielectric structure 1112 may be removed by a grinding process, thereby exposing the outward terminals 1111o. The bottom side of dielectric structure 1112 may be coplanar with the bottom side of outward terminal 1111o. In some examples, the thickness of the dielectric structure 1112 may be in the range of about 87 μm to about 175 μm.

Fig. 2D shows a cross-sectional view of the electronic device 10 at a later stage of manufacture. In the example shown in fig. 2D, inward terminals 1111i and traces 1111t may be disposed on the top side of the first module substrate 111. The inward terminals 1111i may be provided by removing a portion of the first module substrate 111 from the top side of the first module substrate 111. In some examples, an etching process may be used to form inward terminals 1111i. The etching process may include dry etching (e.g., plasma etching, RIE or sputter etching) or wet etching (e.g., immersion and spraying). The inward terminals 1111i may be unetched portions of the top side of the first module substrate 111. The inward terminals 1111i may be exposed from the dielectric structure 1112 at the top side of the first module substrate 111. Inward terminal 1111i may be coupled to outward terminal 1111o.

The trace 1111t may be provided by removing a portion of the first module substrate 111 from the top side of the first module substrate 111. For example, trace 1111t may be formed by etching, as previously described with reference to inward terminal 1111i. In some examples, trace 1111t may be provided simultaneously with inward terminal 1111i. Trace 1111t may extend and couple to a side of inward terminal 1111i. Trace 1111t may extend in a generally horizontal direction over the top side of dielectric structure 1112. Trace 1111t may be exposed at the top side of first module substrate 111. Trace 1111t may be coupled to inward terminal 1111i and outward terminal 1111o. For example, at least some of the inward terminals 1111i may be coupled to the outward terminals 1111o by traces 1111t.

Fig. 2E shows a cross-sectional view of the electronic device 10 at a later stage of manufacture. In the example shown in fig. 2E, a plating layer 1111p may be provided. The plating layer 1111p may be disposed on the top and bottom sides of the first module substrate 111. In some examples, plating 1111p may be disposed on the surfaces of outward terminals 1111o, inward terminals 1111i, and traces 1111 t. In some examples, plating 1111p may be part of inward terminals 1111i or outward terminals 1111 o. In some examples, plating 1111p may include or be referred to as a coating or conductive coating. In some examples, the plating 1111p may include gold, silver, copper, platinum, tin, nickel, palladium, titanium, or tungsten. In some examples, plating 1111p may be provided by electroless plating or electroplating. In some examples, the thickness of the plating 1111p may be in the range of about 0.3 μm to about 15.2 μm. In some examples, outward terminals 1111o, inward terminals 1111i, and traces 1111t may be free of plating 1111p, such that first module substrate 111 may be incorporated into electronic device 10 without plating 1111p.

In some examples, inward terminals 1111i, outward terminals 1111o, traces 1111t, and plating 1111p may be referred to as conductive structures 1111. In other words, conductive structure 1111 may include inward terminals 1111i, outward terminals 1111o, traces 1111t, and plating 1111p. Conductive structure 1111 may include or be referred to as a conductive path, lead, terminal, pad, trace, or via. The conductive structures 1111 may transfer signals, currents or voltages within the first module substrate 111. In some examples, the first module substrate 111 may include or be referred to as a leadframe substrate, a Molded Leadframe (MLF), or a routable molded leadframe (rtMLF).

Fig. 2F shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2F, the module assembly 115 may be disposed on the first module substrate 111. In some examples, the module assembly 115 may include or be referred to as a power assembly, a power device, a power semiconductor device, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, a semiconductor die, a semiconductor chip, or a semiconductor package. In some examples, the module assembly 115 may include or be referred to as a compound semiconductor power device, such as a SiC power MOSFET or a GaN power device. Module assembly 115 may be coupled to inward terminals 1111i. The inward terminals 1111i provide a connection path between the module assembly 115 and the first module substrate 111. In some examples, module assembly 115 may be coupled to plating 1111p on inward terminals 1111i by an interface material. For example, an interface material may be provided on the plating 1111p, and the module assembly 115 may be located on the interface material to allow the module assembly 115 to be coupled to the plating 1111p through a reflow process. In some examples, the interface material may include a conductive adhesive, a conductive epoxy, a solder paste, or an Ag sintering paste.

In some examples, module assembly 115 may include assembly terminals 1151, 1152, and 1153. In some examples, component terminals 1151 and 1152 may be located on a first surface of module assembly 115, and component terminal 1153 may be located on a second surface of module assembly 115 opposite the first surface of module assembly 115. The assembly terminals 1151 and 1152 may be coupled to the first module substrate 111 and may contact the plating 1111p or the inward terminals 1111i. In some examples, component terminals 1151 and 1152 may be coupled to outward terminal 1111o through inward terminal 1111i or through inward terminal 1111i and trace 1111 t. In some examples, the thickness of the module assembly 115 may be in the range of about 55 μm to about 250 μm.

Component terminals 1151, 1152, and 1153 may include or be referred to as pads, bond pads, grounds, or metal layers. In some examples, component terminal 1151 may be referred to as a source, component terminal 1152 may be referred to as a gate, and component terminal 1153 may be referred to as a drain. Component terminals 1151, 1152 and 1153 may comprise copper, aluminum, palladium, titanium, tungsten, titanium/tungsten, nickel, gold or silver. In some examples, component terminals 1151, 1152, and 1153 may be provided as connection paths between module component 115 and first module substrate 111 or between module component 115 and second module substrate 112 (fig. 2M). In some examples, the thickness of component terminals 1151, 1152, and 1153 may be in the range of about 0.68 μm to about 6.55 μm.

Fig. 2G shows a cross-sectional view of the electronic device 10 at a later stage of manufacture. In the example shown in fig. 2G, a second module substrate 112 may be provided. In some examples, the second module substrate 112 may include copper, copper alloy, nickel alloy, iron, or iron-nickel alloy. In some examples, the thickness of the second module substrate 112 may be in the range of about 125 μm to about 250 μm. In some examples, the area (or "footprint") of the second module substrate 112 may be equal to the area (or footprint) of the first module substrate 111.

Fig. 2H shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2H, the outward terminals 1121o may be provided on the bottom side of the second module substrate 112. The outward terminals 1121o may be provided by removing a portion of the second module substrate 112 from the bottom side of the second module substrate 112. In some examples, outward terminal 1121o may be formed using an etching process, as previously described with reference to outward terminal 1111 o. For example, the outward terminals 1121o may be unetched portions of the bottom side of the second module substrate 112.

Fig. 2I shows a cross-sectional view of the electronic device 10 at a later stage of manufacture. In the example shown in fig. 2I, a dielectric structure 1122 may be provided. In some examples, the dielectric structure 1122 may include or be referred to as a resin, a polymer with a filler, a molding compound, a protective material, or a molding material. In some examples, the dielectric structure 1122 may be provided by a film assist molding process, a compression molding process, a transfer molding process, or a liquid resin screen printing process. The dielectric structure 1122 may fill the removed or etched portion of the second module substrate 112 (e.g., the dielectric structure 1122 may be deposited or interposed between the outward terminals 1121 o). The dielectric structure 1122 may electrically isolate the outward terminals 1121o from each other. The outward terminals 1121o may be exposed from the dielectric structure 1122 at the bottom side of the second module substrate 112. In some examples, after overmolding the bottom side of the second module substrate 112, a portion of the dielectric structure 1122 may be removed by a grinding process, thereby exposing the outward terminals 1121o. The bottom side of the dielectric structure 1122 may be coplanar with the bottom side of the outward terminal 1121o. In some examples, the thickness of the dielectric structure 1122 may be in the range of about 87 μm to about 175 μm.

Fig. 2J shows a cross-sectional view of the electronic device 10 at a later stage of manufacture. In the example shown in fig. 2J, inward terminals 1121i and traces 1121t may be disposed on the top side of the second module substrate 112. The inward terminals 1121i may be provided by removing a portion of the second module substrate 112 from the top side of the second module substrate 112. In some examples, inward terminal 1121i may be formed using an etching process, as previously described with reference to inward terminal 1111 i. The inward terminals 1121i may be unetched portions of the top side of the second module substrate 112. The inward terminals 1121i may be exposed from the dielectric structure 1122 at the top side of the second module substrate 112. The inward terminal 1121i may be coupled to the outward terminal 1121o.

Traces 1121t may be provided by removing a portion of second module substrate 112 from the top side of second module substrate 112. For example, the trace 1121t may be formed by etching, as previously described. In some examples, trace 1121t may be provided simultaneously with inward terminal 1121i. The trace 1121t may extend to and couple to a side of the inward terminal 1121i. The trace 1121t may extend in a generally horizontal direction over the top side of the dielectric structure 1122. Traces 1121t may be exposed from the top side of second module substrate 112. The trace 1121t may be coupled to an inward terminal 1121i and an outward terminal 1121o. For example, at least some of the inward terminals 1121i may be coupled to the outward terminals 1121o by traces 1121t.

Fig. 2K shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2K, a plating layer 1121p may be provided. The plating 1121p may be disposed on the top and bottom sides of the second module substrate 112. In some examples, plating 1121p may be provided on the surfaces of outward terminals 1121o, inward terminals 1121i, and traces 1121 t. In some examples, the plating 1121p may be part of the inward terminal 1121i or the outward terminal 1121 o. In some examples, the plating 1121p may include or be referred to as a coating or conductive coating. In some examples, the plating 1121p may include gold, silver, copper, platinum, tin, nickel, palladium, titanium, or tungsten. In some examples, the plating 1121p may be provided by electroless plating or electroplating. In some examples, the thickness of the plating 1121p may be in the range of about 0.3 μm to about 15.2 μm. In some examples, the outward terminals 1121o, inward terminals 1121i, and traces 1121t may be free of plating 1121p, such that the second module substrate 112 may be incorporated into the electronic device 10 without plating 1121p.

In some examples, the inward terminal 1121i, the outward terminal 1121o, the trace 1121t, and the plating 1121p may be referred to as a conductive structure 1121. In other words, the conductive structure 1121 may include an inward terminal 1121i, an outward terminal 1121o, a trace 1121t, and a plating 1121p. In some examples, the conductive structure 1121 may include or be referred to as a conductive path, lead, terminal, pad, trace, or via. The conductive structure 1121 may pass signals, currents, or voltages within the second module substrate 112.

In some examples, the second module substrate 112 may include or be referred to as a leadframe substrate, a molded substrate, or rtMLF. Although the first module substrate 111 and the second module substrate 112 are described as lead frames, it is contemplated and understood that in some examples, the first module substrate 111 or the second module substrate 112 may comprise a laminate or preformed substrate. The preformed substrate may be fabricated prior to attachment to the electronic device and may include a dielectric layer between respective conductive layers. The conductive layer may comprise, for example, copper and may be formed using an electroplating process. The dielectric layer may be a non-photodefinable layer that may be attached in a preformed film rather than in a liquid form, and may comprise a resin with a filler such as threads, wovens, or other inorganic particles for rigid or structural support. Since the dielectric layer is non-photodefinable, features such as vias or openings can be formed by using drilling or laser. In some examples, the dielectric layer may include a prepreg material or a flavoured-film stack (ABF). The preformed substrate may comprise a permanent core structure or carrier, such as a dielectric material including Bismaleimide Triazine (BT) or FR4, and the dielectric layer and conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting the permanent core structure, and the dielectric layer and the conductive layer may be formed on a sacrificial carrier that is removed after formation of the dielectric layer and the conductive layer and prior to attachment to the electronic device. The preformed substrate may be referred to as a Printed Circuit Board (PCB) or a laminate substrate. Such a preformed substrate may be formed by a half-addition process or a modified half-addition process.

Fig. 2L shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2L, the module interconnect 113 may be disposed on the second module substrate 112. The module interconnect 113 may be coupled to the inward terminal 1121i. In some examples, the module interconnects 113 may include or be referred to as solder balls, solder-coated metal core (e.g., cu core) balls, pillars with solder caps, or bumps. In some examples, the module interconnect 113 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), sn-Pb, sn37-Pb, sn95-Pb, sn-Pb-Ag, sn-Cu, sn-Ag, sn-Au, sn-Bi, or Sn-Ag-Cu. In some examples, the module interconnect 113 may be provided by a reflow process after a conductive material including solder is formed on the plated layer 1121p of the inward terminal 1121i. In some examples, the thickness of the module interconnect 113 may be in the range of about 150 μm to about 365 μm.

Fig. 2M shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2M, the second module substrate 112 may be disposed over the first module substrate 111. In some examples, the second module substrate 112 may be flipped such that the inward terminals 1121i of the second module substrate 112 are oriented toward the module assembly 115 and the first module substrate 111, and the outward terminals 1121o are located on the top side of the second module substrate 112. In some examples, after positioning the second module substrate 112 on the first module substrate 111, the second module substrate 112 may be coupled to the first module substrate 111 by, for example, thermocompression bonding. The module interconnect 113 may couple the second module substrate 112 to the first module substrate 111. For example, module interconnect 113 may be coupled to inward terminals 1111i or traces 1111t of first module substrate 111. The module assembly 115 may be coupled to the inward terminals 1121i or traces 1121t of the second module substrate 112. In some examples, component terminals 1153 of module component 115 may be coupled to inward terminals 1121i or traces 1121t of second module substrate 112. The side of the first module substrate 111 to which the module assembly 115 is attached is a first inward-facing example. The side of the first module substrate 111 opposite to the first inward side is an example of the first outward side. The side of the second module substrate 112 to which the module assembly is attached is a second inward facing example. The side of the second module substrate 112 opposite the second inward side is an example of the second outward side. In addition, FIG. 2M illustrates an example where the module assemblies 115 are located in the same plane or coplanar. Fig. 2M further shows an example in which the embedded module 11 does not contain any spacers.

Fig. 2N shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2N, a module encapsulant 114 may be provided. A module encapsulant 114 may be disposed between the first module substrate 111 and the second module substrate 112. The module encapsulant 114 may encapsulate or surround the module interconnects 113 and the module assemblies 115. The module encapsulant 114 may contact sides of the module assembly 115. In some examples, the module encapsulant 114 may contact the conductive structures 1111 and the dielectric structures 1112 of the first module substrate 111, and the conductive structures 1121 and the dielectric structures 1122 of the second module substrate 112. In some examples, the module encapsulant 114 may include or be referred to as a resin, a polymer with filler, a molding compound, a protective material, or a molding material. In some examples, the module encapsulant 114 may be provided by a film-assisted molding process, a compression molding process, or a transfer molding process. In some examples, the thickness of the module encapsulant 114 may be in the range of about 150 μm to about 300 μm. In some examples, the module encapsulant 114 may protect the module interconnects 113 and the module assemblies 115 from exposure to external factors or environments. In some examples, the module encapsulant 114 may be part of the device encapsulant 15 (fig. 1).

In some examples, the first module substrate 111, the second module substrate 112, the module interconnects 113, the module encapsulant 114, and the module assembly 115 may be referred to as an embedded module 11. In some examples, the embedded module 11 may include or be referred to as a power module or an embedded power module. In some examples, the height of the embedded module 11 may be in the range of about 350 μm to about 800 μm. The combined height of the first module substrate 111, the second module substrate 112, and the module assembly 115 (or the module encapsulant 114) may define the height of the embedded module 11. As shown in fig. 2N, the module encapsulant 114 is located over the module assembly 115, the first inward side of the first module substrate 111, and the second inward side of the second module substrate 112. Further, the first outward side of the first module substrate 111 and the second outward side of the second module substrate 112 may be exposed from the module encapsulant 114. In some examples, the outward facing sides of the first module substrate 111 and the second module substrate 112 are free of the module encapsulant 114.

Fig. 2O shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2O, a device substrate 12 may be provided. In some examples, the device substrate 12 may include or be referred to as a directly bonded copper substrate, a directly electroplated copper substrate, a heat sink substrate, a ceramic substrate, or an Active Metal Braze (AMB). The device substrate 12 may support the embedded module 11 and the device substrate 13 (fig. 1). In some examples, the device substrate 12 may transfer or dissipate heat generated by the embedded module 11 from the embedded module 11 to a lower portion of the electronic device 10. In some examples, the height of the device substrate 12 may be in the range of about 650 μm to about 2000 μm. The area (or footprint) of the device substrate 12 may be greater than the area (or footprint) of the embedded module 11. The device substrate 12 may include an inward metal layer 121, an outward metal layer 122, and a core layer 123.

The inward metal layer 121 may include or be referred to as a metal plane, metal path, lead, terminal, pad, or trace. The inward metal layer 121 may include a metal such as aluminum, palladium, titanium, tungsten, titanium/tungsten, nickel, gold, or silver. In some examples, inward metal layer 121 includes copper. An inward metal layer 121 may be disposed on the top side of the core layer 123. In some examples, the thickness of the inward metal layer 121 may be in the range of about 200 μm to about 800 μm.

The inward metal layer 121 may be coupled to the core layer 123. In some examples, the inward metal layer 121 may be formed to cover the entire top side of the core layer 123 and then etched to remove a portion of the inward metal layer 121 and form the inward terminals 121i and traces 121t over the top side of the core layer 123. In some examples, inward terminals 121i may have plating similar to plating 1111 p. The trace 121t may extend to and contact the side of the inward terminal 121 i.

The outward metal layer 122 may include or be referred to as a metal plane, metal path, lead, terminal, pad, or trace. The outward metal layer 122 may include a metal such as aluminum, palladium, titanium, tungsten, titanium/tungsten, nickel, gold, or silver. In some examples, outward metal layer 122 includes copper. An outward metal layer 122 may be disposed on the bottom side of the core layer 123. In some examples, the outward metal layer 122 may be formed to cover the entire bottom side of the core layer 123. In some examples, the outward metal layer 122 may transfer or dissipate heat generated by the embedded module 11 to a lower portion of the electronic device 10. In some examples, the thickness of the outward metal layer 122 may be in the range of about 200 μm to about 800 μm.

The core layer 123 may include or be referred to as a ceramic, thermally conductive material, or dielectric. The core layer 123 may support the inward metal layer 121 and the outward metal layer 122. In some examples, the core layer 123 may transfer heat generated by the embedded module 11 to the outward metal layer 122. In some examples, the area (or footprint) of core layer 123 may be greater than the area (or footprint) of inward metal layer 121 or the area (or footprint) of outward metal layer 122. In some examples, the thickness of the core layer 123 may be in the range of about 200 μm to about 1000 μm. In some examples, a portion of the inward metal layer 121 and a portion of the outward metal layer 122 may be coupled to each other by one or more conductive vias extending through the core layer 123.

Fig. 2P shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2P, the device terminals 14 may be disposed on the device substrate 12. In some examples, the device terminals 14 may be spaced apart from one another and may be disposed on an outer edge or perimeter of the device substrate 12. The device terminals 14 may be coupled to an inward metal layer 121 (e.g., inward terminals 121i or traces 121 t) of the device substrate 12. The device terminals 14 may protrude outward from the device substrate 12. In some examples, the device terminals 14 may be spaced apart from the embedded module 11 and may be disposed external to the embedded module 11 (fig. 2Q). In some examples, the device terminals 14 may include copper, copper alloys, nickel alloys, iron, or iron-nickel alloys. In some examples, the device terminals 14 may be coupled to the inward metal layer 121 by ultrasonic welding, soldering, or Ag sintering. In some examples, the device terminals 14 may be provided as electrical contacts between the electronic device 10 and external components. In some examples, the thickness of the device terminals 14 may be in the range of about 125 μm to about 800 μm.

Fig. 2Q shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2Q, the embedded module 11 may be provided on the device substrate 12. The embedded module 11 may be disposed inside the device terminal 14. The embedded module 11 may be coupled to a device substrate 12. The conductive structures 1111 (e.g., outward terminals 1111 o) of the first module substrate 111 may be coupled to the inward metal layer 121 (e.g., inward terminals 121 i) of the device substrate 12. The device substrate 12 may couple the embedded module 11 to the device terminals 14. For example, the inward metal layer 121 may couple the embedded module 11 to the device terminal 14. In some examples, the inward metal layer 121 may pass signals from the embedded module 11 to the device terminal 14, or may pass signals received by the device terminal 14 to the embedded module 11. In some examples, the device terminals 14 may include or may be referred to as leads, lead frames, or pins. In some examples, after being located on the device substrate 12, the embedded module 11 may be attached or bonded to the device substrate 12 by soldering or Ag sintering. In some examples, trace 121t may be located below (i.e., vertically overlapped by) dielectric structure 1112 of first module substrate 111 (e.g., trace 121t may be a portion of inward metal layer 121 that does not contact conductive structure 1111 or device terminal 14 of first module substrate 111).

Fig. 2R illustrates a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2R, the device substrate 13 may be disposed above the embedded module 11. For example, the device substrate 13 may be disposed on the second module substrate 112 of the embedded module 11. The device substrate 13 may be coupled to the embedded module 11. The device substrate 13 may be coupled to the conductive structure 1121 of the second module substrate 112. In some examples, the device substrate 13 may be located inside the device terminals 14. In some examples, the device substrate 13 may be coupled to the embedded module 11 by soldering or Ag sintering after being located on the embedded module 11.

In some examples, the device substrate 13 may include or be referred to as a directly bonded copper substrate, a directly electroplated copper substrate, a heat sink substrate, a ceramic substrate, or an AMB. In some examples, the device substrate 13 may transfer or dissipate heat generated by the embedded module 11 to a top portion of the electronic device 10. In some examples, the height of the device substrate 13 may be in the range of about 650 μm to about 2000 μm. In some examples, the area (or footprint) of the device substrate 13 may be smaller than the area (or footprint) of the device substrate 12. The device substrate 13 may include an inward metal layer 131, an outward metal layer 132, and a core layer 133.

The inward metal layer 131 may include or be referred to as a metal plane, metal path, lead, terminal, pad, or trace. The inward metal layer 131 may include a metal such as aluminum, palladium, titanium, tungsten, titanium/tungsten, nickel, gold, or silver. In some examples, the inward metal layer comprises copper. The inward metal layer 131 may be disposed on the bottom side of the core layer 133. In some examples, the inward metal layer 131 may be coupled to the conductive structure 1121 (e.g., outward terminal 1121 o) of the second module substrate 112. In some examples, the thickness of the inward metal layer 131 may be in the range of about 200 μm to about 800 μm.

In some examples, the inward metal layer 131 may be formed by covering the entire bottom side of the core layer 133, and then etching or removing a portion of the inward metal layer 131 to form the inward terminals 131i and traces 131t over the bottom side of the core layer 133. The inward terminal 131i may be coupled to the outward terminal 1121o of the second module substrate 112. In some examples, the inward terminal 131i may have a plating similar to the plating 1121 p. Trace 131t may extend to and contact the side of inward terminal 131 i. In some examples, trace 131t may be located on dielectric structure 1122 of second module substrate 112 (e.g., trace 131t may be a portion of inward metal layer 131 that does not contact conductive structure 1121 of second module substrate 112).

In some examples, the outward metal layer 132 may include or be referred to as a metal plane, metal path, lead, terminal, pad, or trace. The outward metal layer 132 may include a metal such as aluminum, palladium, titanium, tungsten, titanium/tungsten, nickel, gold, or silver. In some examples, outward metal layer 132 includes copper. An outward metal layer 132 may be disposed on the top side of the core layer 133. In some examples, the outward metal layer 132 may cover the entire top side of the core layer 133. In some examples, the outward metal layer 132 may transfer or dissipate heat generated from the embedded module 11 to a top portion of the electronic device 10. In some examples, the thickness of the outward metal layer 132 may be in the range of about 200 μm to about 800 μm.

In some examples, core layer 133 may include or be referred to as a ceramic, thermally conductive material, or dielectric. The core layer 133 may support the inward metal layer 131 and the outward metal layer 132. In some examples, the core layer 133 may transfer heat generated by the embedded module 11 to the outward metal layer 132. In some examples, the area (or footprint) of the core layer 133 may be greater than the area (or footprint) of the inward metal layer 131 or the outward metal layer 132. In some examples, the thickness of the core layer 133 may be in the range of about 250 μm to about 1000 μm. In various examples, a portion of the inward metal layer 131 and a portion of the outward metal layer 132 may be coupled to one another by one or more conductive vias extending through the core layer 133.

Fig. 2S shows a cross-sectional view of the electronic device 10 at a later stage of fabrication. In the example shown in fig. 2S, a device encapsulant 15 may be provided. The device encapsulant 15 may encapsulate the embedded modules 11, the device substrates 12 and 13, and the device terminals 14. Portions of the device terminals 14 may extend or be exposed from the device encapsulant 15. For example, the device terminals 14 may protrude outward from the device encapsulant 15. The outward metal layer 122 of the device substrate 12 and the outward metal layer 132 of the device substrate 13 may be exposed from the device encapsulant 15. In some examples, the top side of the device encapsulant 15 may be coplanar with the outward metal layer 132, and the bottom side of the device encapsulant 15 may be coplanar with the outward metal layer 122.

In some examples, the device encapsulant 15 may include or be referred to as a resin, a polymer with a filler, a molding compound, a protective material, or a molding material. In some examples, the device encapsulant 15 may be provided by a film-assisted molding process, a compression molding process, or a transfer molding process. In some examples, the height (or thickness) of the device encapsulant 15 may be in the range of about 1650 μm to about 4800 μm. The height of the device encapsulant 15 may be defined as the height of the electronic device 10. In some examples, the device encapsulant 15 may protect the embedded module 11 from exposure to external factors or environments.

Fig. 3 illustrates a cross-sectional view of an example electronic device 20. In the example shown in fig. 3, the electronic device 20 may include an embedded module 11, a device substrate 12, a device substrate 23, device terminals 14, and a device encapsulant 15. According to various examples, electronic device 20 may include elements, features, materials, or formation processes similar to those of electronic device 10 as previously described.

The device substrate 23 may include an outward metal layer 132 and a core layer 133. The core layer 133 may be coupled to or may contact the second module substrate 112 of the embedded module 11. In some examples, the core layer 133 may be coupled to the conductive structure 1121 (e.g., the outward terminals 1121 o) of the second module substrate 112. In some examples, the core layer 133 may contact the plating 1121p. The core layer 133 may transfer heat generated by the embedded module 11 to the outward metal layer 132. In some examples, the thickness of the device substrate 23 may be in the range of about 450 μm to about 1500 μm. In some examples, device substrate 23 may include elements, features, materials, or formation processes similar to or identical to elements, features, materials, or formation processes of device substrate 13 as previously described.

Fig. 4 illustrates a cross-sectional view of an example electronic device 30. In the example shown in fig. 4, the electronic device 30 may include an embedded module 11, device substrates 12 and 13, device terminals 14-1, and a device encapsulant 15. According to various examples, the elements, features, materials, or forming processes of electronic device 30 may be similar or identical to the elements, features, materials, or forming processes of electronic device 10 as previously described.

The device substrate 13 may extend (or enlarge) beyond the embedded module 11 to contact or cover portions of the device terminals 14-1. In some examples, the area (or footprint) of the device substrate 13 may be equal to or about equal to the area (or footprint) of the device substrate 12. The device substrate 13 may be coupled to the embedded module 11 and the device terminal 14-1. In some example macros, the device substrate 13 may couple the embedded module 11 to the device terminal 14-1.

The inward metal layer 131 may couple the embedded module 11 to the device terminal 14-1. In some examples, a portion of the inward metal layer 131 that may be positioned proximate to an edge or perimeter of the device substrate 13 may be coupled to the device terminal 14-1. The inward metal layer 131 may transfer signals from the embedded module 11 to the device terminal 14-1 or transfer signals received by the device terminal 14-1 to the embedded module 11.

The device terminal 14-1 may be coupled to the device substrate 12 and the device substrate 13. In some examples, device terminals 14-1 may be spaced apart from each other and may be coupled to edges of device substrates 12 and 13. In some examples, device terminals 14-1 may include terminals coupled to device substrate 12 and terminals coupled to device substrate 13. In some examples, the terminals coupled to the device substrate 12 may be planar, and the terminal-coupled device substrate 13 may be curved or convex relative to the terminals coupled to the device substrate 12. In some examples, the upper sides of the terminals coupled to the device substrate 13 may be coplanar with the top side of the embedded module 11. The device terminals 14-1 may comprise terminals protruding outwardly from the device encapsulant 15. In some examples, the terminals protruding outward from the device encapsulant 15 may be planar. In some examples, device terminal 14-1 may receive a signal from embedded module 11 through device substrate 12 or device substrate 13. In some examples, the elements, features, materials, or formation processes of device terminal 14-1 may be similar to or the same as the elements, features, materials, or formation processes of device terminal 14 as previously described.

Fig. 5 illustrates a cross-sectional view of an example electronic device 40. In the example shown in fig. 5, the electronic device 40 may include an embedded module 11, device substrates 12 and 23, device terminals 14-1, and a device encapsulant 15. In some examples, the elements, features, materials, or formation processes of electronic device 40 may be similar to or the same as elements, features, materials, or formation processes of electronic device 10, electronic device 20, or electronic device 30 as previously described.

The device substrate 23 may extend (or enlarge) beyond the embedded module 11 to contact or cover portions of the device terminals 14-1. The device substrate 23 may include an outward metal layer 132 and a core layer 133. The core layer 133 may contact the second module substrate 112 and the device terminal 14-1 of the embedded module 11. In some examples, the core layer 133 may be coupled to the conductive structure 1121 (e.g., outward terminal 1121 o) and the device terminal 14-1 of the second module substrate 112.

Fig. 6 illustrates a cross-sectional view of an example electronic device 50. In the example shown in fig. 6, the electronic device 50 may include an embedded module 21, device substrates 12 and 13, device terminals 14, and device encapsulant 25. In some examples, the elements, features, materials, or formation processes of electronic device 50 may be similar to or the same as the elements, features, materials, or formation processes of electronic device 10 as previously described.

The embedded module 21 may include a first module substrate 111, module interconnects 113, and a module assembly 115.

Fig. 7A-7D illustrate cross-sectional views of an example method for manufacturing an example electronic device 50.

Fig. 7A shows a cross-sectional view of the electronic device 50 at an early stage of manufacture. In the example shown in fig. 7A, the steps described with respect to fig. 2A to 2E may be followed, and then the module assembly 115 and the module interconnect 113 may be disposed on the first module substrate 111.

In the example shown in fig. 7A, the module interconnect 113 may be disposed on the first module substrate 111. The module interconnects 113 may be disposed externally or laterally about the module assembly 115. The module interconnect 113 may be coupled to an inward terminal 1111i. In some examples, module assemblies 115 and module interconnects 113 may be attached to plating 1111p of inward terminals 1111i by an interface material. For example, an interface material may be provided to plating 1111p, and module assemblies 115 and module interconnects 113 may be located on the interface material to allow module assemblies 115 and module interconnects 113 to be coupled to plating 1111p by a reflow process. In some examples, the first module substrate 111, the module interconnect 113, and the module assembly 115 may be referred to as an embedded module 21. In some examples, the embedded module 21 may be free of encapsulant. For example, the module assemblies 115 and module interconnects 113 disposed on the first module substrate 111 may be exposed (or unencapsulated). According to various examples, the elements, features, materials, or forming processes of the embedded module 21 may be similar or identical to the elements, features, materials, or forming processes of the embedded module 11 as previously described.

Fig. 7B shows a cross-sectional view of the electronic device 50 at a later stage of fabrication. In the example shown in fig. 7B, the device terminals 14 and the embedded module 21 may be provided on the device substrate 12. In some examples, embedded module 21 may be disposed on device substrate 12 after device terminals 14 are coupled to device substrate 12.

Fig. 7C shows a cross-sectional view of the electronic device 50 at a later stage of manufacture. In the example shown in fig. 7C, the device substrate 13 may be disposed over the embedded module 21. The device substrate 13 may be coupled to a module assembly 115 and a module interconnect 113. For example, the inward metal layer 131 of the device substrate 13 may be coupled to the module interconnect 113 or the component terminal 1153 of the module component 115. In some examples, after being disposed on the embedded module 21, the device substrate 13 may be coupled to the embedded module 21 by soldering (e.g., a solder reflow process) or Ag sintering.

Fig. 7D shows a cross-sectional view of the electronic device 50 at a later stage of manufacture. In the example shown in fig. 7D, a device encapsulant 25 may be provided. The device encapsulant 25 may encapsulate the embedded modules 21, the device substrates 12 and 13, and the device terminals 14. In some examples, the device encapsulant 25 may encapsulate the first module substrate 111, the module interconnects 113, and the module assemblies 115. The device encapsulant 25 may contact the inward terminals 1111i and traces 1111t of the first module substrate 111, the module interconnects 113, and the module assemblies 115. A portion of the device terminals 14 may be exposed from and extend beyond the device encapsulant 25. In some examples, the elements, features, materials, or formation processes of the device encapsulant 25 may be similar to or the same as the elements, features, materials, or formation processes of the device encapsulant 15 as previously described.

Fig. 8 illustrates a cross-sectional view of an example electronic device 60. In the example shown in fig. 8, the electronic device 60 may include an embedded module 31, device substrates 12 and 13, device terminals 24, and device encapsulant 25. In some examples, electronic device 60 may include elements, features, materials, or formation processes similar to elements, features, materials, or formation processes of electronic device 10 or electronic device 50 as previously described.

The embedded module 31 may include a first module substrate 111, a second module substrate 112, module interconnects 113, and a module assembly 115.

Fig. 9A-9E illustrate cross-sectional views of an example method for manufacturing an example electronic device 60.

Fig. 9A shows a cross-sectional view of electronic device 60 at an early stage of manufacture. In the example shown in fig. 9A, the steps described with respect to fig. 2A-2L may be followed, and then a second module substrate 112 having module interconnects 113 coupled thereto may be disposed over the first module substrate 111 and the module assembly 115. In some examples, the first module substrate 111, the second module substrate 112, the module interconnects 113, and the module assemblies 115 may be referred to as embedded modules 31. In some examples, the elements, features, materials, or formation processes of embedded module 31 may be similar to or the same as elements, features, materials, or formation processes of embedded module 11 as previously described.

Fig. 9B shows a cross-sectional view of the electronic device 60 at a later stage of fabrication. In the example shown in fig. 9B, the device terminal 24 may be provided on the embedded module 31. In some examples, the device terminals 24 may be spaced apart from each other and may be disposed on an edge of the embedded module 31. The device terminals 24 may be coupled to the second module substrate 112 of the embedded module 31. In some examples, the device terminal 24 may be coupled to the conductive structure 1121 (e.g., the outward terminal 1121o of the conductive structure 1121). The device terminals 24 may protrude outward from the embedded module 31. In some examples, the elements, features, materials, or formation processes of device terminal 24 may be similar to or the same as the elements, features, materials, or formation processes of device terminal 14 as previously described.

Fig. 9C shows a cross-sectional view of the electronic device 60 at a later stage of manufacture. In the example shown in fig. 9C, the device substrate 13 may be disposed over the embedded module 31. The area (or footprint) of the device substrate 13 may be smaller than the area (or footprint) of the Yu Qianru module 31. The device substrate 13 may be located inside the device terminals 24. The device substrate 13 may be spaced apart from the device terminals 24. The device substrate 13 may be coupled to the conductive structure 1121 of the second module substrate 112 (e.g., the outward terminal 1121o of the conductive structure 1121).

Fig. 9D shows a cross-sectional view of electronic device 60 at a later stage of fabrication. In the example shown in fig. 9D, the device substrate 12 may be disposed under the embedded module 31. In other words, the embedded module 31, the device substrate 13, and the device terminals 24 may be disposed over the device substrate 12. The area (or footprint) of the device substrate 12 may be smaller than the area (or footprint) of the Yu Qianru module 31. The area (or footprint) of the device substrate 12 may be equal to or about equal to the area (or footprint) of the device substrate 13. The device substrate 12 may be coupled to conductive structures 1111 (e.g., outward terminals 1111o of conductive structures 1111) of the first module substrate 111.

Fig. 9E shows a cross-sectional view of the electronic device 60 at a later stage of manufacture. In the example shown in fig. 9E, a device encapsulant 25 may be provided. The device encapsulant 25 may encapsulate the embedded modules 31, the device substrates 12 and 13, and the device terminals 24. In some examples, the device encapsulant 25 may encapsulate the first module substrate 111, the second module substrate 112, the module interconnects 113, and the module assemblies 115. The device encapsulant 25 may contact inward terminals 1111i and traces 1111t of the first module substrate 111, inward terminals 1121i and traces 1121t of the second module substrate 112, module interconnects 113, and module assemblies 115. A portion of the device terminals 24 may be exposed from and extend beyond the device encapsulant 25. In some examples, the outward metal layer 122 or the outward metal layer 132 may be exposed from the device encapsulant 25.

Fig. 10 illustrates a cross-sectional view of an example electronic device 70. In the example shown in fig. 10, the electronic device 70 may include an embedded module 31, device substrates 22 and 23, device terminals 24, and device encapsulant 25. In some examples, the elements, features, materials, or formation processes of electronic device 70 may be similar to or the same as elements, features, materials, or formation processes of electronic device 20 or electronic device 60 as previously described.

The device substrate 22 may include an outward metal layer 122 and a core layer 123. The core layer 123 may contact the first module substrate 111 of the embedded module 31. In some examples, core layer 123 may be coupled to conductive structure 1111 (e.g., outward terminals 1111 o) of first module substrate 111. In some examples, core layer 123 may contact plating 1111p. The core layer 123 may transfer heat generated by the embedded module 31 to the outward metal layer 132. In some examples, the thickness of the device substrate 22 may be in the range of about 450 μm to about 1500 μm. In some examples, the elements, features, materials, or formation processes of the device substrate 22 may be similar to or the same as the elements, features, materials, or formation processes of the device substrate 12 as previously described.

The device substrate 23 may include an outward metal layer 132 and a core layer 133. The core layer 133 of the device substrate 23 may be coupled to or may contact the second module substrate 112 of the embedded module 31. In some examples, the core layer 133 may be coupled to the conductive structure 1121 (e.g., the outward terminals 1121 o) of the second module substrate 112. In some examples, the core layer 133 may contact the plating 1121p. The core layer 133 may transfer heat generated by the embedded module 31 to the outward metal layer 132. In some examples, the elements, features, materials, or formation processes of device substrate 23 may be similar to or the same as the elements, features, materials, or formation processes of device substrate 13 as previously described.

Fig. 11 illustrates a cross-sectional view of an example electronic device 80. In the example shown in fig. 11, the electronic device 80 may include an embedded module 31, device substrates 12 and 13, device terminals 24, a device encapsulant 25-1, and a device encapsulant 25-2. In some examples, the elements, features, materials, or formation processes of electronic device 80 may be similar to or the same as elements, features, materials, or formation processes of electronic device 60 as previously described.

The device encapsulant 25-1 may encapsulate the embedded modules 31, the device substrate 13, and the device terminals 24. The device terminals 24 may protrude outward from the device encapsulant 25-1. The device encapsulant 25-2 may encapsulate the device substrate 12. The top side of the device encapsulant 25-1 may be coplanar with the top side of the device substrate 13. The bottom side of the device encapsulant 25-2 may be coplanar with the bottom side of the device substrate 12. The bottom side of the device encapsulant 25-1 may contact the top side of the device encapsulant 25-2. In some examples, the elements, features, materials, or formation processes of the device encapsulants 25-1 and 25-2 may be similar or identical to the elements, features, materials, or formation processes of the device encapsulant 25 as previously described. Fig. 11 shows an example in which the device encapsulant 25-1 encapsulates the embedded module 31 and the device substrate 13, with the first module substrate 111 exposed from the device encapsulant 25-1. In addition, the second device encapsulant 25-2 may cover the portion of the first module substrate 111 exposed from the device encapsulant 25-1, as illustrated in fig. 11.

Fig. 12 illustrates a cross-sectional view of an example electronic device 90. In the example shown in fig. 12, the electronic device 90 may include an embedded module 31, device substrates 22 and 23, device terminals 24, and device encapsulants 25-1 and 25-2. In some examples, the elements, features, materials, or formation processes of electronic device 90 may be similar to or the same as elements, features, materials, or formation processes of electronic device 20, electronic device 60, electronic device 70, or electronic device 80 as previously described.

The device encapsulant 25-1 may encapsulate the embedded modules 31, the device substrate 23, and the device terminals 24. The device encapsulant 25-2 may encapsulate the device substrate 22. The top side of the device encapsulant 25-1 may be coplanar with the top side of the device substrate 23. The bottom side of the device encapsulant 25-2 may be coplanar with the bottom side of the device substrate 22.

Fig. 13 illustrates a cross-sectional view of an example electronic device 100. In the example shown in fig. 13, the electronic device 100 may include an embedded module 11, device substrates 12 and 13, device terminals 24, and a device encapsulant 15. In some examples, the elements, features, materials, or formation processes of electronic device 100 may be similar to or the same as those of electronic device 10 or electronic device 60 as previously described.

Fig. 14A-14D illustrate cross-sectional views of an example method for manufacturing an example electronic device 100.

Fig. 14A shows a cross-sectional view of the electronic device 100 at an early stage of manufacture. In the example shown in fig. 14A, the steps described with respect to fig. 2A to 2N may be followed, and then the device terminal 24 may be coupled to the embedded module 11.

In some examples, the device terminals 24 may be spaced apart from each other and may be disposed on an edge of the embedded module 11. The device terminals 24 may be coupled to the second module substrate 112 of the embedded module 11. In some examples, the device terminals 24 may be coupled to the conductive structures 1121 (e.g., outward terminals 1121 o) of the second module substrate 112. The device terminals 24 may protrude outward from the embedded module 11.

Fig. 14B shows a cross-sectional view of the electronic device 100 at a later stage of fabrication. In the example shown in fig. 14B, the device substrate 13 may be disposed above the embedded module 11. The area (or footprint) of the device substrate 13 may be smaller than the area (or footprint) of the Yu Qianru module 11. The device substrate 13 may be located inside the device terminals 24. The device substrate 13 may be spaced apart from the device terminals 24. The device substrate 13 may be coupled to the conductive structure 1121 (e.g., the outward terminal 1121 o) of the second module substrate 112.

Fig. 14C shows a cross-sectional view of the electronic device 100 at a later stage of fabrication. In the example shown in fig. 14C, the device substrate 12 may be disposed under the embedded module 11. In other words, the embedded module 11, the device substrate 13, and the device terminals 24 may be disposed over the device substrate 12. The area (or footprint) of the device substrate 12 may be smaller than the area (or footprint) of the Yu Qianru module 11. The area (or footprint) of the device substrate 12 may correspond to the area (or footprint) of the device substrate 13. The device substrate 12 may be coupled to the conductive structures 1111 of the first module substrate 111.

Fig. 14D shows a cross-sectional view of the electronic device 100 at a later stage of fabrication. In the example shown in fig. 14D, a device encapsulant 15 may be provided. The device encapsulant 15 may encapsulate the embedded modules 11, the device substrates 12 and 13, and the device terminals 24. The device encapsulant 15 may contact the module encapsulant 114 of the embedded module 11.

Fig. 15 illustrates a cross-sectional view of an example electronic device 110. In the example shown in fig. 15, the electronic device 110 may include an embedded module 11, device substrates 22 and 23, device terminals 24, and a device encapsulant 15. In some examples, the elements, features, materials, or formation processes of electronic device 110 may be similar to or the same as elements, features, materials, or formation processes of electronic device 10, electronic device 20, electronic device 60, or electronic device 70 as previously described.

The core layer 123 of the device substrate 22 may be coupled to or may contact the first module substrate 111 of the embedded module 11. The core layer 123 may transfer heat generated by the embedded module 11 to the outward metal layer 122.

The core layer 133 of the device substrate 23 may be coupled to or may contact the second module substrate 112 of the embedded module 11. The core layer 133 may transfer heat generated by the embedded module 11 to the outward metal layer 132.

Fig. 16 illustrates a cross-sectional view of an example electronic device 120. In the example shown in fig. 16, the electronic device 120 may include an embedded module 11, device substrates 12 and 13, device terminals 24, a device encapsulant 15-1, and a device encapsulant 15-2. In some examples, the elements, features, materials, or formation processes of electronic device 120 may be similar to or the same as elements, features, materials, or formation processes of electronic device 10 or electronic device 60 as previously described.

Fig. 17A-17E illustrate cross-sectional views of an example method for manufacturing an example electronic device 120.

Fig. 17A shows a cross-sectional view of the electronic device 120 at an early stage of manufacture. In the example shown in fig. 17A, the steps described with respect to fig. 2A to 2N may be followed, and then the device terminal 24 may be provided on the embedded module 11, as described above with reference to fig. 14A.

Fig. 17B shows a cross-sectional view of the electronic device 120 at a later stage of fabrication. In the example shown in fig. 17B, the device substrate 13 may be disposed over the embedded module 11, as described above with reference to fig. 14B.

Fig. 17C shows a cross-sectional view of the electronic device 120 at a later stage of fabrication. In the example shown in fig. 17C, a device encapsulant 15-1 may be provided. The device encapsulant 15-1 may encapsulate the embedded module 11, the device substrate 13, and the device terminals 24. The device terminals 24 may protrude outward from the device encapsulant 15-1. The top side of the device encapsulant 15-1 may be coplanar with the top side of the device substrate 13. The bottom side of the device encapsulant 15-1 may be coplanar with the bottom side of the embedded module 11.

Fig. 17D shows a cross-sectional view of the electronic device 120 at a later stage of fabrication. In the example shown in fig. 17D, the device substrate 12 may be disposed under the embedded module 11. In other words, the encapsulated embedded module 11, the device substrate 13, and the device terminals 24 may be disposed over the device substrate 12.

Fig. 17E shows a cross-sectional view of the electronic device 120 at a later stage of fabrication. In the example shown in fig. 17E, a device encapsulant 15-2 may be provided. The device encapsulant 15-2 may encapsulate the device substrate 12. The bottom side of the device encapsulant 15-2 may be coplanar with the bottom side of the device substrate 12. The top side of the device encapsulant 15-2 may be in contact with the bottom side of the device encapsulant 15-1 or the bottom side of the embedded module 11.

Fig. 18 illustrates a cross-sectional view of an example electronic device 130. In the example shown in fig. 18, the electronic device 130 may include the embedded module 11, the device substrates 22 and 23, the device terminals 24, and the device encapsulants 15-1 and 15-2. In some examples, the elements, features, materials, or formation processes of electronic device 130 may be similar to or the same as the elements, features, materials, or formation processes of electronic device 10, electronic device 20, electronic device 60, electronic device 70, or electronic device 120 as previously described.

Fig. 19 illustrates a cross-sectional view of an example stacked embedded module or power module 200. In the example shown in fig. 19, stacked embedded module 200 may include a first module substrate 111, a second module substrate 112, a third module substrate 212, a first module interconnect 113, a second module interconnect 213, a first module encapsulant 114, a second module encapsulant 214, one or more first module assemblies 115, and one or more second module assemblies 215.

The first module substrate 111 may include a conductive structure 1111 and a dielectric structure 1112. Similar to the embedded module 11 shown in fig. 1, the conductive structures 1111 may include inward terminals, outward terminals, traces, or plating. The second module substrate 112 may include a conductive structure 1121 and a dielectric structure 1122. Similar to the embedded module 11 shown in fig. 1, the conductive structures 1121 may include inward terminals, outward terminals, traces, or plating. The third module substrate 212 may include a conductive structure 2121 and a dielectric structure 2122. Similar to the embedded module 11 shown in fig. 1, the conductive structures 2121 may include inward terminals, outward terminals, traces, or plating. Similar to the embedded module 11 shown in fig. 1, the first module components 115 may each include component terminals 1151, 1152, and 1153. Similar to the embedded module 11 shown in fig. 1, the second module assemblies 215 may each include assembly terminals 2151, 2152, and 2153.

Fig. 20A, 20B, 20C, and 20D illustrate cross-sectional views of an example method for manufacturing an example stacked embedded module or power module 200. Fig. 20A shows a cross-sectional view of stacked embedded module 200 at an early stage of fabrication. In some examples, the starting structure of fig. 20A may be similar to fig. 2N.

In the example shown in fig. 20A, one or more first module interconnects 113 and one or more first module assemblies 115 may be electrically coupled to the first module substrate 111, the second module substrate 112 may be electrically coupled to the one or more first module interconnects 113 or the one or more first module assemblies 115, and a first module encapsulant 114 may be filled between the first module substrate 111 and the second module substrate 112 to cover the first module interconnects 113 and the first module assemblies 115. In some examples, the first module encapsulant 114 may contact the first module substrate 111 and the second module substrate 112. In some examples, the first module encapsulant 114 may be part of the device encapsulant 15 (fig. 21). Although fig. 20A-20D illustrate the width or length of the first module substrate 111 being greater than the width or length of the second module substrate 112, it is contemplated and understood that in other examples, the width or length of the first module substrate 111 may be equal to or approximately equal to the width or length of the second module substrate 112. In some examples, the sides of the first module encapsulant 114 may be coplanar with the sides of the second module substrate 112. In some examples, the sides of the first module substrate 111 may extend outward more than the sides of the first module encapsulant 114. This process may be similar to the process shown in fig. 2A through 2N.

Fig. 20B shows a cross-sectional view of stacked embedded module 200 at a later stage of fabrication. In the example shown in fig. 20B, one or more second module assemblies 215 may be disposed on the second module substrate 112. The second module assembly 215 may be coupled to the outward terminals of the second module substrate 112. The outward terminals may provide a connection path between the second module assembly 215 and the second module substrate 112. In some examples, the second module assembly 215 may be coupled to plating on the outward terminals by an interface material. In some examples, an interface material may be provided on the plating layer, and the second module assembly 215 may be positioned on the interface material to allow the second module assembly 215 to be coupled to the plating layer by a reflow process.

In some examples, the second module assembly 215 may include assembly terminals 2151, 2152, and 2153. In some examples, the assembly terminals 2151 and 2152 may be disposed on a first side of the second module assembly 215 and the assembly terminal 2153 may be disposed on a second side of the second module assembly 215 opposite the first side of the second module assembly 215. In some examples, the component terminal 2151 may be a source, the component terminal 2152 may be a gate, and the component terminal 2153 may be a drain. The assembly terminals 2151 and 2152 can be coupled to the second module substrate 112 and can contact plated or outward terminals of the conductive structure 1121. In some examples, the component terminals 2151 and 2152 can be coupled to the inward terminals of the conductive structure 1121 by the outward terminals of the conductive structure 1121 or by the outward terminals and traces.

Fig. 20C shows a cross-sectional view of stacked embedded module 200 at a later stage of fabrication. In the example shown in fig. 20C, a third module substrate 212 having a second module interconnect 213 may be disposed on the second module substrate 112 and the second module assembly 215.

In some examples, the second module interconnect 213 may be disposed on the third module substrate 212. The second module interconnect 213 may be coupled to an inward terminal of the conductive structure 2121 of the third module substrate 212. In some examples, the second module interconnect 213 may include or be referred to as a solder ball, a solder-coated metal core (e.g., cu core) ball, a post with a solder cap, or a bump. In some examples, the second module interconnect 213 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), sn-Pb, sn37-Pb, sn95-Pb, sn-Pb-Ag, sn-Cu, sn-Ag, sn-Au, sn-Bi, or Sn-Ag-Cu. In some examples, the second module interconnect 213 may be provided by a reflow process after the conductive material including solder is disposed on the plating of the inward terminals of the third module substrate 212. In some examples, the thickness of the second module interconnect 213 may be in the range of about 150 μm to about 365 μm.

In some examples, the third module substrate 212 may be located above the second module assembly 215 such that the inward terminals of the third module substrate 212 are oriented toward the second module assembly 215 and the second module substrate 112, and the outward terminals of the third module substrate 212 are located on the top side of the third module substrate 212. In some examples, after positioning third module substrate 212 on second module substrate 112 and second module assembly 215, third module substrate 212 may be coupled to second module substrate 112 and second module assembly 215 by, for example, thermocompression bonding. The second module interconnect 213 may couple the third module substrate 212 to the second module substrate 112. In some examples, the second module interconnect 213 may be coupled to an outward terminal or trace of the second module substrate 112. The second module assembly 215 may be coupled to inward terminals or traces of the third module substrate 212. In some examples, the component terminals 2153 of the second module assembly 215 may be coupled to inward terminals or traces of the third module substrate 212.

The side of the second module substrate 112 to which the second module assembly 215 is attached may be a second outward facing example. The side of the second module substrate 112 opposite the second outward side may be an example of the second inward side. The side of the third module substrate 212 to which the second module assembly 215 is attached is an example of a third direction inside. The side of the third module substrate 212 opposite the third-direction inside is an example of the third-direction outside.

In some examples, the second module interconnect 213 may be disposed first on and coupled with the outward terminals of the second module substrate 112, and then the third module substrate 212 may be disposed over the second module interconnect 213 and the second module assembly 215. In some examples, the third module substrate 212 may be electrically coupled to the one or more second module interconnects 213 and the one or more second module assemblies 215.

Fig. 20D shows a cross-sectional view of stacked embedded module 200 at a later stage of fabrication. In the example shown in fig. 20D, a second module encapsulant 214 may be provided. The second module encapsulant 214 may be disposed between the second module substrate 112 and the third module substrate 212. The second module encapsulant 214 may encapsulate, surround, or cover the second module interconnect 213 and the second module assembly 215. The second module encapsulant 214 may contact sides of the second module interconnects 213 and sides of the second module assembly 215. In some examples, the second module encapsulant 214 may contact the conductive structure 1121 and the dielectric structure 1122 of the second module substrate 112, and the conductive structure 2121 and the dielectric structure 2122 of the third module substrate 212. In some examples, the second module encapsulant 214 may include or be referred to as a resin, a polymer with filler, a molding compound, a protective material, or a molding material. In some examples, the second module encapsulant 214 may be provided by a film-assisted molding process, a compression molding process, or a transfer molding process. In some examples, the thickness of the second module encapsulant 214 may be in the range of about 150 μm to about 300 μm. In some examples, the second module encapsulant 214 may cover a side of the third module substrate 212. In other examples, the sides of the second module encapsulant 214 and the sides of the third module substrate 212 may be coplanar. The second module encapsulant 214 may protect the second module interconnect 213 and the second module assembly 215 from exposure to external factors or environments. In some examples, the second module encapsulant 214 may be part of the device encapsulant 15 (fig. 21).

Fig. 20E shows a cross-sectional view of stacked embedded module 200 at a later stage of fabrication. In the example shown in fig. 20E, stacked embedded modules 200 may be singulated or sawed. In some examples, the singulation process or sawing process may be performed by a diamond impeller or a laser beam.

In some examples, the second module encapsulant 214, the second module substrate 112, the first module encapsulant 114, and the first module substrate 111 may be sequentially singulated or sawed. In some examples, the sides of the second module encapsulant 214, the second module substrate 112, the first module encapsulant 114, and the first module substrate 111 may be coplanar.

In some examples, the third module substrate 212, the second module encapsulant 214, the second module substrate 112, the first module encapsulant 114, and the first module substrate 111 may be sequentially singulated or sawed, and sides of each of the third module substrate 212, the second module encapsulant 214, the second module substrate 112, the first module encapsulant 114, and the first module substrate 111 may be coplanar.

In some examples, the second module assembly 215 may be electrically coupled to the first module substrate 111 such that in the final stacked embedded module, the first module substrate 111 is positioned between the second module substrate 112 and the third module substrate 212, and the second module interconnect 213 electrically couples the third module substrate 212 to the first module substrate 111, and the second module encapsulant 214 is disposed between the first module substrate 111 and the third module substrate 212 (e.g., the first module substrate 111 is positioned between the first module encapsulant 114 and the second module encapsulant 214). In some examples, the component terminals 2153 of the second module assembly 215 may be coupled to outward terminals, traces, or plating of the second module substrate 112, and the component terminals 2151 and 2152 may be coupled to inward terminals, traces, or plating of the third module substrate 212 (e.g., the second module assembly 215 may be flipped 180 ° relative to the orientation of the second module assembly 215 shown in fig. 20B-20E).

Fig. 21 illustrates a cross-sectional view of an example electronic device 300. In the example shown in fig. 21, the electronic device 300 may include a stacked embedded module 200, a device substrate 12, device terminals 14, and a device encapsulant 15. According to various examples, an element, feature, material, or formation process of the electronic device 300 may be similar to or the same as an element, feature, material, or formation process of the electronic device 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, or 130 as previously described.

A portion of the device substrate 12 may be exposed from the device encapsulant 15. In some examples, the bottom side of the device substrate 12 may be exposed from the device encapsulant 15. In some examples, the outward metal layer 122 of the device substrate 12 may be exposed from the device encapsulant 15. In some examples, the bottom side of the outward metal layer 122 may be coplanar with the bottom side of the device encapsulant 15.

A portion of the stacked embedded module 200 may be exposed from the device encapsulant 15. In some examples, the bottom side of the third module substrate 212 may be exposed from the device encapsulant 15. In some examples, the top side of the third module substrate 212 and the top side of the device encapsulant 15 may be coplanar. In some examples, the outward terminals, traces, or plating of the third module substrate 212 may be exposed.

Fig. 22 illustrates a cross-sectional view of an example electronic device 400. In the example shown in fig. 22, the electronic device 400 may include a stacked embedded module 200, a device substrate 12, a device substrate 13, a device terminal 14, and a device encapsulant 15. According to various examples, an element, feature, material, or formation process of the electronic device 400 may be similar to or the same as an element, feature, material, or formation process of the electronic device 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, or 300 as previously described.

The device substrate 13 may be located above or protrude from the device encapsulant 15. In some examples, the device substrate 13 may be positioned higher than the device encapsulant 15. For example, the bottom side of the inward metal layer 131 may be coplanar with the top side of the device encapsulant 15. In some examples, sides of each of the inward metal layer 131, the core layer 133, and the outward metal layer 132 may be exposed. In some examples, a top side of the outward metal layer 132 may be exposed.

Fig. 23 illustrates a cross-sectional view of an example electronic device 500. In the example shown in fig. 23, the electronic device 500 may include a stacked embedded module 200, a device substrate 12, a device substrate 13, a device terminal 14, and a device encapsulant 15. According to various examples, an element, feature, material, or formation process of the electronic device 500 may be similar to or the same as an element, feature, material, or formation process of the electronic device 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 300, or 400 as previously described.

In some examples, the device substrate 13 may be positioned in the device encapsulant 15. For example, the device encapsulant 15 may cover or contact the sides of the inward metal layer 131, the outward metal layer 132, or the core layer 133. In some examples, a portion of the device substrate 13 may be exposed from the device encapsulant 15. For example, the top side of the device substrate 13 may be exposed from the device encapsulant 15. In some examples, the outward metal layer 132 of the device substrate 13 may be exposed from the device encapsulant 15. In some examples, the top side of the outward metal layer 132 may be coplanar with the top side of the device encapsulant 15.

Fig. 24 illustrates a cross-sectional view of an example electronic device 600. In the example shown in fig. 24, the electronic device 600 may include a first embedded module 11, a second embedded module 11', a device substrate 12, a device terminal 14, and a device encapsulant 15. According to various examples, an element, feature, material, or formation process of the electronic device 600 may be similar to or the same as an element, feature, material, or formation process of the electronic device 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 300, 400, or 500 as previously described.

The elements, features, materials, or formation processes of the first embedded module 11 may be similar or identical to the elements, features, materials, or formation processes of the embedded module 11 shown in fig. 2N. The elements, features, materials, or formation processes of the second embedded module 11' may be similar or identical to the elements, features, materials, or formation processes of the embedded module 11 shown in fig. 2N. In some examples, the second embedded module 11 'may include a first module substrate 111', a second module substrate 112', one or more module interconnects 113', a module encapsulant 114', and one or more module assemblies 115'. Similar to the embedded module 11 shown in fig. 1, one or more module assemblies 115 'may each include assembly terminals 1151', 1152', and 1153'. In some examples, the first module substrate 111 'may be referred to as a third module substrate and the second module substrate 112' may be referred to as a fourth module substrate.

The first module substrate 111' may include a conductive structure 1111' and a dielectric structure 1112'. Similar to the conductive structures 1111 of the first module substrate 111, the conductive structures 1111' may include inward terminals, outward terminals, traces, and plating. The second module substrate 112' may include a conductive structure 1121' and a dielectric structure 1122'. Similar to the conductive structure 1121 of the second module substrate 112, the conductive structure 1121' may include inward terminals, outward terminals, traces, and plating.

In some examples, the second module substrate 112 of the first embedded module 11 may be electrically coupled to the first module substrate 111 'of the second embedded module 11'. In some examples, the outward terminals, traces, or plating of conductive structure 1121 may be electrically coupled to the outward terminals, traces, or plating of conductive structure 1111'.

In some examples, the first embedded module 11 may be coupled to the second embedded module 11' through the interface material 601. In some examples, the interface material 601 may include or be referred to as a conductive adhesive, conductive epoxy, solder paste, ag sintering paste, or Anisotropic Conductive Film (ACF). In some examples, there may be a gap between the first embedded module 11 and the second embedded module 11' of the thickness of the interface material 601. In some examples, the device encapsulant 15 may be located in the gap.

In the example of fig. 24, at least a first pair of opposing sides of the first embedded module 11 and at least a first pair of opposing sides of the second embedded module 11 'may have different horizontal positions (e.g., the second embedded module 11' may be laterally offset from the first embedded module 11). For example, a first (e.g., left) side of the second embedded module 11 'may be positioned farther from a first (e.g., left) side of the device encapsulant 15 than a first (e.g., left) side of the first embedded module 11, or a second (e.g., right) side of the second embedded module 11' may be positioned closer to a second (e.g., right) side of the device encapsulant 15 than a second (e.g., right) side of the first embedded module 11. The second pair of opposing sides of the first embedded module 11 (e.g., the sides connecting the first pair of opposing sides) may be laterally offset or coplanar with the second pair of opposing sides of the second embedded module 11'.

A portion of the second embedded module 11' may be exposed from the device encapsulant 15. In some examples, the bottom side of the second module substrate 112' may be exposed from the device encapsulant 15. In some examples, the top side of the second module substrate 112' and the top side of the device encapsulant 15 may be coplanar. In some examples, the outward terminals, traces, or plating of the conductive structures 1121 'of the second module substrate 112' may be exposed.

Fig. 25 illustrates a cross-sectional view of an example electronic device 610. In the example shown in fig. 25, the electronic device 610 may include a first embedded module 11, a second embedded module 11', a device substrate 12, a device substrate 13, a device terminal 14, and a device encapsulant 15. According to various examples, elements, features, materials, or formation processes of electronic device 610 may be similar to or identical to elements, features, materials, or formation processes of electronic device 400 or electronic device 600 as previously described.

Fig. 26 illustrates a cross-sectional view of an example electronic device 650. In the example shown in fig. 26, the electronic device 650 may include the first embedded module 11, the second embedded module 11', the device substrate 12, the device substrate 13, the device terminals 14, and the device encapsulant 15. According to various examples, the elements, features, materials, or formation processes of electronic device 650 may be similar to or identical to the elements, features, materials, or formation processes of electronic device 10, electronic device 500, or electronic device 600 as previously described.

In some examples, the device substrate 13 may be located in the device encapsulant 15. For example, the device encapsulant 15 may cover or contact the sides of the inward metal layer 131, the outward metal layer 132, or the core layer 133. In some examples, a portion of the device substrate 13 may be exposed from the device encapsulant 15. In some examples, the top side of the device substrate 13 may be exposed from the device encapsulant 15. In some examples, the outward metal layer 132 of the device substrate 13 may be exposed from the device encapsulant 15. In some examples, the top side of the outward metal layer 132 may be coplanar with the top side of the device encapsulant 15.

Fig. 27 illustrates a cross-sectional view of an example electronic device 700. In the example shown in fig. 27, the electronic device 700 may include a first embedded module 11, a second embedded module 11', a device substrate 12, a device substrate 13, a device terminal 24, and a device encapsulant 15. According to various examples, an element, feature, material, or formation process of the electronic device 650 may be similar to or the same as an element, feature, material, or formation process of the electronic device 50, 60, 70, 80, 90, 100, 110, 120, 130, 300, or 600 as previously described.

In some examples, the device terminal 24 is interposed between the first embedded module 11 and the second embedded module 11'. In some examples, the bottom side of the device terminal 24 may be coupled to the top side of the first embedded module 11. For example, the device terminals 24 may be coupled to the second module substrate 112 (e.g., to the outward terminals or plating of the conductive structures 1121). In some examples, the top side of the device terminal 24 may be coupled to the bottom side of the second embedded module 11'. For example, the device terminals 24 may be coupled to a first module substrate 111' (e.g., to an outward terminal or plating of the conductive structure 1111 ') of the second embedded module 11 '.

Fig. 28 illustrates a cross-sectional view of an example electronic device 710. In the example shown in fig. 28, the electronic device 710 may include the first embedded module 11, the second embedded module 11', the device substrate 12, the device substrate 13, the device terminals 24, and the device encapsulant 15. According to various examples, elements, features, materials, or formation processes of electronic device 710 may be similar to or identical to elements, features, materials, or formation processes of electronic device electronic devices 400, 610, or 700 as previously described.

Fig. 29 illustrates a cross-sectional view of an example electronic device 750. In the example shown in fig. 29, the electronic device 750 may include a first embedded module 11, a second embedded module 11', a device substrate 12, a device substrate 13, a device terminal 24, and a device encapsulant 15. According to various examples, elements, features, materials, or formation processes of electronic device 750 may be similar to or the same as elements, features, materials, or formation processes of electronic device 500, 650, or 700 as previously described.

Fig. 30A, 30B, and 30C illustrate an example electronic device 10'. In the example shown in fig. 30A, 30B, and 30C, the electronic device 10' may include one or more embedded modules 11A ", one or more embedded modules 11B", a first device substrate 12", a second device substrate 13", one or more device terminals 24", one or more device terminals 241", and a device encapsulant 15". The first device substrate 12 "may include an inward metal layer 121", an outward metal layer 122", and a core layer 123". The second device substrate 13 "may include an inward metal layer 131", an outward metal layer 132", and a core layer 133".

In some examples, the embedded modules 11A ", 11B" may be horizontally spaced apart from each other (e.g., arranged in rows and columns). In some examples, a portion of the device encapsulant 15 "may be interposed between the embedded modules 11" a, 11B ". In some examples, embedded modules 11A ", 11B" may be located between device substrate 12 "and device substrate 13". The embedded modules 11A ", 11B" may be coupled to the device substrate 12 "and the second device substrate 13". In some examples, device terminals 24 "and 241" may be located between device substrate 12 "and second device substrate 13'. The device terminals 24 "may be laterally or vertically spaced apart from each other. The device terminals 241 "may be laterally or vertically spaced apart from each other. Device terminals 24 "and 241" may be coupled to device substrate 12 "or device substrate 13".

In the example shown in fig. 30A, 30B, 30C, 35A, and 35B, the embedded module 11A "and the embedded module 11B" may each be disposed generally in a straight line between a first pair of opposing sides of the device encapsulant 15 ". The embedded module 11A "may be positioned proximate to a first side of the device encapsulant 15", the device substrate 12", or the device substrate 13", and the embedded module 11B "may be positioned proximate to a second, opposite side of the device encapsulant 15", the device substrate 12", or the device substrate 13".

The embedded module 11A "may be oriented such that the component terminals 1151" and 1152 "and the first module substrate 111" face the first device substrate 12 "and the component terminal 1153" and the second module substrate 112 "face the second device substrate 13". The embedded module 11B "may be oriented such that the component terminals 1151" and 1152 "and the first module substrate 111" face the device substrate 13 "and the component terminal 1153" and the second module substrate 112 "face the device substrate 12".

As shown in fig. 30B, 30C, 35A, and 35B, the embedded module 11A "may be oriented such that the first module substrate 111" is coupled to or contacts the inward metal layer 121 "of the device substrate 12" and the second module substrate 112 "is coupled to or contacts the inward metal layer 131" of the device substrate 13". The embedded module 11B "may be oriented such that the first module substrate 111" is coupled to or contacts the inward metal layer 131 "of the device substrate 13" and the second module substrate 112 "is coupled to or contacts the inward metal layer 121" of the device substrate 12".

Fig. 31A and 31B show cross-sectional views of an example embedded module 11 ". The embedded module 11 "may be identical to the embedded module 11A" and the embedded module 11B ". The embedded module 11 "may include a first module substrate 111", a second module substrate 112", one or more module interconnects 113", a module encapsulant 114", and one or more module assemblies 115". The first module substrate 111 "may include a conductive structure 1111" and a dielectric structure 1112". The second module substrate 112 "may include a conductive structure 1121" and a dielectric structure 1122". The module interconnect 113 "may include a metal core ball 113i and a solder coating 113o. In some examples, the module encapsulant 114 "may be part of the device encapsulant 15". According to various embodiments, module assemblies 115 "may each include assembly terminals 1151", 1152", 1153". In some examples, component terminal 1151 "may include or be referred to as a source, source electrode, or source terminal. In some examples, component terminal 1152 "may include or be referred to as a gate, gate electrode, or gate terminal. In some examples, component terminal 1153 "may include or be referred to as a drain, drain electrode, or drain terminal. According to various examples, the elements, features, materials, or forming processes of the embedded module 11 "may be similar to or the same as the elements, features, materials, or forming processes of the embedded module 11 as previously described.

In some embodiments, the embedded module 11 "may include a first module component 115" and a second module component 115". In some examples, the gate terminal 1152 "of each of the first module assembly 115" and the second module assembly 115 "may be coupled to the same inward terminal of the conductive structure 1111" (e.g., to the gate of the gate portion 1111", as shown in fig. 32A and 33A). In some examples, the source terminal 1151 "of each of the first module assembly 115" and the second module assembly 115 "may be coupled to the same inward terminal of the conductive structure 1111" (e.g., to the source portion 1111' _{Source electrode} As shown in fig. 32A and 33A). In some examples, the drain terminal 1153 "of each of the first module assembly 115" and the second module assembly 115 "may be coupled to the same inward terminal of the conductive structure 1121" (e.g., to the drain portion 1121 "; _{drain electrode} As shown in fig. 32B and 33B).

Fig. 32A shows a plan view of an example pattern of conductive structures 1111 "and dielectric structures 1112" of a first module substrate 111 ". Fig. 33A shows a plan view of the module assembly 115 "coupled to the first module substrate 111". In some examples, source terminal 1151 "of module component 115" may be coupled to source portion 1111 "of conductive structure 1111" _{Source electrode} . In some examples, the gate terminal 1152 "of the module assembly 115" may be coupled to the gate portion 1111 "of the conductive structure 1111" _{Grid electrode} . Source portion 1111' _{Source electrode} And gate portion 1111' _{Grid electrode} May each include an inward terminal of conductive structure 1111 ".

Fig. 32B shows a plan view of an example pattern of conductive structures 1121 "and dielectric structures 1122" of a second module substrate 112 "with module interconnects 113" coupled to the conductive junctionsConstruct 1121). Fig. 33B shows a plan view of the module assembly 115 "coupled to the second module substrate 112". In some examples, the drain terminal 1153 "of the module assembly 115" may be coupled to the drain portion 1121 "of the conductive structure 1121"; _{drain electrode} . The module interconnect 113 "may be coupled to the source portion 1121" of the conductive structure 1121 "of the second module substrate 112" _{Source electrode} Source portion 1111 "of conductive structure 1111" of first module substrate 111" _{Source electrode} Between them. The module interconnect 113 "may be coupled to the gate portion 1121" of the conductive structure 1121 "of the second module substrate 112" _{Grid electrode} Gate portion 1111 "of conductive structure 1111" with first module substrate 111" _{Grid electrode} Between them.

In some examples, the source terminal 1151 "of the module component 115" may be electrically coupled to the source portion 1121 "of the second module substrate 112" through the module interconnect 113" _{Source electrode} The module interconnect is coupled to the source portion 1111 "of the first module substrate 111" _{Source electrode} And a source portion 1121 "of a second module substrate 112" _{Source electrode} . In some examples, the gate terminal 1152 "of the module assembly 115" may be coupled to the gate portion 1121 "of the second module substrate 112" through the module interconnect 113" _{Grid electrode} The module interconnect is coupled to the gate portion 1111 "of the first module substrate 111" _{Grid electrode} And a gate portion 1121 "of a second module substrate 112" _{Grid electrode} 。

Fig. 34A shows a plan view of an example pattern of the inward metal layer 121 "of the device substrate 12". Fig. 34B shows a plan view of an example pattern of the inward metal layer 131 "of the device substrate 13". Referring to FIG. 30A, device terminal 241 "(G1) may be electrically coupled to inward metal layer 121": _{grid 1} The device terminal 241 "(S1) may be electrically coupled to the inward metal layer 121' _{Source + drain 2} The device terminal 241 "(D1) may be electrically coupled to the inward metal layer 131": _{Drain 1} The device terminal 241 "(D2) may be electrically coupled to the inward metal layer 131": _{source 1+ drain 2} The device terminal 241 "(S2) may be electrically coupled to the inward metal layer 131' _{Source electrode 2} Device terminal 241 "(G)2) May be electrically coupled to the inward metal layer 121' _{Grid 2} . In addition, in conjunction with fig. 30A above, device terminal 24 "(D1) may be electrically coupled to inward metal layer 121″. _{Drain 1} And inward metal layer 131' _{Drain 1} The device terminal 24 "(s1+d2) may be electrically coupled to the inward metal layer 121″" _{Source 1+ drain 2} And inward metal layer 131' _{Source 1+ drain 2} The device terminal 24 "(S2) may be electrically coupled to the inward metal layer 121' _{Source electrode 2} And inward metal layer 131' _{Source electrode 2} 。

Fig. 35A shows a plan view of a set of embedded modules 11A "and a set of embedded modules 11B" coupled to an inward metal layer 121 "of a first device substrate 12". The embedded module 11 "a" may include a first module substrate 111 "facing and coupled to or in contact with the first device substrate 12". For example, the conductive structure 1111 "of the embedded module 11" a "may be located between the module assembly 115" of the embedded module 11 "a" and the inward metal layer 121 "of the first device substrate 12". The embedded module 11 "b" may include a second module substrate 112 "facing and coupled to or in contact with the first device substrate 12". For example, the conductive structure 1121 "of the embedded module 11" b "may be located between the module assembly 115" of the embedded module 11 "b" and the inward metal layer 121 "of the first device substrate 12".

Fig. 35B shows a plan view of a set of embedded modules 11A "and a set of embedded modules 11B" coupled to an inward metal layer 131 "of a second device substrate 13". The embedded module 11A "may include a second module substrate 112" facing and coupled to or in contact with the second device substrate 12". For example, the conductive structure 1121 "of the embedded module 11A" may be located between the module assembly 115 "of the embedded module 11A" and the inward metal layer 131 "of the second device substrate 13". The embedded module 11B "may include a first module substrate 111" facing and coupled to or in contact with the second device substrate 13 ". For example, the conductive structure 1111 "of the embedded module 11B" may be located between the module assembly 115 "of the embedded module 11B" and the inward metal layer 131 "of the second device substrate 13".

The electronic device 10 'and the embedded module 11 "may allow the embedded module 11" to be tested prior to assembling the electronic device 10'. The device substrates 12 "and 13" may allow for double sided heat dissipation of the electronic device 10'. The electronic device 10' may allow for reduced height/thickness and may be free of through wires (e.g., wirebonded semiconductor die or other electronic components). The electronic device 10' may also be free of spacers. The electronic device 10' and the embedded modules 11 "may allow for convenient customization of any number of embedded modules 11" within the package.

From all of the foregoing, one skilled in the art can determine that, according to an example, an electronic device can include a module interconnect coupled to a first module substrate and to a second module substrate. In an example, the device terminal may be coupled to a first device substrate and a second device substrate. In an example, the first device substrate may include a first inward metal layer, and the device terminal may be coupled to the first inward metal layer of the first device substrate. In an example, the width of the first embedded module may be greater than the width of the second device substrate, and the first device substrate may further include a first inward metal layer coupled to the first module substrate and the first core layer disposed between the first inward metal layer and the first outward metal layer. In one example, the first outward metal layer may be exposed from the encapsulant structure. In an example, the second outward metal layer includes a portion of the second device substrate exposed from the encapsulant structure.

From all of the foregoing, one skilled in the art can determine that, in one example, an electronic device can include a plurality of embedded modules. The device terminals may include a first device terminal, a second device terminal, a third device terminal, a fourth device terminal, a fifth device terminal, a sixth device terminal, a seventh device terminal, an eighth device terminal, and a ninth device terminal. The first inward metal layer may comprise a first inward first gate layer (121', _{Grid 1} ) A first inward second gate layer (121', _{grid 2} ) A first inward first drain layer (121' _{Drain 1} ) First inward first source and second drain layers (121', _{source 1+ drain 2} ) A second source electrode layer(121” _{Source electrode 2} ). The second inward metal layer may comprise a second inward first drain layer (131', _{drain 1} ) A second inward first source and second drain layer (131' _{Source 1+ drain 2} ) A second inward second source layer (131' _{Source electrode 2} ). The first device terminal may be coupled to a first inward first gate layer (121'; _{grid 1} ). A second device terminal may be coupled to the first inward first source layer and the second drain (121', _{source 1+ drain 2} ). A third device terminal may be coupled to the second inward first drain layer (131', _{drain 1} ). A fourth device terminal may be coupled to the second inward first source layer and the second drain (131'; _{source 1+ drain 2} ). A fifth device terminal may be coupled to the second inward second source layer (131'; _{source electrode 2} ). The sixth device terminal may be coupled to the first inward second gate layer (121'; _{grid 2} ). The seventh device terminal may be coupled to the first inward first drain layer (121'; _{drain 1} ) And a second inward first drain layer (131', _{Drain 1} ). An eighth device terminal may be coupled to the first inward first source and second drain layer (121', _{source 1+ drain 2} ) And a second inward first source and second drain layer (131' _{Source 1+ drain 2} ). A ninth device terminal may be coupled to the first inward second source layer (121'; _{source electrode 2} ) And a second inward second source layer (131', _{source electrode 2} ). The plurality of embedded devices may be coupled to a first inward conductive layer, a second inward conductive layer; and a device terminal.

From all of the above, one skilled in the art can determine that in one example, the first module substrate can include a first inward side and a first outward side opposite the first inward side. The second module substrate may include a second inward side and a second outward side opposite the second inward side. The first embedded module may include a first module encapsulant over the first module assembly, the first inward side, and the second inward side. The first outward side and the second outward side may be exposed from the module encapsulant. In one example, the first embedded module is free of spacers.

In an example, the first device substrate may further include a first core layer including a first side and a second side opposite the first side, and a first inward conductive layer on the second side. The first outward conductive layer may be located on a first side of the first core layer. The first inward conductive layer may be coupled to a first conductive structure of the first module substrate.

In an example, the encapsulant structure may include a first side, a second side opposite the first side, and a third side extending from the first side to the second side. The first outward conduction layer of the first device substrate may be exposed from the first side of the encapsulant structure. The second outward conduction layer of the second device substrate may be exposed from the second side of the encapsulant structure. The device terminals may be exposed from a third side of the encapsulant structure.

In an example, the first module substrate may be a first routable molded leadframe. The second module substrate may be a second routable molded leadframe. The first routable molded leadframe may be coupled to the second routable molded leadframe by a module interconnect. The device terminals may be coupled to a second routable molded leadframe.

From all of the above, one skilled in the art can determine that, in an example, an electronic device can include a plurality of embedded modules, each of the plurality of embedded modules including a module first substrate, one or more electronic components coupled to the module first substrate, and a module second substrate positioned over the one or more electronic components. The first device substrate may be coupled to a module first substrate of a first embedded module of the plurality of embedded modules and a module second substrate of a second embedded module of the plurality of embedded modules. The second device substrate may be coupled to the module second substrate of the first embedded module and the module first substrate of the second embedded module.

The present disclosure contains references to certain examples, however, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the disclosure. Therefore, it is intended that the disclosure not be limited to the disclosed examples, but that the disclosure will include all examples falling within the scope of the appended claims.

Claims

1. An electronic device, comprising:

a first embedded module, the first embedded module comprising:

a first module substrate; and

a first module assembly coupled to the first module substrate;

a first device substrate coupled to the first module substrate;

a device terminal coupled to the first module assembly; and

a device encapsulant structure encapsulating the first embedded module, the device terminals, and the first device substrate;

wherein:

a portion of the first device substrate is exposed from the device encapsulant structure; and is also provided with

Portions of the device terminals are exposed from the device encapsulant structure.

2. The electronic device of claim 1, wherein:

the first embedded module includes a second module substrate coupled to the first module substrate and the first module assembly;

the first module assembly is interposed between the first module substrate and the second module substrate;

the first module substrate includes a first inward side, a first outward side opposite the first inward side, a first conductive structure, and a first dielectric structure;

the second module substrate includes a second inward side, a second outward side opposite the second inward side, a second conductive structure, and a second dielectric structure;

the first module assembly is coupled to the first conductive structure at the first inward side of the first module substrate; and is also provided with

The first module assembly is coupled to the second conductive structure at the second inward side of the second module substrate.

3. The electronic device of claim 2, wherein:

the first embedded module includes:

a third module substrate comprising a third on-axis side, a third off-axis side opposite the third on-axis side, a third conductive structure, and a third dielectric structure;

A second module assembly coupled to the second conductive structure at the second outward side of the second module substrate and coupled to the third conductive structure at the third inward side of the third module substrate;

a first module encapsulant interposed between the first module substrate and the second module substrate and encapsulating the first module assembly; and

a second module encapsulant interposed between the second module substrate and the third module substrate and encapsulating the second module assembly.

4. The electronic device of claim 3, wherein:

the third outside of the third module substrate is exposed from the device encapsulant structure.

5. The electronic device of claim 2, wherein:

the first embedded module includes a first module encapsulant over the first module assembly, the first inward side of the first module substrate, and the second inward side of the second module substrate; and is also provided with

The first outward side of the first module substrate and the second outward side of the second module substrate are exposed from the first module encapsulant.

6. The electronic device of claim 5, further comprising:

a second embedded module, the second embedded module comprising:

a fourth module substrate comprising a fourth inward side, a fourth outward side opposite the fourth inward side, a fourth conductive structure, and a fourth dielectric structure;

a second module assembly coupled to the third conductive structure at the third inward side of the third module substrate and coupled to the fourth conductive structure adjacent the fourth inward side of the fourth module substrate; and

a second module encapsulant located over the second module assembly, the third inward side of the third module substrate and the fourth inward side of the fourth module substrate;

wherein:

the third outward side of the third module substrate and the fourth outward side of the fourth module substrate are exposed from the second module encapsulant; and is also provided with

The device encapsulant structure encapsulates the second embedded module.

7. The electronic device of claim 6, wherein:

the second embedded module is located above the first embedded module.

8. The electronic device of claim 7, wherein:

the device terminal is interposed between the first embedded module and the second embedded module.

9. The electronic device of claim 6, wherein:

the second embedded module is laterally spaced apart from the first embedded module.

10. The electronic device of claim 2, wherein:

the device terminal is attached to the second conductive structure of the second module substrate.

11. The electronic device of claim 1, further comprising:

a second device substrate coupled to the first module assembly;

wherein:

the second device substrate is exposed from the device encapsulant structure.

12. The electronic device of claim 11, wherein:

the first device substrate includes:

a first core layer;

a first outward metal layer coupled to the first core layer; and

A first inward metal layer coupled to the first module substrate and the first core layer, the first core layer disposed between the first inward metal layer and the first outward metal layer; and is also provided with

The second device substrate includes:

a second core layer;

a second outward metal layer coupled to the second core layer; and

a second inward metal layer coupled to the first module assembly and the second core layer, the second core layer disposed between the second inward metal layer and the second outward metal layer.

13. The electronic device of claim 12, further comprising:

a plurality of embedded modules, the plurality of embedded modules including the first embedded module;

wherein:

the plurality of embedded modules are coupled to one or more of the first inward metal layer, the second inward metal layer, or the device terminal.

14. The electronic device of claim 1, wherein:

the device encapsulant structure comprises:

a first device encapsulant encapsulating the first embedded module; and

A second device encapsulant encapsulating the first device substrate;

the first module substrate is exposed from the first device encapsulant; and is also provided with

The second device encapsulant covers a portion of the first module substrate exposed from the first device encapsulant.

15. The electronic device of claim 1, further comprising:

a second module assembly coupled to the first module substrate;

wherein:

the first module substrate includes a routable molded leadframe; and is also provided with

The first module assembly and the second module assembly are located on the same plane.

16. An electronic device, comprising:

a first embedded module, the first embedded module comprising:

a first module substrate comprising a first conductive structure;

a second module substrate comprising a second conductive structure; and

a first module assembly interposed between the first module substrate and the second module substrate, the first module assembly comprising:

a first component terminal coupled to the first conductive structure; and

A second component terminal coupled to the second conductive structure;

a first device substrate coupled to the first module substrate and including a first outward conduction layer;

a second device substrate coupled to the first module assembly and including a second outward conduction layer;

a device terminal coupled to the first module assembly; and

a device encapsulant structure encapsulating the first embedded module, the first device substrate, the second device substrate, and the device terminals;

wherein:

the device terminals, the first outward conductive layer, and the second outward conductive layer are exposed from the device encapsulant structure.

17. The electronic device of claim 16, wherein:

the first embedded module includes:

a third module substrate comprising a third conductive structure;

a second module assembly interposed between the second module substrate and the third module substrate and including a third assembly terminal coupled to the second conductive structure and a fourth assembly terminal coupled to the third conductive structure;

18. The electronic device of claim 16, further comprising:

a first module encapsulant encapsulating the first module assembly; and

a second embedded module, the second embedded module comprising:

a third module substrate comprising a third conductive structure;

a fourth module substrate comprising a fourth conductive structure;

a second module assembly including a third assembly terminal coupled to the third conductive structure and a fourth assembly terminal coupled to the fourth conductive structure; and

a second module encapsulant encapsulating the second module assembly;

wherein:

the device encapsulant structure encapsulates the second embedded module.

19. A method of manufacturing an electronic device, the method comprising:

Providing a first embedded module, the first embedded module comprising:

a first module substrate comprising a first conductive structure;

a second module substrate comprising a second conductive structure; and

a first component terminal coupled to the first conductive structure; and

a second component terminal coupled to the second conductive structure;

providing a first device substrate coupled to the first module substrate and including a first outward conduction layer;

providing a second device substrate coupled to the first module assembly and including a second outward conduction layer;

providing a device terminal coupled to the first module assembly; and

providing a device encapsulant structure that encapsulates the first embedded module, the first device substrate, the second device substrate, and the device terminals;

Wherein:

20. The method according to claim 19, wherein:

providing the first embedded module includes:

providing a third module substrate comprising a third conductive structure;

providing a second module assembly interposed between the second module substrate and the third module substrate and including a third assembly terminal coupled to the second conductive structure and a fourth assembly terminal coupled to the third conductive structure;

providing a first module encapsulant interposed between the first module substrate and the second module substrate and encapsulating the first module assembly; and

a second module encapsulant is provided, interposed between the second module substrate and the third module substrate, and encapsulates the second module assembly.

21. The method as recited in claim 19, further comprising:

providing a first module encapsulant, the first module encapsulant encapsulating the first module assembly; and

Providing a second embedded module, the second embedded module comprising:

a third module substrate comprising a third conductive structure;

a fourth module substrate comprising a fourth conductive structure;

a second module encapsulant encapsulating the second module assembly;

wherein:

providing the device encapsulant structure includes encapsulating the second embedded module.