JPS6094755A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6094755A JPS6094755A JP58203116A JP20311683A JPS6094755A JP S6094755 A JPS6094755 A JP S6094755A JP 58203116 A JP58203116 A JP 58203116A JP 20311683 A JP20311683 A JP 20311683A JP S6094755 A JPS6094755 A JP S6094755A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- bonding
- pad
- envelope
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に高密度ＩＣやＬＳ■ペ
レッ１−のパッケージング技術に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor devices, and particularly to packaging technology for high-density ICs and LS pellets.
ＩＣやし８１等の半導体装置は、集積回路の形成されて
いる半導体ペレットをリードが具面された外囲器内にパ
ッケージングした実装形態で使用される。この場合、半
導体ペレッ１への表面に形成された集積回路の内部端子
（ホンディングパッド）は、ボンディングワイヤを介し
−Ｃ外囲器内部で外囲器リードに接続され、外囲器リー
ドににっで外囲器の外部に取出される。第１図は、外囲
器内部に於ける前記ポンディングパッドと外囲器リード
との接続状態を示している。図中１は外囲器基板、２は
外囲器リードで、外囲器基板１十には半導体ペレット３
がマウントされるど共に、該半導体ペレット表面に形成
されたポンディングパッド４はボンディングワイヤ５を
介して外囲器リード２に接続されている。A semiconductor device such as the IC palm 81 is used in a packaged form in which a semiconductor pellet on which an integrated circuit is formed is packaged in an envelope provided with leads. In this case, the internal terminals (bonding pads) of the integrated circuit formed on the surface of the semiconductor pellet 1 are connected to the package leads inside the -C package via bonding wires, and are connected to the package leads through bonding wires. It is taken out of the envelope. FIG. 1 shows the state of connection between the bonding pad and the envelope lead inside the envelope. In the figure, 1 is an envelope board, 2 is an envelope lead, and a semiconductor pellet 3 is on the envelope board 10.
When the semiconductor pellet is mounted, a bonding pad 4 formed on the surface of the semiconductor pellet is connected to the envelope lead 2 via a bonding wire 5.
上記の様に従来の半導体装置では、半導体ペレットのボ
ンディングワイヤと外囲器リードどはボンディングワイ
ヤによって直接々続されていた。As described above, in conventional semiconductor devices, the bonding wire of the semiconductor pellet and the envelope lead are directly connected to each other by the bonding wire.
ＩＣからＬＳＩへといった半導体装置の高集積化、高密
度化に伴い、パッケージングの際にポンディングパッド
と外囲器リードとの間の接続に用いられている従来の方
法には次の様な問題が生じていた。With the increasing integration and density of semiconductor devices, from ICs to LSIs, the following conventional methods are used to connect bonding pads and package leads during packaging. A problem had arisen.
高集積化が進むと、半導体ペレット中に形成される回路
パターンのデザイン上、ポンディングパッド４をペレッ
ト３の一部に集中させる方が集積度を向上する上で有利
である。ところが、ポンディングパッドを一部に集中さ
せると、外囲器り一部２・・・はペレット３の周囲に均
一に配設されている為、第２図に示す様に両者を接続す
るボンディングワイヤ５が強い角度で配列されることに
なる。As the degree of integration progresses, it is advantageous to concentrate the bonding pads 4 on a part of the pellet 3 in terms of the design of the circuit pattern formed in the semiconductor pellet in order to improve the degree of integration. However, when the bonding pads are concentrated in one part, the outer shell part 2... is evenly distributed around the pellet 3, so the bonding pads connecting the two parts as shown in FIG. The wires 5 will be arranged at a strong angle.
この結果、隣接するボンディングワイヤ５が相互に接触
したり、別のポンディングパッド４に接触して短絡を生
じてしまう。このような問題を回避する為に、従来の半
導体装置では外囲器リード２・・・どの接続を考慮して
ポンディングパッド４・・・をペレット３の周縁部に出
来るだけ散在させなければならなかった。これは、既述
した所から明らかな様に、集積度を犠牲にせざるを得な
いことを意味する。As a result, adjacent bonding wires 5 come into contact with each other or with another bonding pad 4, resulting in a short circuit. In order to avoid such problems, in conventional semiconductor devices, the bonding pads 4 must be scattered as much as possible around the periphery of the pellet 3, taking into account the connection of the package leads 2. There wasn't. As is clear from the above, this means that the degree of integration must be sacrificed.
他方、ポンディングパッド４は機能素子に較べて大きな
面積を占める為、機能素子エリアを制限して集積度の向
上を妨げる要因どなるが、この問題に関しても従来のパ
ッケージング技術は次の様な欠点を有している。即ち、
ポンディングパッド４・・・相互の間のスペースには素
子を形成できないから、ポンディングパッド４・・・を
散在さＵることはデッドスペースが大きくなることを意
味するがらである。因みに、従来の半導体装直動【プる
ポンディングパッド４・・・のりイズは外囲器リード２
との接続を考慮した場合、パッド幅ａ＝１００１１ｍ、
パッド間隔ｂ＝２６μｍとするのが限度で・あった。On the other hand, since the bonding pad 4 occupies a larger area than the functional element, it limits the area of the functional element and hinders the improvement of the degree of integration.However, regarding this problem, conventional packaging technology has the following drawbacks. have. That is,
Since no element can be formed in the space between the bonding pads 4, scattering the bonding pads 4 means that the dead space becomes large. By the way, in the conventional semiconductor direct-acting [pull-ponding pad 4...glue size is
Considering the connection with the pad width a=10011m,
The limit was to set the pad spacing b to 26 μm.
本発明は上記事情に鑑みて為されたもので、半導体ペレ
ット表面に於【ノるポンディングパッドの配置を可能な
限り高密度で一部に集中させてペレット内回路の高集積
化を図り、■っボンディングワイヤ相互間あるいはボン
ディングワイＸ７どポンディングパッドとの間の接触に
Ｊこる７、０絡等の問題を生じることなく外囲器へのパ
ッケージングを可能とした半導体装置を１１を供するし
の７パある。The present invention has been made in view of the above circumstances, and aims to achieve high integration of circuits within the pellet by arranging bonding pads on the surface of a semiconductor pellet as densely as possible and concentrating them in one part. (11) To provide a semiconductor device which can be packaged into an envelope without causing problems such as contact between bonding wires or bonding pads. There are seven Shinopa.
本発明による半導体装置は、リードを備えた外囲器内に
収納された半導体ペレットと、該半導体ペレットと共に
前記外囲器内に収納された配線層を有する中継部材と、
該中継部材に形成された配線層の一端を前記半導体ペレ
ットの表面に形成されたポンディングパッドに接続する
ボンディングワイヤと、前記中継部材に形成された配線
層の他端を前記外囲器のリードに接続するボンディング
ワイヤとを具備したことを特徴とするものである。A semiconductor device according to the present invention includes: a semiconductor pellet housed in an envelope having leads; a relay member having a wiring layer housed in the envelope together with the semiconductor pellet;
A bonding wire connects one end of the wiring layer formed on the relay member to a bonding pad formed on the surface of the semiconductor pellet, and the other end of the wiring layer formed on the relay member is connected to a lead of the envelope. The device is characterized by comprising a bonding wire connected to the.
本発明に於ける中継部材としては、シリコン等の半導体
ペレット、３Ｑ３ （３ｉｌｉｃｏｎ ｏｎ ３ａｐｐ
ｈｉｒｅ ）ペレットあるいはポリイミド樹脂等の耐熱
性絶縁樹脂ペレットに所望の配線層を形成したものを用
いることが出来る。配線層としては、これらペレット表
面に形成されたアルミニウム等の金属配線パターンを用
いることが出来、また半導体ペレットやＳＯＳペレット
の場合には不純物の拡散による拡散配線パターンを用い
ても良い。更に、半導体ペレットやＳＯＳベレットを中
継部材５−
として用いる場合には、該中継部材に配ｌ１１１層だ【
ノでなく回路素子をも形成することが出来る。As the relay member in the present invention, semiconductor pellets such as silicon, 3Q3 (3ilicon on 3app
) pellets or heat-resistant insulating resin pellets such as polyimide resin on which a desired wiring layer is formed can be used. As the wiring layer, a metal wiring pattern made of aluminum or the like formed on the surface of these pellets can be used, and in the case of semiconductor pellets or SOS pellets, a diffusion wiring pattern formed by diffusion of impurities may be used. Furthermore, when semiconductor pellets or SOS pellets are used as the relay member 5-, the relay member has a layer 111 [
It is also possible to form circuit elements.
上記本発明の半導体装置では、半導体ぺ１ノツトのポン
ディングパッドは中継部材に形成された配線層を介して
外囲器リードに接続され、該配線層の一端とポンディン
グパッドとの間、並びに前記配線層の他端と外囲器リー
ドの間の二箇所でワイヤボンディングが行われる。従っ
て、中継部材に於ける配線層の一端をポンディングパッ
ドの近傍に配置し、前記配線層の他端を外囲器リード近
傍に配置すれば、外囲器リードとの接続に何等の障害を
来たすこと無くポンディングパッドを半導体ペレットの
一部に集中さゼることができ、集積度の向上を図ること
が出来る。In the semiconductor device of the present invention, the bonding pad of the semiconductor node is connected to the envelope lead via the wiring layer formed on the relay member, and the bonding pad of the semiconductor node is connected to the envelope lead through the wiring layer formed on the relay member, and between one end of the wiring layer and the bonding pad, and Wire bonding is performed at two locations between the other end of the wiring layer and the envelope lead. Therefore, if one end of the wiring layer of the relay member is placed near the bonding pad and the other end of the wiring layer is placed near the envelope lead, there will be no problem in connection with the envelope lead. The bonding pads can be concentrated on a part of the semiconductor pellet without causing any damage, and the degree of integration can be improved.
なおハイブリッドＩＣでは、第３図に示づ様に内部配線
を持たないペレット６．６′をボンディングワイヤ５の
中継用に使用することが従来から行われている。然し乍
ら、この場合は中継用のペレット６．６′が何等配線を
持たない為、甲にボンディングワイヤ５を中間で支持す
る機能しか梵６一
揮し得ず、到底本発明の目的を達成し得るものではない
。In the hybrid IC, as shown in FIG. 3, pellets 6 and 6' having no internal wiring have been conventionally used for relaying the bonding wires 5. However, in this case, since the relay pellets 6 and 6' do not have any wiring, the shell 6 can only perform the function of supporting the bonding wire 5 in the middle, and the purpose of the present invention cannot be achieved at all. isn't it.
以下、第４図〜第８図（Ａ）（Ｂ）を参照して本発明の
詳細な説明する。Hereinafter, the present invention will be described in detail with reference to FIGS. 4 to 8 (A) and (B).
第４図は本発明の一実施例になる半導体装置に於いて、
外囲器内に収容された半導体ペレットおよび中継部材を
示す平面図である。同図に於いて、１１はセラミック製
の外囲器、１２は外囲器のマウント基板、１３は外囲器
リードである。マウント基板１１には半導体ゲートアレ
イペレット１４及び中継用のシリコンペレット１５がグ
イボンディングされている。ゲートアレイペレッ１−１
４では、内部回路の集積度を向上させる為にポンディン
グパッド１６・・・、１６′・・・を対向側縁にのみ集
中して形成しである。特に、中継用のペレット１５に対
向した側縁にはポンディングパッド１６・・・が２列に
亙って高密度に配列されている。他方、中継用ペレッ１
〜１５には表面にアルミニウムの配線層１７・・・がパ
ターンニング形成されているのみで、回路素子は形成さ
れていない。この配線層１７・・・は夫々その一端をゲ
ートアレイペレット１／Ｉの２列に配列されたポンディ
ングパッド１６に対向してその近傍に配置され、他端は
夫々対応する外囲器リード１３・・・の近傍に配置され
ており、両端には夫々パッド１８・・・、１８′・・・
が形成されている。上記ポンディングパッド及びパッド
１６・・・。FIG. 4 shows a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a plan view showing a semiconductor pellet and a relay member housed in an envelope. In the figure, 11 is a ceramic envelope, 12 is a mounting board for the envelope, and 13 is an envelope lead. A semiconductor gate array pellet 14 and a relay silicon pellet 15 are bonded to the mount substrate 11. Gate array pellet 1-1
4, in order to improve the degree of integration of the internal circuit, the bonding pads 16..., 16'... are formed concentrated only on the opposite side edges. In particular, on the side edge facing the relay pellets 15, two rows of bonding pads 16 are arranged at high density. On the other hand, relay pellet 1
15, only aluminum wiring layers 17 are formed by patterning on the surface, and no circuit elements are formed thereon. Each of the wiring layers 17 has one end facing and close to the bonding pads 16 arranged in two rows of the gate array pellet 1/I, and the other end of each of the wiring layers 17... . . , and pads 18 . . . , 18' .
is formed. The above-mentioned pounding pad and pad 16...
１６−・・・、１８・・・、１８・・・は大々図示しな
いボンディングワイヤにより次の様にライ−１／ボンデ
イングされている。先ず、ゲートアレイペレットに形成
されたポンディングパッドのうら、１列に配置されたポ
ンディングパッド１６−・・・は夫々ボンディングワイ
ヤを介して対応する外囲器リード１３に直接々続されて
いる。他方、２列にガって高密度に配置されたポンディ
ングパッド１６・・・は、これに対向して配置された中
継部材上のパッド１日・・・との間で夫々ワイヤボンデ
ィングされている。16-..., 18..., 18... are wire-1/bonded as follows using bonding wires (not shown). First, behind the bonding pads formed on the gate array pellet, the bonding pads 16 arranged in a row are each directly connected to the corresponding envelope lead 13 via a bonding wire. . On the other hand, the bonding pads 16 arranged in two rows with high density are wire-bonded to the pads 16 on the relay member arranged opposite to each other. There is.
そして、外囲器リード１３に近接して中継部材１５上に
形成されたパッド１８−・・・は、、人々対応する外囲
器リード１３との間でワイＶボンディングされている。The pads 18 formed on the relay member 15 in the vicinity of the envelope lead 13 are wire-V bonded to the corresponding envelope lead 13.
従って、高密度で２列に配置されたポンディングパッド
１８・・・は、夫々中継部材１５に形成された配線層１
７・・・を介して外囲器リード１３・・・に接続されて
いることになる。なお、第４図に於けるポンディングパ
ッド１６・・・、１６′・・・、配線層１７・・・、パ
ッド１８・・・、１８′・・・は何れも簡略化して書か
れており、実際には通かに密集して形成されている。Therefore, the bonding pads 18 arranged in two rows with high density are connected to the wiring layer 1 formed on the relay member 15, respectively.
7... to the envelope leads 13... Note that the bonding pads 16..., 16'..., wiring layer 17..., pads 18..., 18'... in FIG. 4 are all simplified. , in fact, they are densely formed.
第５図は、第４図に於けるポンディングパッド１６・・
・とパッド１８・・・との間のワイヤボンディング部分
を拡大して示す平面図である。図示の様に、ポンディン
グパッド１６・・・は前列及び後列で互い違いに配置さ
れ、これによって第６図に示す様にパッド間隔はゼロに
なっている（パッド幅ａは第２図の場合と同じ＜１００
μｍである）。また、中継部材１５上のパッド１８・・
・は、夫々ポンディングパッド１８・・・を中継部材上
に並行移動した位置に形成されている。従って、両者を
接続するボンディングワイヤ１９・・・は極めて高密度
であるにも拘らず、相互に接触したり他のボンディング
パッ９ー
ドに接触したりすることなく整然と並んでいる。Figure 5 shows the bonding pad 16 in Figure 4.
. . is an enlarged plan view showing a wire bonding portion between pads 18 and 18 . As shown in the figure, the pounding pads 16 are arranged alternately in the front row and the rear row, so that the pad spacing is zero as shown in FIG. 6 (the pad width a is different from that in FIG. 2). Same <100
μm). In addition, the pad 18 on the relay member 15...
. are formed at positions where the bonding pads 18... are moved in parallel on the relay member. Therefore, although the bonding wires 19 connecting the two are extremely dense, they are lined up in an orderly manner without contacting each other or other bonding pads.
上記実施例によれば、ゲートアレイペレット４のポンデ
ィングパッドを一部に集中して形成しても、何等支障な
くパッケージングすることが出来る。この結果、ゲート
アレイペレッ１〜１４内の回路デザインを高集積化のみ
を考慮して行なうことができ、また大きな面積を占める
ポンディングパッドを密集させることにより機能素子エ
リアを広く確保できる等により、集積度の向上を図るこ
とが可能となる。According to the above embodiment, even if the bonding pads of the gate array pellet 4 are formed in a concentrated manner in one part, packaging can be performed without any problem. As a result, the circuit design within the gate array pellets 1 to 14 can be designed with only high integration in mind, and by crowding the bonding pads that occupy a large area, a wide functional element area can be secured, etc. It becomes possible to improve the degree of integration.
なお、この実施例では中継用のベレッ１へを一個だけ用
いたが、必要に応じて二つ以上の中継用ペレットを用い
ることができ、ゲートアレ、イベレット１４の四方に中
継用ペレット１５を配置しても良い。In this embodiment, only one relay pellet 1 is used, but two or more relay pellets can be used if necessary, and the relay pellets 15 are arranged on all sides of the gate array and the pellet 14. It's okay.
第７図（Ａ）は本発明の他の実施例になる半導体装置に
於いて、パッケージングの為の外囲器リードと半導体ペ
レットとの間の接続状態を示す平面図であり、第７図（
Ｂ）は同図（Ａ）のＢ−Ｂ線に沿う断面図である。この
実施例では、中継用１０−
のペレット２１１上にＬＳＩペレット２２、更にその上
にＬＳＩペレット２３が夫々エポキシ系接着剤等で積層
固定されている。中継用ペレット２１には第４図〜第７
図の実施例に於ける中継用ペレット１５と同じく、中継
用の配線層がアルミニウムパターンで形成されている。FIG. 7(A) is a plan view showing a state of connection between an envelope lead for packaging and a semiconductor pellet in a semiconductor device according to another embodiment of the present invention; FIG. (
B) is a sectional view taken along line BB in FIG. In this embodiment, an LSI pellet 22 is stacked on a relay pellet 211, and an LSI pellet 23 is fixed thereon using an epoxy adhesive or the like. The relay pellets 21 are shown in Figures 4 to 7.
Similar to the relay pellet 15 in the illustrated embodiment, the relay wiring layer is formed of an aluminum pattern.
そして、Ｌ Ｓ 、１ペレット２２．２３のポンディン
グパッドはボンディングワイヤ２４により中継用のペレ
ット２１上に形成されたアルミニウム配線層を介して外
囲器リード２５に接続されている。The bonding pads of L S and 1 pellet 22 and 23 are connected to the envelope lead 25 by a bonding wire 24 through an aluminum wiring layer formed on the relay pellet 21 .
この実施例では、先の実施例の場合と同じくＬＳＩペレ
ット２２．２３のポンディングパッドを一部に集中させ
ることが可能となる他、一つの外囲器内に複数のｊ−８
１ペレツトをパッケージングすることが可能となる。従
って、Ｌ Ｓ 、Ｉペレット２２．２３の集積度を上げ
なくても、比較的簡単な方法で、一つの外囲器内にパッ
ケージされた半導体装置の実装密度を大幅に向上するこ
とが出来る。In this embodiment, as in the case of the previous embodiment, it is possible to concentrate the bonding pads of the LSI pellets 22 and 23 in one part, and in addition, a plurality of j-8
It becomes possible to package one pellet. Therefore, without increasing the degree of integration of the L S and I pellets 22 and 23, the packaging density of semiconductor devices packaged in one envelope can be significantly improved by a relatively simple method.
以上詳述した様に、本発明によれば半導体ペレット表面
に於けるポンディングパッドの配置を可能な限り高密度
で一部に集中さけてべ１フッ１〜内回路の高集積化を図
り、「１つボンｆイングヮイ１７＋ｉｌ互間あるいはボ
ンディングワイＸ７とボンｊ′イングパッドとの間の接
触にＪ：る短絡等の問題を生じることなく外囲器へのパ
ッケージングをｌ′ｉＩ能と出来る等、顕著な効果が得
られるものである。As detailed above, according to the present invention, the bonding pads on the surface of the semiconductor pellet are arranged as densely as possible, avoiding concentration in one part, thereby achieving high integration of the internal circuits. ``Packaging into an envelope can be performed without causing problems such as short circuits due to contact between one bonding pad or between the bonding pad and the bonding pad. etc., remarkable effects can be obtained.
第１図は従来の半導体装置に於（）る半導体ペレットと
外囲器リードどの間の接続方法を承り断面図、第２図は
従来の半導体装置に於（ｊる問題点を示す説明図、第３
図はハイブリッドＩ（］について従来行われている別の
ワイ（７ボンデーｆング方法を示す断面図、第４図は本
発明の一実施例に成る半導体装置に於いて、外囲器内に
収容された２１（導体ペレット及び中継部材を示す平面
図、”：ｌｊ Ｊ図は第４図の一部を拡大して示ず平面
図、第６図は第５図に於けるポンディングパッドのパッ
ド幅とパッド間隔を示す図、第７図（Ａ＞ｉＪ本′１を
明の他の実施例に成る半導体装置に於いて、パッケージ
ングの為の外囲器リードと半導体ペレットとの間の接続
状態を示す平面図、第７（Ｂ）は同図（Ａ＞のＢ＝Ｂ線
に沿う断面図である。
１１・・・外囲器、１２・・・外囲器基板、１３・・・
外囲器リード、１４・・・ゲートアレイペレット、１５
・・・中継用ペレット、１６．．１．６−・・・ポンデ
ィングパッド、１７・・・配線層、１．８．．１８′・
・・パッド、１９・・・ボンディングワイヤ、２１・・
・中継型ペレット、２２．２３・・・ＬＳＩペレット、
２４・・・ボンディングワイヤ、２５・・・外囲器リー
ド。
出願人代理人 弁理士 鈴江武彦
１３−FIG. 1 is a sectional view showing a connection method between a semiconductor pellet and an envelope lead in a conventional semiconductor device, and FIG. 2 is an explanatory diagram showing problems in a conventional semiconductor device. Third
The figure is a cross-sectional view showing another bonding method conventionally used for hybrid I(). Figure 21 (plan view showing conductor pellets and relay members): lj Figure J is an enlarged plan view of a part of Figure 4, and Figure 6 is a plan view showing the pad of the bonding pad in Figure 5. A diagram showing the width and pad spacing, and FIG. A plan view showing the state, No. 7 (B) is a sectional view taken along the B=B line in the same figure (A>. 11... Envelope, 12... Envelope substrate, 13...
Envelope lead, 14... Gate array pellet, 15
... Relay pellets, 16. ．． 1.6-... Bonding pad, 17... Wiring layer, 1.8. ．． 18'・
...Pad, 19...Bonding wire, 21...
・Relay type pellet, 22.23...LSI pellet,
24...Bonding wire, 25...Envelope lead. Applicant's agent Patent attorney Takehiko Suzue 13-
Claims (1)
トと、該半導体ペレットとｊｔに前記外囲器内に収納さ
れた配線層を有づ−る中継部材ど、該中継部材に形成さ
れた配線層の一端を前記半導体ペレットの表面に形成さ
れたポンディングパッドに接続するボンディングワイヤ
と、前記中継部材に形成された配線層の他端を前記外囲
器のリードに接続するボンディングワイヤとを具備した
ことを１に檄とする半導体装置。A semiconductor integrated pellet housed in an envelope having leads, and a relay member having a wiring layer housed in the envelope between the semiconductor pellet and the jt, formed on the relay member. a bonding wire that connects one end of the wiring layer formed on the semiconductor pellet to a bonding pad formed on the surface of the semiconductor pellet; and a bonding wire that connects the other end of the wiring layer formed on the relay member to the lead of the envelope. A semiconductor device having the above features.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58203116A JPS6094755A (en) | 1983-10-29 | 1983-10-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58203116A JPS6094755A (en) | 1983-10-29 | 1983-10-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6094755A true JPS6094755A (en) | 1985-05-27 |
Family
ID=16468661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58203116A Pending JPS6094755A (en) | 1983-10-29 | 1983-10-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6094755A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235352A (en) * | 2003-01-29 | 2004-08-19 | Sharp Corp | Semiconductor apparatus |
| JP2007180587A (en) * | 2007-03-29 | 2007-07-12 | Sharp Corp | Semiconductor device |
-
1983
- 1983-10-29 JP JP58203116A patent/JPS6094755A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235352A (en) * | 2003-01-29 | 2004-08-19 | Sharp Corp | Semiconductor apparatus |
| USRE41826E1 (en) | 2003-01-29 | 2010-10-19 | Sharp Kabushiki Kaisha | Semiconductor device |
| JP4615189B2 (en) * | 2003-01-29 | 2011-01-19 | シャープ株式会社 | Semiconductor device and interposer chip |
| JP2007180587A (en) * | 2007-03-29 | 2007-07-12 | Sharp Corp | Semiconductor device |
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