JPH02125653A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH02125653A JPH02125653A JP63279856A JP27985688A JPH02125653A JP H02125653 A JPH02125653 A JP H02125653A JP 63279856 A JP63279856 A JP 63279856A JP 27985688 A JP27985688 A JP 27985688A JP H02125653 A JPH02125653 A JP H02125653A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- integrated circuit
- insulating substrate
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特に対応するバット
同志を互に接続する複数の半導体チップを備えた混成集
積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device including a plurality of semiconductor chips whose corresponding butts are interconnected.
従来、この種の混成集積回路装置は、第３図に示すよう
に、Ｄ−ＲＡＭのように同一機能、同一構造の複数の半
導体チップ２Ａを絶縁性基板ＩＡ上に搭載し、これら半
導体チップの対応するパッド（２１Ａ〜２４Ａ）同志を
互に接続する場合、゛パターン配線３Ａが交差するため
に絶縁性基板ＩＡを多層化してパターン配線３Ａを形成
する構造となっていた。Conventionally, this type of hybrid integrated circuit device, as shown in FIG. When the corresponding pads (21A to 24A) are connected to each other, the pattern wiring 3A is formed by multilayering the insulating substrate IA because the pattern wiring 3A intersects with each other.
上述した従来の混成集積回路装置は、同一機能、構造の
複数の半導体チップ２人の対応するパッド（２１Ａ〜２
４Ａ）同志を互いに接続する場合、多層化した絶縁性基
板ＩＡによりパターン配線３Ａを形成する構造となって
いるので、絶縁性基板ＩＡの製造コストが高くなるとい
う欠点がある。The above-described conventional hybrid integrated circuit device has a plurality of semiconductor chips having the same function and structure with corresponding pads (21A to 2).
4A) When connecting comrades to each other, the structure is such that the pattern wiring 3A is formed using a multilayered insulating substrate IA, which has the drawback of increasing the manufacturing cost of the insulating substrate IA.
本発明の目的は、絶縁性基板の製造コストを低減するこ
とができる混成集積回路装置を提供することにある。An object of the present invention is to provide a hybrid integrated circuit device that can reduce the manufacturing cost of an insulating substrate.
本発明の混成集積回路装置は、絶縁性基板上に、所定の
位置に回路接続用の複数のパッドを備えた第１の半導体
チップと、前記各パッドと対応しかつ互いに鏡映対称と
なる位置に設けられた回路接続用の複数のパッドを備え
た第２の半導体チ・ノブと、前記第１及び第２の半導体
チップの対応する各パッド間をそれぞれ接続するための
複数のパターン配線と、これら各パターン配線を介して
１符記第１及び第２の半導体チップの対応する各パッド
間をそれぞれ接続する複数の金属細線とを有している。A hybrid integrated circuit device of the present invention includes a first semiconductor chip provided with a plurality of pads for circuit connection at predetermined positions on an insulating substrate, and positions corresponding to each of the pads and mirror-symmetrical to each other. a second semiconductor chip/knob provided with a plurality of pads for circuit connection provided in the semiconductor chip; a plurality of pattern wirings for respectively connecting the corresponding pads of the first and second semiconductor chips; It has a plurality of thin metal wires that respectively connect the corresponding pads of the first and second semiconductor chips marked 1 through these pattern wirings.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するための中間工程の
混成集積回路装置の平面図である。FIG. 1 is a plan view of a hybrid integrated circuit device in an intermediate process for explaining one embodiment of the present invention.
この実施例は、絶縁性基板１上に搭載され、所定の位置
に回路接続用の複数のパッド２１Ａ〜２４＾を備えた第
１の半導体チップ２Ａと、この半導体チップ２Ａの各パ
ッド２１Ａ〜２４Ａと対応しかつ互いに鏡映対称の位置
に設けられた回路接続用の複数のパッド２１８〜２４Ｂ
を備え、半導体チップ２Ａと同一機能をもつ第２の半導
体チップ２Ｂと、絶縁性基板１上に形成され、これら第
１及び第２の半導体チップ２Ａ 、２ｍの対応するパッ
ド２１＾〜２４＾、２１８〜２４Ｂ間をそれぞれ接続す
るための複数のパターン配線３と、これら各パターン配
線３を介して第１及び第２の半導体チップ２，２Ｂの対
応する各パッド２１＾〜２４Ａ、２１Ｂ〜２４ ａ間を
それぞれ接続する複数の金属細線４とを有する構造とな
っている。This embodiment includes a first semiconductor chip 2A mounted on an insulating substrate 1 and provided with a plurality of pads 21A to 24A for circuit connection at predetermined positions, and each pad 21A to 24A of this semiconductor chip 2A. A plurality of pads 218 to 24B for circuit connection provided in positions corresponding to and mirror-symmetrical to each other.
a second semiconductor chip 2B having the same function as the semiconductor chip 2A; A plurality of pattern wirings 3 for connecting between 218 to 24B, respectively, and corresponding pads 21^ to 24A, 21B to 24a of the first and second semiconductor chips 2 and 2B via these pattern wirings 3. It has a structure including a plurality of thin metal wires 4 connecting between the two.
第１図から分るように、対応するパッド２１Ａ２１Ｂ
、２２Ａ ２２ａ 、２３Ａ ２３Ｂ２４Ａ
２４８間をそれぞれ接続するパターン配線３及び金属
細線４は互いに交差することがないので、パターン配線
３を絶縁性基板１．の同一層内に形成することができ、
絶縁性基板１の層数を低減することができる。As can be seen from FIG. 1, the corresponding pads 21A21B
, 22A 22a , 23A 23B24A
Since the pattern wiring 3 and the thin metal wire 4 that respectively connect between the 248 and 248 do not cross each other, the pattern wiring 3 is connected to the insulating substrate 1. can be formed in the same layer of
The number of layers of the insulating substrate 1 can be reduced.
第２図は本発明を適用した完成状態の混成集積回路の断
面図である。FIG. 2 is a sectional view of a completed hybrid integrated circuit to which the present invention is applied.
半導体チップ２Ａ、２Ｂを搭載し配線した絶縁性基板１
は、リードフレーム５のアイランド部５１上に接着固定
され、絶縁性基板１上のパッドが金属細線４によりリー
ド端子５２に接続され、そして樹脂部６で封止される構
造となっている。Insulating substrate 1 on which semiconductor chips 2A and 2B are mounted and wired
is adhesively fixed onto an island portion 51 of a lead frame 5, a pad on an insulating substrate 1 is connected to a lead terminal 52 by a thin metal wire 4, and then sealed with a resin portion 6.
以上説明したように本発明は、対応するパッドを互いに
鏡映対称となる位置に配置した第１及び第２の半導体チ
ップを絶縁性基板上に搭載し、これら対応するバ・ｙド
間を絶縁性基板上に形成されたパターン配線と金属細線
とにより接続する構造とすることにより、これらパター
ン配線及び金属細線が互いに交差することがないのでパ
ターン配線を絶縁性基板の同一層内に形成することがで
き、従って絶縁性基板の層数を低減することができ、絶
縁性基板の製造コストを低減することができる効果があ
る。As explained above, the present invention mounts the first and second semiconductor chips, in which the corresponding pads are arranged in mirror-symmetrical positions to each other, on an insulating substrate, and insulates the corresponding pads from each other. By creating a structure in which the pattern wiring formed on the insulating substrate is connected to the thin metal wire, the pattern wiring and the thin metal wire do not cross each other, so the pattern wiring can be formed in the same layer of the insulating substrate. Therefore, the number of layers of the insulating substrate can be reduced, and the manufacturing cost of the insulating substrate can be reduced.
第１図及び第２図はそれぞれ本発明の一実施例を説明す
るための中間工程及び完成状態の混成集積回路装置の平
面図及び断面側面図、第３図は従来の混成集積回路装置
の一例の中間工程における平面図である。
１、ＬＡ’・・・絶縁性基板、２Ａ、２Ｂ・・・半導体
チップ、３，３Ａ・・・パターン配線、４・・・金属細
線、５・・・リードフレーム、６・・・樹脂部、２１Ａ
〜２４Ａ、２１Ｂ〜２４ ａ・・・パッド、５１・・・
アイランド部、５２・・・リード端子。1 and 2 are a plan view and a sectional side view of a hybrid integrated circuit device in an intermediate process and a completed state, respectively, for explaining an embodiment of the present invention, and FIG. 3 is an example of a conventional hybrid integrated circuit device. It is a top view in the intermediate process of. 1, LA'... Insulating substrate, 2A, 2B... Semiconductor chip, 3, 3A... Pattern wiring, 4... Metal thin wire, 5... Lead frame, 6... Resin part, 21A
~24A, 21B~24 a...pad, 51...
Island part, 52...Lead terminal.
Claims (1)
ッドを備えた第１の半導体チップと、前記各パッドと対
応しかつ互いに鏡映対称となる位置に設けられた回路接
続用の複数のパッドを備えた第２の半導体チップと、前
記第１及び第２の半導体チップの対応する各パッド間を
それぞれ接続するための複数のパターン配線と、これら
各パターン配線を介して前記第１及び第２の半導体チッ
プの対応する各パッド間をそれぞれ接続する複数の金属
細線とを有することを特徴とする混成集積回路装置。a first semiconductor chip provided with a plurality of pads for circuit connection at predetermined positions on an insulating substrate; and a plurality of pads for circuit connection provided at positions corresponding to and mirror-symmetrical to each of the pads. a second semiconductor chip having a pad, a plurality of pattern wirings for respectively connecting the corresponding pads of the first and second semiconductor chips, and a plurality of pattern wirings for respectively connecting the corresponding pads of the first and second semiconductor chips; A hybrid integrated circuit device comprising a plurality of thin metal wires connecting corresponding pads of a second semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63279856A JPH02125653A (en) | 1988-11-04 | 1988-11-04 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63279856A JPH02125653A (en) | 1988-11-04 | 1988-11-04 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02125653A true JPH02125653A (en) | 1990-05-14 |
Family
ID=17616898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63279856A Pending JPH02125653A (en) | 1988-11-04 | 1988-11-04 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02125653A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0954028A4 (en) * | 1996-11-12 | 2005-05-04 | Tif Co Ltd | Memory module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4989157A (en) * | 1972-12-29 | 1974-08-26 | ||
| JPS5248418B2 (en) * | 1975-11-07 | 1977-12-09 |
-
1988
- 1988-11-04 JP JP63279856A patent/JPH02125653A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4989157A (en) * | 1972-12-29 | 1974-08-26 | ||
| JPS5248418B2 (en) * | 1975-11-07 | 1977-12-09 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0954028A4 (en) * | 1996-11-12 | 2005-05-04 | Tif Co Ltd | Memory module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6290953A (en) | Resin-sealed semiconductor device | |
| KR20020062820A (en) | Semiconductor device having stacked multi chip module structure | |
| JPH1168026A (en) | Wiring auxiliary package and printed circuit wiring board structure | |
| JPH04273451A (en) | Semiconductor device | |
| JP2001156251A (en) | Semiconductor device | |
| JP3549714B2 (en) | Semiconductor device | |
| JPH02125653A (en) | Hybrid integrated circuit device | |
| JP2982182B2 (en) | Resin-sealed semiconductor device | |
| JP3227930B2 (en) | Composite semiconductor device and method of manufacturing the same | |
| JPS58178544A (en) | Lead frame | |
| JP3692353B2 (en) | Assembling method of semiconductor device | |
| JPH0482244A (en) | Semiconductor integrated circuit device and its wiring change method | |
| JPH06342874A (en) | Semiconductor device high in integration degree | |
| JP2505359Y2 (en) | Semiconductor mounting board | |
| JP2533810B2 (en) | Semiconductor device | |
| JPH0745780A (en) | Quad flat package for semiconductor device | |
| JP4229086B2 (en) | Semiconductor device | |
| JP2842592B2 (en) | Semiconductor integrated circuit device | |
| JPH02295144A (en) | Integrated circuit | |
| JPH07283274A (en) | Semiconductor device and junction seat | |
| JPH03236245A (en) | Semiconductor device | |
| JP2783233B2 (en) | LSI package | |
| JP2841459B2 (en) | Hybrid integrated circuit | |
| JPS62173728A (en) | Hybrid integrated circuit | |
| JPS6380543A (en) | Integrated circuit device |